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Support for 3 analog watchdogs in ADCv3 (STM32F3, L4, L4+, G4). 

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/branches/stable_20.3.x@13796 27425a3e-05d8-49a3-a47f-9c15f0e5edd8
This commit is contained in:
Giovanni Di Sirio 2020-07-31 08:32:07 +00:00
parent e33f4e43cc
commit c447c5b001
11 changed files with 190 additions and 75 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

11
os/hal/ports/STM32/LLD/ADCv3/hal_adc_lld.c
View File

@ -850,8 +850,17 @@ void adc_lld_start_conversion(ADCDriver *adcp) {
/* ADC setup, if it is defined a callback for the analog watch dog then it
is enabled.*/
adcp->adcm->ISR = adcp->adcm->ISR;
adcp->adcm->IER = ADC_IER_OVRIE | ADC_IER_AWD1IE;
if (grpp->error_cb != NULL) {
adcp->adcm->IER = ADC_IER_OVRIE | ADC_IER_AWD1IE
| ADC_IER_AWD2IE
| ADC_IER_AWD3IE;
adcp->adcm->TR1 = grpp->tr1;
adcp->adcm->TR2 = grpp->tr2;
adcp->adcm->TR3 = grpp->tr3;
adcp->adcm->AWD2CR = grpp->awd2cr;
adcp->adcm->AWD3CR = grpp->awd3cr;
}
#if STM32_ADC_DUAL_MODE
/* Configuring the CCR register with the user-specified settings

24
os/hal/ports/STM32/LLD/ADCv3/hal_adc_lld.h
View File

@ -855,6 +855,14 @@ typedef enum {
uint32_t cfgr2; \
/* ADC TR1 register initialization data.*/ \
uint32_t tr1; \
/* ADC TR2 register initialization data.*/ \
uint32_t tr2; \
/* ADC TR3 register initialization data.*/ \
uint32_t tr3; \
/* ADC AWD2CR register initialization data.*/ \
uint32_t awd2cr; \
/* ADC AWD3CR register initialization data.*/ \
uint32_t awd3cr; \
/* ADC CCR register initialization data. \
NOTE: Put this field to zero if not using oversampling.*/ \
uint32_t ccr; \
@ -873,6 +881,10 @@ typedef enum {
uint32_t cfgr; \
uint32_t cfgr2; \
uint32_t tr1; \
uint32_t tr2; \
uint32_t tr3; \
uint32_t awd2cr; \
uint32_t awd3cr; \
uint32_t smpr[2]; \
uint32_t sqr[4]
#endif /* STM32_ADC_DUAL_MODE == FALSE */
@ -882,6 +894,10 @@ typedef enum {
#define adc_lld_configuration_group_fields \
uint32_t cfgr; \
uint32_t tr1; \
uint32_t tr2; \
uint32_t tr3; \
uint32_t awd2cr; \
uint32_t awd3cr; \
uint32_t ccr; \
uint32_t smpr[2]; \
uint32_t sqr[4]; \
@ -891,16 +907,22 @@ typedef enum {
#define adc_lld_configuration_group_fields \
uint32_t cfgr; \
uint32_t tr1; \
uint32_t tr2; \
uint32_t tr3; \
uint32_t awd2cr; \
uint32_t awd3cr; \
uint32_t smpr[2]; \
uint32_t sqr[4]
#endif /* STM32_ADC_DUAL_MODE == FALSE */
#endif /* STM32_ADCV3_OVERSAMPLING == FALSE */
/**
* @name Threshold register initializer
* @name Threshold registers initializers
* @{
*/
#define ADC_TR(low, high) (((uint32_t)(high) << 16) | (uint32_t)(low))
#define ADC_TR_DISABLED ADC_TR(0U, 0x0FFFU)
#define ADC_AWDCR_ENABLE(n) (1U << (n))
/** @} */
/**

11
os/hal/ports/STM32/LLD/ADCv5/hal_adc_lld.c
View File

@ -294,11 +294,16 @@ void adc_lld_start_conversion(ADCDriver *adcp) {
/* ADC setup, if it is defined a callback for the analog watch dog then it
is enabled.*/
adcp->adc->ISR = adcp->adc->ISR;
adcp->adc->IER = ADC_IER_OVRIE |
ADC_IER_AWD1IE | ADC_IER_AWD2IE | ADC_IER_AWD3IE;
if (grpp->error_cb != NULL) {
adcp->adc->IER = ADC_IER_OVRIE | ADC_IER_AWD1IE
| ADC_IER_AWD2IE
| ADC_IER_AWD3IE;
adcp->adc->TR1 = grpp->tr1;
adcp->adc->TR2 = grpp->tr2;
adcp->adc->TR3 = grpp->tr3;
adcp->adc->AWD2CR = grpp->awd2cr;
adcp->adc->AWD3CR = grpp->awd3cr;
}
adcp->adc->SMPR = grpp->smpr;
adcp->adc->CHSELR = grpp->chselr;
@ -333,7 +338,7 @@ void adc_lld_stop_conversion(ADCDriver *adcp) {
void adc_lld_serve_interrupt(ADCDriver *adcp) {
uint32_t isr;
isr = adcp->adc->ISR & adcp->adc->IER;
isr = adcp->adc->ISR;
adcp->adc->ISR = isr;
/* It could be a spurious interrupt caused by overflows after DMA disabling,

38
os/hal/ports/STM32/LLD/ADCv5/hal_adc_lld.h
View File

@ -89,11 +89,43 @@
/** @} */
/**
* @name Threashold registers initializer
* @name CHSELR register initializers for CHSELRMOD=0
* @{
*/
#define ADC_CHSELR_CHSEL_N(n) (1U << (n))
/** @} */
/**
* @name CHSELR register initializers for CHSELRMOD=1
* @{
*/
#define ADC_CHSELR_SQ1_N(n) ((uint32_t)(n) << 0U)
#define ADC_CHSELR_SQ2_N(n) ((uint32_t)(n) << 4U)
#define ADC_CHSELR_SQ3_N(n) ((uint32_t)(n) << 8U)
#define ADC_CHSELR_SQ4_N(n) ((uint32_t)(n) << 12U)
#define ADC_CHSELR_SQ5_N(n) ((uint32_t)(n) << 16U)
#define ADC_CHSELR_SQ6_N(n) ((uint32_t)(n) << 20U)
#define ADC_CHSELR_SQ7_N(n) ((uint32_t)(n) << 24U)
#define ADC_CHSELR_SQ8_N(n) ((uint32_t)(n) << 28U)
#define ADC_CHSELR_SQ1_END (15U << 0U)
#define ADC_CHSELR_SQ2_END (15U << 4U)
#define ADC_CHSELR_SQ3_END (15U << 8U)
#define ADC_CHSELR_SQ4_END (15U << 12U)
#define ADC_CHSELR_SQ5_END (15U << 16U)
#define ADC_CHSELR_SQ6_END (15U << 20U)
#define ADC_CHSELR_SQ7_END (15U << 24U)
#define ADC_CHSELR_SQ8_END (15U << 28U)
/** @} */
/**
* @name Threshold registers initializers
* @{
*/
#define ADC_TR(low, high) (((uint32_t)(high) << 16U) | \
(uint32_t)(low))
#define ADC_TR_DISABLED ADC_TR(0U, 0x0FFFU)
#define ADC_AWDCR_ENABLE(n) (1U << (n))
/** @} */
/*===========================================================================*/
@ -313,6 +345,10 @@ typedef enum {
uint32_t tr2; \
/* ADC TR3 register initialization data.*/ \
uint32_t tr3; \
/* ADC AWD2CR register initialization data.*/ \
uint32_t awd2cr; \
/* ADC AWD3CR register initialization data.*/ \
uint32_t awd3cr; \
/* ADC SMPR register initialization data.*/ \
uint32_t smpr; \
/* ADC CHSELR register initialization data. \

3
readme.txt
View File

@ -74,7 +74,8 @@
*****************************************************************************
*** 20.3.2 ***
- NEW: Support for 3 analog watchdogs in STM32G0 ADC.
- NEW: Support for 3 analog watchdogs in ADCv3 (STM32F3, L4, L4+, G4).
- NEW: Support for 3 analog watchdogs in ADCv5 (STM32G0).
- NEW: Updated FatFS to version 0.14.
- NEW: Added a new setting to STM32 USBv1 allowing for some clock deviation
from 48MHz. Renamed setting USB_HOST_WAKEUP_DURATION to

46
testhal/STM32/STM32F3xx/ADC/main.c
View File

@ -52,17 +52,21 @@ static void adcerrorcallback(ADCDriver *adcp, adcerror_t err) {
* Channels: IN7, IN8.
*/
static const ADCConversionGroup adcgrpcfg1 = {
FALSE,
ADC_GRP1_NUM_CHANNELS,
NULL,
adcerrorcallback,
ADC_CFGR_CONT, /* CFGR */
ADC_TR(0, 4095), /* TR1 */
{ /* SMPR[2] */
.circular = false,
.num_channels = ADC_GRP1_NUM_CHANNELS,
.end_cb = NULL,
.error_cb = adcerrorcallback,
.cfgr = ADC_CFGR_CONT,
.tr1 = ADC_TR_DISABLED,
.tr2 = ADC_TR_DISABLED,
.tr3 = ADC_TR_DISABLED,
.awd2cr = 0U,
.awd3cr = 0U,
.smpr = {
0,
0
},
{ /* SQR[4] */
.sqr = {
ADC_SQR1_SQ1_N(ADC_CHANNEL_IN7) | ADC_SQR1_SQ2_N(ADC_CHANNEL_IN8),
0,
0,
@ -76,19 +80,21 @@ static const ADCConversionGroup adcgrpcfg1 = {
* Channels: IN7, IN8, IN7, IN8, IN7, IN8, Sensor, VBat/2.
*/
static const ADCConversionGroup adcgrpcfg2 = {
TRUE,
ADC_GRP2_NUM_CHANNELS,
adccallback,
adcerrorcallback,
ADC_CFGR_CONT, /* CFGR */
ADC_TR(0, 4095), /* TR1 */
{ /* SMPR[2] */
ADC_SMPR1_SMP_AN7(ADC_SMPR_SMP_19P5)
| ADC_SMPR1_SMP_AN8(ADC_SMPR_SMP_19P5),
ADC_SMPR2_SMP_AN16(ADC_SMPR_SMP_61P5)
| ADC_SMPR2_SMP_AN17(ADC_SMPR_SMP_61P5),
.circular = true,
.num_channels = ADC_GRP2_NUM_CHANNELS,
.end_cb = adccallback,
.error_cb = adcerrorcallback,
.cfgr = ADC_CFGR_CONT,
.tr1 = ADC_TR_DISABLED,
.tr2 = ADC_TR_DISABLED,
.tr3 = ADC_TR_DISABLED,
.awd2cr = 0U,
.awd3cr = 0U,
.smpr = {
ADC_SMPR1_SMP_AN7(ADC_SMPR_SMP_19P5) | ADC_SMPR1_SMP_AN8(ADC_SMPR_SMP_19P5),
ADC_SMPR2_SMP_AN16(ADC_SMPR_SMP_61P5) | ADC_SMPR2_SMP_AN17(ADC_SMPR_SMP_61P5),
},
{ /* SQR[4] */
.sqr = {
ADC_SQR1_SQ1_N(ADC_CHANNEL_IN7) | ADC_SQR1_SQ2_N(ADC_CHANNEL_IN8) |
ADC_SQR1_SQ3_N(ADC_CHANNEL_IN7) | ADC_SQR1_SQ4_N(ADC_CHANNEL_IN8),
ADC_SQR2_SQ5_N(ADC_CHANNEL_IN7) | ADC_SQR2_SQ6_N(ADC_CHANNEL_IN8) |

52
testhal/STM32/STM32F3xx/ADC_DUAL/main.c
View File

@ -52,28 +52,32 @@ static void adcerrorcallback(ADCDriver *adcp, adcerror_t err) {
* Channels: IN7, IN8.
*/
static const ADCConversionGroup adcgrpcfg1 = {
FALSE,
ADC_GRP1_NUM_CHANNELS,
NULL,
adcerrorcallback,
ADC_CFGR_CONT, /* CFGR */
ADC_TR(0, 4095), /* TR1 */
ADC_CCR_DUAL_FIELD(1), /* CCR */
{ /* SMPR[2] */
.circular = false,
.num_channels = ADC_GRP1_NUM_CHANNELS,
.end_cb = NULL,
.error_cb = adcerrorcallback,
.cfgr = ADC_CFGR_CONT,
.tr1 = ADC_TR_DISABLED,
.tr2 = ADC_TR_DISABLED,
.tr3 = ADC_TR_DISABLED,
.awd2cr = 0U,
.awd3cr = 0U,
.ccr = ADC_CCR_DUAL_FIELD(1),
.smpr = {
0,
0
},
{ /* SQR[4] */
.sqr = {
ADC_SQR1_SQ1_N(ADC_CHANNEL_IN7) | ADC_SQR1_SQ2_N(ADC_CHANNEL_IN8),
0,
0,
0
},
{ /* SSMPR[2] */
.ssmpr = {
0,
0
},
{ /* SSQR[4] */
.ssqr = {
ADC_SQR1_SQ1_N(ADC_CHANNEL_IN8) | ADC_SQR1_SQ2_N(ADC_CHANNEL_IN7),
0,
0,
@ -87,20 +91,24 @@ static const ADCConversionGroup adcgrpcfg1 = {
* Channels: IN7, IN8, IN7, IN8, IN7, IN8, Sensor, VBat/2.
*/
static const ADCConversionGroup adcgrpcfg2 = {
TRUE,
ADC_GRP2_NUM_CHANNELS,
adccallback,
adcerrorcallback,
ADC_CFGR_CONT, /* CFGR */
ADC_TR(0, 4095), /* TR1 */
ADC_CCR_DUAL_FIELD(1) | ADC_CCR_TSEN | ADC_CCR_VBATEN, /* CCR */
{ /* SMPR[2] */
.circular = true,
.num_channels = ADC_GRP2_NUM_CHANNELS,
.end_cb = adccallback,
.error_cb = adcerrorcallback,
.cfgr = ADC_CFGR_CONT,
.tr1 = ADC_TR_DISABLED,
.tr2 = ADC_TR_DISABLED,
.tr3 = ADC_TR_DISABLED,
.awd2cr = 0U,
.awd3cr = 0U,
.ccr = ADC_CCR_DUAL_FIELD(1) | ADC_CCR_TSEN | ADC_CCR_VBATEN,
.smpr = {
ADC_SMPR1_SMP_AN7(ADC_SMPR_SMP_19P5)
| ADC_SMPR1_SMP_AN8(ADC_SMPR_SMP_19P5),
ADC_SMPR2_SMP_AN16(ADC_SMPR_SMP_61P5)
| ADC_SMPR2_SMP_AN17(ADC_SMPR_SMP_61P5),
},
{ /* SQR[4] */
.sqr = {
ADC_SQR1_SQ1_N(ADC_CHANNEL_IN7) | ADC_SQR1_SQ2_N(ADC_CHANNEL_IN8) |
ADC_SQR1_SQ3_N(ADC_CHANNEL_IN7) | ADC_SQR1_SQ4_N(ADC_CHANNEL_IN8),
ADC_SQR2_SQ5_N(ADC_CHANNEL_IN7) | ADC_SQR2_SQ6_N(ADC_CHANNEL_IN8) |
@ -108,13 +116,13 @@ static const ADCConversionGroup adcgrpcfg2 = {
0,
0
},
{ /* SSMPR[2] */
.ssmpr = {
ADC_SMPR1_SMP_AN7(ADC_SMPR_SMP_19P5)
| ADC_SMPR1_SMP_AN8(ADC_SMPR_SMP_19P5),
ADC_SMPR2_SMP_AN16(ADC_SMPR_SMP_61P5)
| ADC_SMPR2_SMP_AN17(ADC_SMPR_SMP_61P5),
},
{ /* SSQR[4] */
.ssqr = {
ADC_SQR1_SQ1_N(ADC_CHANNEL_IN8) | ADC_SQR1_SQ2_N(ADC_CHANNEL_IN7) |
ADC_SQR1_SQ3_N(ADC_CHANNEL_IN8) | ADC_SQR1_SQ4_N(ADC_CHANNEL_IN7),
ADC_SQR2_SQ5_N(ADC_CHANNEL_IN8) | ADC_SQR2_SQ6_N(ADC_CHANNEL_IN7) |

32
testhal/STM32/multi/ADC/cfg/stm32g071rb_nucleo64/portab.c
View File

@ -65,13 +65,15 @@ const ADCConversionGroup portab_adcgrpcfg1 = {
.num_channels = ADC_GRP1_NUM_CHANNELS,
.end_cb = NULL,
.error_cb = adcerrorcallback,
.cfgr1 = ADC_CFGR1_CONT | ADC_CFGR1_RES_12BIT, /* CFGR1 */
.cfgr2 = 0, /* CFGR2 */
.tr1 = ADC_TR(0, 0), /* TR1 */
.tr2 = ADC_TR(0, 0), /* TR2 */
.tr3 = ADC_TR(0, 0), /* TR3 */
.smpr = ADC_SMPR_SMP_1P5, /* SMPR */
.chselr = ADC_CHSELR_CHSEL10 /* CHSELR */
.cfgr1 = ADC_CFGR1_CONT | ADC_CFGR1_RES_12BIT,
.cfgr2 = 0,
.tr1 = ADC_TR_DISABLED,
.tr2 = ADC_TR_DISABLED,
.tr3 = ADC_TR_DISABLED,
.awd2cr = 0U,
.awd3cr = 0U,
.smpr = ADC_SMPR_SMP_1P5,
.chselr = ADC_CHSELR_CHSEL10
};
/*
@ -87,14 +89,16 @@ const ADCConversionGroup portab_adcgrpcfg2 = {
.cfgr1 = ADC_CFGR1_CONT |
ADC_CFGR1_RES_12BIT |
ADC_CFGR1_EXTEN_RISING |
ADC_CFGR1_EXTSEL_SRC(0), /* CFGR1 */
.cfgr2 = 0, /* CFGR2 */
.tr1 = ADC_TR(0, 0), /* TR1 */
.tr2 = ADC_TR(0, 0), /* TR2 */
.tr3 = ADC_TR(0, 0), /* TR3 */
.smpr = ADC_SMPR_SMP_39P5, /* SMPR */
ADC_CFGR1_EXTSEL_SRC(0),
.cfgr2 = 0,
.tr1 = ADC_TR_DISABLED,
.tr2 = ADC_TR_DISABLED,
.tr3 = ADC_TR_DISABLED,
.awd2cr = 0U,
.awd3cr = 0U,
.smpr = ADC_SMPR_SMP_39P5,
.chselr = ADC_CHSELR_CHSEL10 | ADC_CHSELR_CHSEL11 |
ADC_CHSELR_CHSEL17 | ADC_CHSELR_CHSEL18 /* CHSELR */
ADC_CHSELR_CHSEL17 | ADC_CHSELR_CHSEL18
};
/*===========================================================================*/

12
testhal/STM32/multi/ADC/cfg/stm32g474re_nucleo64/portab.c
View File

@ -67,7 +67,11 @@ const ADCConversionGroup portab_adcgrpcfg1 = {
.error_cb = adcerrorcallback,
.cfgr = 0U,
.cfgr2 = 0U,
.tr1 = ADC_TR(0, 4095),
.tr1 = ADC_TR_DISABLED,
.tr2 = ADC_TR_DISABLED,
.tr3 = ADC_TR_DISABLED,
.awd2cr = 0U,
.awd3cr = 0U,
.smpr = {
ADC_SMPR1_SMP_AN1(ADC_SMPR_SMP_247P5) |
ADC_SMPR1_SMP_AN2(ADC_SMPR_SMP_247P5),
@ -94,7 +98,11 @@ const ADCConversionGroup portab_adcgrpcfg2 = {
.cfgr = ADC_CFGR_EXTEN_RISING |
ADC_CFGR_EXTSEL_SRC(12), /* TIM4_TRGO */
.cfgr2 = 0U,
.tr1 = ADC_TR(0, 4095),
.tr1 = ADC_TR_DISABLED,
.tr2 = ADC_TR_DISABLED,
.tr3 = ADC_TR_DISABLED,
.awd2cr = 0U,
.awd3cr = 0U,
.smpr = {
ADC_SMPR1_SMP_AN1(ADC_SMPR_SMP_247P5) |
ADC_SMPR1_SMP_AN2(ADC_SMPR_SMP_247P5),

12
testhal/STM32/multi/ADC/cfg/stm32l476_discovery/portab.c
View File

@ -67,7 +67,11 @@ const ADCConversionGroup portab_adcgrpcfg1 = {
.error_cb = adcerrorcallback,
.cfgr = 0U,
.cfgr2 = 0U,
.tr1 = ADC_TR(0, 4095),
.tr1 = ADC_TR_DISABLED,
.tr2 = ADC_TR_DISABLED,
.tr3 = ADC_TR_DISABLED,
.awd2cr = 0U,
.awd3cr = 0U,
.smpr = {
ADC_SMPR1_SMP_AN0(ADC_SMPR_SMP_247P5) |
ADC_SMPR1_SMP_AN5(ADC_SMPR_SMP_247P5),
@ -94,7 +98,11 @@ const ADCConversionGroup portab_adcgrpcfg2 = {
.cfgr = ADC_CFGR_EXTEN_RISING |
ADC_CFGR_EXTSEL_SRC(12), /* TIM4_TRGO */
.cfgr2 = 0U,
.tr1 = ADC_TR(0, 4095),
.tr1 = ADC_TR_DISABLED,
.tr2 = ADC_TR_DISABLED,
.tr3 = ADC_TR_DISABLED,
.awd2cr = 0U,
.awd3cr = 0U,
.smpr = {
ADC_SMPR1_SMP_AN0(ADC_SMPR_SMP_247P5) |
ADC_SMPR1_SMP_AN5(ADC_SMPR_SMP_247P5),

12
testhal/STM32/multi/ADC/cfg/stm32l4r5zi_nucleo144/portab.c
View File

@ -67,7 +67,11 @@ const ADCConversionGroup portab_adcgrpcfg1 = {
.error_cb = adcerrorcallback,
.cfgr = 0U,
.cfgr2 = 0U,
.tr1 = ADC_TR(0, 4095),
.tr1 = ADC_TR_DISABLED,
.tr2 = ADC_TR_DISABLED,
.tr3 = ADC_TR_DISABLED,
.awd2cr = 0U,
.awd3cr = 0U,
.smpr = {
ADC_SMPR1_SMP_AN0(ADC_SMPR_SMP_247P5) |
ADC_SMPR1_SMP_AN5(ADC_SMPR_SMP_247P5),
@ -94,7 +98,11 @@ const ADCConversionGroup portab_adcgrpcfg2 = {
.cfgr = ADC_CFGR_EXTEN_RISING |
ADC_CFGR_EXTSEL_SRC(12), /* TIM4_TRGO */
.cfgr2 = 0U,
.tr1 = ADC_TR(0, 4095),
.tr1 = ADC_TR_DISABLED,
.tr2 = ADC_TR_DISABLED,
.tr3 = ADC_TR_DISABLED,
.awd2cr = 0U,
.awd3cr = 0U,
.smpr = {
ADC_SMPR1_SMP_AN0(ADC_SMPR_SMP_247P5) |
ADC_SMPR1_SMP_AN5(ADC_SMPR_SMP_247P5),