removing e200 & adding simulator
This commit is contained in:
rusefi
Fabien Poussin
parent
52bdcab0db
commit
c44f635d70
|
|
@ -1,258 +0,0 @@
|
|||
/*
|
||||
ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
|
||||
|
||||
Licensed under the Apache License, Version 2.0 (the "License");
|
||||
you may not use this file except in compliance with the License.
|
||||
You may obtain a copy of the License at
|
||||
|
||||
http://www.apache.org/licenses/LICENSE-2.0
|
||||
|
||||
Unless required by applicable law or agreed to in writing, software
|
||||
distributed under the License is distributed on an "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
See the License for the specific language governing permissions and
|
||||
limitations under the License.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file CW/crt0.s
|
||||
* @brief Generic PowerPC startup file for CodeWarrior.
|
||||
*
|
||||
* @addtogroup PPC_CW_CORE
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Module constants. */
|
||||
/*===========================================================================*/
|
||||
|
||||
#if !defined(FALSE) || defined(__DOXYGEN__)
|
||||
#define FALSE 0
|
||||
#endif
|
||||
|
||||
#if !defined(TRUE) || defined(__DOXYGEN__)
|
||||
#define TRUE 1
|
||||
#endif
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Module pre-compile time settings. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @brief Stack segments initialization switch.
|
||||
*/
|
||||
#if !defined(CRT0_STACKS_FILL_PATTERN) || defined(__DOXYGEN__)
|
||||
#define CRT0_STACKS_FILL_PATTERN 0x55555555
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Stack segments initialization switch.
|
||||
*/
|
||||
#if !defined(CRT0_INIT_STACKS) || defined(__DOXYGEN__)
|
||||
#define CRT0_INIT_STACKS TRUE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief DATA segment initialization switch.
|
||||
*/
|
||||
#if !defined(CRT0_INIT_DATA) || defined(__DOXYGEN__)
|
||||
#define CRT0_INIT_DATA TRUE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief BSS segment initialization switch.
|
||||
*/
|
||||
#if !defined(CRT0_INIT_BSS) || defined(__DOXYGEN__)
|
||||
#define CRT0_INIT_BSS TRUE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Constructors invocation switch.
|
||||
*/
|
||||
#if !defined(CRT0_CALL_CONSTRUCTORS) || defined(__DOXYGEN__)
|
||||
#define CRT0_CALL_CONSTRUCTORS FALSE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Destructors invocation switch.
|
||||
*/
|
||||
#if !defined(CRT0_CALL_DESTRUCTORS) || defined(__DOXYGEN__)
|
||||
#define CRT0_CALL_DESTRUCTORS FALSE
|
||||
#endif
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Code section. */
|
||||
/*===========================================================================*/
|
||||
|
||||
#if !defined(__DOXYGEN__)
|
||||
.extern __sdata2_start__
|
||||
.extern __sdata_start__
|
||||
.extern __bss_start__
|
||||
.extern __bss_end__
|
||||
.extern __irq_stack_base__
|
||||
.extern __irq_stack_end__
|
||||
.extern __process_stack_end__
|
||||
.extern __process_stack_base__
|
||||
.extern __romdata_start__
|
||||
.extern __data_start__
|
||||
.extern __data_end__
|
||||
.extern __init_array_start
|
||||
.extern __init_array_end
|
||||
.extern __fini_array_start
|
||||
.extern __fini_array_end
|
||||
|
||||
.extern main
|
||||
|
||||
.section .crt0, text_vle
|
||||
.align 16
|
||||
.globl _boot_address
|
||||
.type _boot_address, @function
|
||||
_boot_address:
|
||||
/* Stack setup.*/
|
||||
e_lis r1, __process_stack_end__@h
|
||||
e_or2i r1, __process_stack_end__@l
|
||||
se_li r0, 0
|
||||
e_stwu r0, -8(r1)
|
||||
|
||||
/* Small sections registers initialization.*/
|
||||
e_lis r2, __sdata2_start__@h
|
||||
e_or2i r2, __sdata2_start__@l
|
||||
e_lis r13, __sdata_start__@h
|
||||
e_or2i r13, __sdata_start__@l
|
||||
|
||||
/* Early initialization.*/
|
||||
e_bl __early_init
|
||||
|
||||
#if CRT0_INIT_STACKS == TRUE
|
||||
/* Stacks fill pattern.*/
|
||||
e_lis r7, CRT0_STACKS_FILL_PATTERN@h
|
||||
e_or2i r7, CRT0_STACKS_FILL_PATTERN@l
|
||||
|
||||
/* IRQ Stack initialization. Note, the architecture does not use this
|
||||
stack, the size is usually zero. An OS can have special SW handling
|
||||
and require this. A 4 bytes alignment is assumed and required.*/
|
||||
e_lis r4, __irq_stack_base__@h
|
||||
e_or2i r4, __irq_stack_base__@l
|
||||
e_lis r5, __irq_stack_end__@h
|
||||
e_or2i r5, __irq_stack_end__@l
|
||||
.irqsloop:
|
||||
se_cmpl r4, r5
|
||||
se_bge .irqsend
|
||||
se_stw r7, 0(r4)
|
||||
se_addi r4, 4
|
||||
se_b .irqsloop
|
||||
.irqsend:
|
||||
|
||||
/* Process Stack initialization. Note, does not overwrite the already
|
||||
written EABI frame. A 4 bytes alignment is assumed and required.*/
|
||||
e_lis r4, __process_stack_base__@h
|
||||
e_or2i r4, __process_stack_base__@l
|
||||
e_lis r5, (__process_stack_end__ - 8)@h
|
||||
e_or2i r5, (__process_stack_end__ - 8)@l
|
||||
.prcsloop:
|
||||
se_cmpl r4, r5
|
||||
se_bge .prcsend
|
||||
se_stw r7, 0(r4)
|
||||
se_addi r4, 4
|
||||
se_b .prcsloop
|
||||
.prcsend:
|
||||
#endif
|
||||
|
||||
#if CRT0_INIT_BSS == TRUE
|
||||
/* BSS clearing.*/
|
||||
e_lis r4, __bss_start__@h
|
||||
e_or2i r4, __bss_start__@l
|
||||
e_lis r5, __bss_end__@h
|
||||
e_or2i r5, __bss_end__@l
|
||||
se_li r7, 0
|
||||
.bssloop:
|
||||
se_cmpl r4, r5
|
||||
se_bge .bssend
|
||||
se_stw r7, 0(r4)
|
||||
se_addi r4, 4
|
||||
se_b .bssloop
|
||||
.bssend:
|
||||
#endif
|
||||
|
||||
#if CRT0_INIT_DATA == TRUE
|
||||
/* DATA initialization.*/
|
||||
e_lis r4, __romdata_start__@h
|
||||
e_or2i r4, __romdata_start__@l
|
||||
e_lis r5, __data_start__@h
|
||||
e_or2i r5, __data_start__@l
|
||||
e_lis r6, __data_end__@h
|
||||
e_or2i r6, __data_end__@l
|
||||
.dataloop:
|
||||
se_cmpl r5, r6
|
||||
se_bge .dataend
|
||||
se_lwz r7, 0(r4)
|
||||
se_addi r4, 4
|
||||
se_stw r7, 0(r5)
|
||||
se_addi r5, 4
|
||||
se_b .dataloop
|
||||
.dataend:
|
||||
#endif
|
||||
|
||||
/* Late initialization.*/
|
||||
e_bl __late_init
|
||||
|
||||
#if CRT0_CALL_CONSTRUCTORS == TRUE
|
||||
/* Constructors invocation.*/
|
||||
e_lis r4, __init_array_start@h
|
||||
e_or2i r4, __init_array_start@l
|
||||
e_lis r5, __init_array_end@h
|
||||
e_or2i r5, __init_array_end@l
|
||||
.iniloop:
|
||||
se_cmpl r4, r5
|
||||
se_bge .iniend
|
||||
se_lwz r6, 0(r4)
|
||||
se_mtctr r6
|
||||
se_addi r4, 4
|
||||
se_bctrl
|
||||
se_b .iniloop
|
||||
.iniend:
|
||||
#endif
|
||||
|
||||
/* Main program invocation.*/
|
||||
e_bl main
|
||||
|
||||
#if CRT0_CALL_DESTRUCTORS == TRUE
|
||||
/* Destructors invocation.*/
|
||||
e_lis r4, __fini_array_start@h
|
||||
e_or2i r4, __fini_array_start@l
|
||||
e_lis r5, __fini_array_end@h
|
||||
e_or2i r5, __fini_array_end@l
|
||||
.finiloop:
|
||||
se_cmpl r4, r5
|
||||
se_bge .finiend
|
||||
se_lwz r6, 0(r4)
|
||||
se_mtctr r6
|
||||
se_addi r4, 4
|
||||
se_bctrl
|
||||
se_b .finiloop
|
||||
.finiend:
|
||||
#endif
|
||||
|
||||
/* Branching to the defined exit handler.*/
|
||||
e_b __default_exit
|
||||
|
||||
#endif /* !defined(__DOXYGEN__) */
|
||||
|
||||
.section .text_vle
|
||||
.align 4
|
||||
|
||||
/* Default main exit code, infinite loop.*/
|
||||
.weak __default_exit
|
||||
__default_exit:
|
||||
e_b __default_exit
|
||||
|
||||
/* Default early initialization code, none.*/
|
||||
.weak __early_init
|
||||
se_blr
|
||||
|
||||
/* Default late initialization code, none.*/
|
||||
.weak __late_init
|
||||
__late_init:
|
||||
se_blr
|
||||
|
||||
/** @} */
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -1,78 +0,0 @@
|
|||
/*
|
||||
ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
|
||||
|
||||
Licensed under the Apache License, Version 2.0 (the "License");
|
||||
you may not use this file except in compliance with the License.
|
||||
You may obtain a copy of the License at
|
||||
|
||||
http://www.apache.org/licenses/LICENSE-2.0
|
||||
|
||||
Unless required by applicable law or agreed to in writing, software
|
||||
distributed under the License is distributed on an "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
See the License for the specific language governing permissions and
|
||||
limitations under the License.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file vectors.h
|
||||
* @brief ISR vector module header.
|
||||
*
|
||||
* @addtogroup PPC_CW_CORE
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifndef _VECTORS_H_
|
||||
#define _VECTORS_H_
|
||||
|
||||
#include "ppcparams.h"
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Module constants. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Module pre-compile time settings. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Derived constants and error checks. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Module data structures and types. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Module macros. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* External declarations. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/* The following code is not processed when the file is included from an
|
||||
asm module.*/
|
||||
#if !defined(_FROM_ASM_)
|
||||
|
||||
#if !defined(__DOXYGEN__)
|
||||
extern uint32_t _vectors[PPC_NUM_VECTORS];
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
void _unhandled_irq(void);
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* !defined(_FROM_ASM_) */
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Module inline functions. */
|
||||
/*===========================================================================*/
|
||||
|
||||
#endif /* _VECTORS_H_ */
|
||||
|
||||
/** @} */
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -1,242 +0,0 @@
|
|||
/*
|
||||
ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
|
||||
|
||||
Licensed under the Apache License, Version 2.0 (the "License");
|
||||
you may not use this file except in compliance with the License.
|
||||
You may obtain a copy of the License at
|
||||
|
||||
http://www.apache.org/licenses/LICENSE-2.0
|
||||
|
||||
Unless required by applicable law or agreed to in writing, software
|
||||
distributed under the License is distributed on an "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
See the License for the specific language governing permissions and
|
||||
limitations under the License.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file GCC/crt0.s
|
||||
* @brief Generic PowerPC startup file for GCC.
|
||||
*
|
||||
* @addtogroup PPC_GCC_CORE
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Module constants. */
|
||||
/*===========================================================================*/
|
||||
|
||||
#if !defined(FALSE) || defined(__DOXYGEN__)
|
||||
#define FALSE 0
|
||||
#endif
|
||||
|
||||
#if !defined(TRUE) || defined(__DOXYGEN__)
|
||||
#define TRUE 1
|
||||
#endif
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Module pre-compile time settings. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @brief Stack segments initialization switch.
|
||||
*/
|
||||
#if !defined(CRT0_STACKS_FILL_PATTERN) || defined(__DOXYGEN__)
|
||||
#define CRT0_STACKS_FILL_PATTERN 0x55555555
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Stack segments initialization switch.
|
||||
*/
|
||||
#if !defined(CRT0_INIT_STACKS) || defined(__DOXYGEN__)
|
||||
#define CRT0_INIT_STACKS TRUE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief DATA segment initialization switch.
|
||||
*/
|
||||
#if !defined(CRT0_INIT_DATA) || defined(__DOXYGEN__)
|
||||
#define CRT0_INIT_DATA TRUE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief BSS segment initialization switch.
|
||||
*/
|
||||
#if !defined(CRT0_INIT_BSS) || defined(__DOXYGEN__)
|
||||
#define CRT0_INIT_BSS TRUE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Constructors invocation switch.
|
||||
*/
|
||||
#if !defined(CRT0_CALL_CONSTRUCTORS) || defined(__DOXYGEN__)
|
||||
#define CRT0_CALL_CONSTRUCTORS TRUE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Destructors invocation switch.
|
||||
*/
|
||||
#if !defined(CRT0_CALL_DESTRUCTORS) || defined(__DOXYGEN__)
|
||||
#define CRT0_CALL_DESTRUCTORS TRUE
|
||||
#endif
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Code section. */
|
||||
/*===========================================================================*/
|
||||
|
||||
#if !defined(__DOXYGEN__)
|
||||
|
||||
.section .crt0, "ax"
|
||||
.align 2
|
||||
.globl _boot_address
|
||||
.type _boot_address, @function
|
||||
_boot_address:
|
||||
/* Stack setup.*/
|
||||
lis %r1, __process_stack_end__@h
|
||||
ori %r1, %r1, __process_stack_end__@l
|
||||
li %r0, 0
|
||||
stwu %r0, -8(%r1)
|
||||
|
||||
/* Small sections registers initialization.*/
|
||||
lis %r2, __sdata2_start__@h
|
||||
ori %r2, %r2, __sdata2_start__@l
|
||||
lis %r13, __sdata_start__@h
|
||||
ori %r13, %r13, __sdata_start__@l
|
||||
|
||||
/* Early initialization.*/
|
||||
bl __early_init
|
||||
|
||||
#if CRT0_INIT_STACKS == TRUE
|
||||
/* Stacks fill pattern.*/
|
||||
lis %r7, CRT0_STACKS_FILL_PATTERN@h
|
||||
ori %r7, %r7, CRT0_STACKS_FILL_PATTERN@l
|
||||
|
||||
/* IRQ Stack initialization. Note, the architecture does not use this
|
||||
stack, the size is usually zero. An OS can have special SW handling
|
||||
and require this. A 4 bytes alignment is assmend and required.*/
|
||||
lis %r4, __irq_stack_base__@h
|
||||
ori %r4, %r4, __irq_stack_base__@l
|
||||
lis %r5, __irq_stack_end__@h
|
||||
ori %r5, %r5, __irq_stack_end__@l
|
||||
.irqsloop:
|
||||
cmpl cr0, %r4, %r5
|
||||
bge cr0, .irqsend
|
||||
stw %r7, 0(%r4)
|
||||
addi %r4, %r4, 4
|
||||
b .irqsloop
|
||||
.irqsend:
|
||||
|
||||
/* Process Stack initialization. Note, does not overwrite the already
|
||||
written EABI frame. A 4 bytes alignment is assmend and required.*/
|
||||
lis %r4, __process_stack_base__@h
|
||||
ori %r4, %r4, __process_stack_base__@l
|
||||
lis %r5, (__process_stack_end__ - 8)@h
|
||||
ori %r5, %r5, (__process_stack_end__ - 8)@l
|
||||
.prcsloop:
|
||||
cmpl cr0, %r4, %r5
|
||||
bge cr0, .prcsend
|
||||
stw %r7, 0(%r4)
|
||||
addi %r4, %r4, 4
|
||||
b .prcsloop
|
||||
.prcsend:
|
||||
#endif
|
||||
|
||||
#if CRT0_INIT_BSS == TRUE
|
||||
/* BSS clearing.*/
|
||||
lis %r4, __bss_start__@h
|
||||
ori %r4, %r4, __bss_start__@l
|
||||
lis %r5, __bss_end__@h
|
||||
ori %r5, %r5, __bss_end__@l
|
||||
li %r7, 0
|
||||
.bssloop:
|
||||
cmpl cr0, %r4, %r5
|
||||
bge cr0, .bssend
|
||||
stw %r7, 0(%r4)
|
||||
addi %r4, %r4, 4
|
||||
b .bssloop
|
||||
.bssend:
|
||||
#endif
|
||||
|
||||
#if CRT0_INIT_DATA == TRUE
|
||||
/* DATA initialization.*/
|
||||
lis %r4, __romdata_start__@h
|
||||
ori %r4, %r4, __romdata_start__@l
|
||||
lis %r5, __data_start__@h
|
||||
ori %r5, %r5, __data_start__@l
|
||||
lis %r6, __data_end__@h
|
||||
ori %r6, %r6, __data_end__@l
|
||||
.dataloop:
|
||||
cmpl cr0, %r5, %r6
|
||||
bge cr0, .dataend
|
||||
lwz %r7, 0(%r4)
|
||||
addi %r4, %r4, 4
|
||||
stw %r7, 0(%r5)
|
||||
addi %r5, %r5, 4
|
||||
b .dataloop
|
||||
.dataend:
|
||||
#endif
|
||||
|
||||
/* Late initialization.*/
|
||||
bl __late_init
|
||||
|
||||
#if CRT0_CALL_CONSTRUCTORS == TRUE
|
||||
/* Constructors invocation.*/
|
||||
lis %r4, __init_array_start@h
|
||||
ori %r4, %r4, __init_array_start@l
|
||||
lis %r5, __init_array_end@h
|
||||
ori %r5, %r5, __init_array_end@l
|
||||
.iniloop:
|
||||
cmplw %cr0, %r4, %r5
|
||||
bge %cr0, .iniend
|
||||
lwz %r6, 0(%r4)
|
||||
mtctr %r6
|
||||
addi %r4, %r4, 4
|
||||
bctrl
|
||||
b .iniloop
|
||||
.iniend:
|
||||
#endif
|
||||
|
||||
/* Main program invocation.*/
|
||||
bl main
|
||||
|
||||
#if CRT0_CALL_DESTRUCTORS == TRUE
|
||||
/* Destructors invocation.*/
|
||||
lis %r4, __fini_array_start@h
|
||||
ori %r4, %r4, __fini_array_start@l
|
||||
lis %r5, __fini_array_end@h
|
||||
ori %r5, %r5, __fini_array_end@l
|
||||
.finiloop:
|
||||
cmplw %cr0, %r4, %r5
|
||||
bge %cr0, .finiend
|
||||
lwz %r6, 0(%r4)
|
||||
mtctr %r6
|
||||
addi %r4, %r4, 4
|
||||
bctrl
|
||||
b .finiloop
|
||||
.finiend:
|
||||
#endif
|
||||
|
||||
/* Branching to the defined exit handler.*/
|
||||
b __default_exit
|
||||
|
||||
/* Default main exit code, infinite loop.*/
|
||||
.weak __default_exit
|
||||
.type __default_exit, @function
|
||||
__default_exit:
|
||||
b __default_exit
|
||||
|
||||
/* Default early initialization code, none.*/
|
||||
.weak __early_init
|
||||
.type __early_init, @function
|
||||
__early_init:
|
||||
blr
|
||||
|
||||
/* Default late initialization code, none.*/
|
||||
.weak __late_init
|
||||
.type __late_init, @function
|
||||
__late_init:
|
||||
blr
|
||||
|
||||
#endif /* !defined(__DOXYGEN__) */
|
||||
|
||||
/** @} */
|
||||
|
|
@ -1,27 +0,0 @@
|
|||
/*
|
||||
ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
|
||||
|
||||
Licensed under the Apache License, Version 2.0 (the "License");
|
||||
you may not use this file except in compliance with the License.
|
||||
You may obtain a copy of the License at
|
||||
|
||||
http://www.apache.org/licenses/LICENSE-2.0
|
||||
|
||||
Unless required by applicable law or agreed to in writing, software
|
||||
distributed under the License is distributed on an "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
See the License for the specific language governing permissions and
|
||||
limitations under the License.
|
||||
*/
|
||||
|
||||
/*
|
||||
* SPC560B50 memory setup.
|
||||
*/
|
||||
MEMORY
|
||||
{
|
||||
flash : org = 0x00000000, len = 512k
|
||||
dataflash : org = 0x00800000, len = 64k
|
||||
ram : org = 0x40000000, len = 32k
|
||||
}
|
||||
|
||||
INCLUDE rules_z0.ld
|
||||
|
|
@ -1,27 +0,0 @@
|
|||
/*
|
||||
ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
|
||||
|
||||
Licensed under the Apache License, Version 2.0 (the "License");
|
||||
you may not use this file except in compliance with the License.
|
||||
You may obtain a copy of the License at
|
||||
|
||||
http://www.apache.org/licenses/LICENSE-2.0
|
||||
|
||||
Unless required by applicable law or agreed to in writing, software
|
||||
distributed under the License is distributed on an "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
See the License for the specific language governing permissions and
|
||||
limitations under the License.
|
||||
*/
|
||||
|
||||
/*
|
||||
* SPC560B60 memory setup.
|
||||
*/
|
||||
MEMORY
|
||||
{
|
||||
flash : org = 0x00000000, len = 1024k
|
||||
dataflash : org = 0x00800000, len = 64k
|
||||
ram : org = 0x40000000, len = 80k
|
||||
}
|
||||
|
||||
INCLUDE rules_z0.ld
|
||||
|
|
@ -1,27 +0,0 @@
|
|||
/*
|
||||
ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
|
||||
|
||||
Licensed under the Apache License, Version 2.0 (the "License");
|
||||
you may not use this file except in compliance with the License.
|
||||
You may obtain a copy of the License at
|
||||
|
||||
http://www.apache.org/licenses/LICENSE-2.0
|
||||
|
||||
Unless required by applicable law or agreed to in writing, software
|
||||
distributed under the License is distributed on an "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
See the License for the specific language governing permissions and
|
||||
limitations under the License.
|
||||
*/
|
||||
|
||||
/*
|
||||
* SPC560B64 memory setup.
|
||||
*/
|
||||
MEMORY
|
||||
{
|
||||
flash : org = 0x00000000, len = 1536k
|
||||
dataflash : org = 0x00800000, len = 64k
|
||||
ram : org = 0x40000000, len = 96k
|
||||
}
|
||||
|
||||
INCLUDE rules_z0.ld
|
||||
|
|
@ -1,27 +0,0 @@
|
|||
/*
|
||||
ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
|
||||
|
||||
Licensed under the Apache License, Version 2.0 (the "License");
|
||||
you may not use this file except in compliance with the License.
|
||||
You may obtain a copy of the License at
|
||||
|
||||
http://www.apache.org/licenses/LICENSE-2.0
|
||||
|
||||
Unless required by applicable law or agreed to in writing, software
|
||||
distributed under the License is distributed on an "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
See the License for the specific language governing permissions and
|
||||
limitations under the License.
|
||||
*/
|
||||
|
||||
/*
|
||||
* SPC560D40 memory setup.
|
||||
*/
|
||||
MEMORY
|
||||
{
|
||||
flash : org = 0x00000000, len = 256k
|
||||
dataflash : org = 0x00800000, len = 64k
|
||||
ram : org = 0x40000000, len = 16k
|
||||
}
|
||||
|
||||
INCLUDE rules_z0.ld
|
||||
|
|
@ -1,27 +0,0 @@
|
|||
/*
|
||||
ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
|
||||
|
||||
Licensed under the Apache License, Version 2.0 (the "License");
|
||||
you may not use this file except in compliance with the License.
|
||||
You may obtain a copy of the License at
|
||||
|
||||
http://www.apache.org/licenses/LICENSE-2.0
|
||||
|
||||
Unless required by applicable law or agreed to in writing, software
|
||||
distributed under the License is distributed on an "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
See the License for the specific language governing permissions and
|
||||
limitations under the License.
|
||||
*/
|
||||
|
||||
/*
|
||||
* SPC560P50 memory setup.
|
||||
*/
|
||||
MEMORY
|
||||
{
|
||||
flash : org = 0x00000000, len = 512k
|
||||
dataflash : org = 0x00800000, len = 64k
|
||||
ram : org = 0x40000000, len = 40k
|
||||
}
|
||||
|
||||
INCLUDE rules_z0.ld
|
||||
|
|
@ -1,26 +0,0 @@
|
|||
/*
|
||||
ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
|
||||
|
||||
Licensed under the Apache License, Version 2.0 (the "License");
|
||||
you may not use this file except in compliance with the License.
|
||||
You may obtain a copy of the License at
|
||||
|
||||
http://www.apache.org/licenses/LICENSE-2.0
|
||||
|
||||
Unless required by applicable law or agreed to in writing, software
|
||||
distributed under the License is distributed on an "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
See the License for the specific language governing permissions and
|
||||
limitations under the License.
|
||||
*/
|
||||
|
||||
/*
|
||||
* SPC563M64 memory setup.
|
||||
*/
|
||||
MEMORY
|
||||
{
|
||||
flash : org = 0x00000000, len = 1536k
|
||||
ram : org = 0x40000000, len = 94k
|
||||
}
|
||||
|
||||
INCLUDE rules_z3.ld
|
||||
|
|
@ -1,26 +0,0 @@
|
|||
/*
|
||||
ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
|
||||
|
||||
Licensed under the Apache License, Version 2.0 (the "License");
|
||||
you may not use this file except in compliance with the License.
|
||||
You may obtain a copy of the License at
|
||||
|
||||
http://www.apache.org/licenses/LICENSE-2.0
|
||||
|
||||
Unless required by applicable law or agreed to in writing, software
|
||||
distributed under the License is distributed on an "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
See the License for the specific language governing permissions and
|
||||
limitations under the License.
|
||||
*/
|
||||
|
||||
/*
|
||||
* SPC563A70 memory setup.
|
||||
*/
|
||||
MEMORY
|
||||
{
|
||||
flash : org = 0x00000000, len = 2M
|
||||
ram : org = 0x40000000, len = 128k
|
||||
}
|
||||
|
||||
INCLUDE rules_z4.ld
|
||||
|
|
@ -1,26 +0,0 @@
|
|||
/*
|
||||
ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
|
||||
|
||||
Licensed under the Apache License, Version 2.0 (the "License");
|
||||
you may not use this file except in compliance with the License.
|
||||
You may obtain a copy of the License at
|
||||
|
||||
http://www.apache.org/licenses/LICENSE-2.0
|
||||
|
||||
Unless required by applicable law or agreed to in writing, software
|
||||
distributed under the License is distributed on an "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
See the License for the specific language governing permissions and
|
||||
limitations under the License.
|
||||
*/
|
||||
|
||||
/*
|
||||
* SPC563A80 memory setup.
|
||||
*/
|
||||
MEMORY
|
||||
{
|
||||
flash : org = 0x00000000, len = 4M
|
||||
ram : org = 0x40000000, len = 192k
|
||||
}
|
||||
|
||||
INCLUDE rules_z4.ld
|
||||
|
|
@ -1,27 +0,0 @@
|
|||
/*
|
||||
ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
|
||||
|
||||
Licensed under the Apache License, Version 2.0 (the "License");
|
||||
you may not use this file except in compliance with the License.
|
||||
You may obtain a copy of the License at
|
||||
|
||||
http://www.apache.org/licenses/LICENSE-2.0
|
||||
|
||||
Unless required by applicable law or agreed to in writing, software
|
||||
distributed under the License is distributed on an "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
See the License for the specific language governing permissions and
|
||||
limitations under the License.
|
||||
*/
|
||||
|
||||
/*
|
||||
* SPC56EC74 memory setup.
|
||||
*/
|
||||
MEMORY
|
||||
{
|
||||
flash : org = 0x00000000, len = 3M
|
||||
dataflash : org = 0x00800000, len = 64k
|
||||
ram : org = 0x40000000, len = 256k
|
||||
}
|
||||
|
||||
INCLUDE rules_z4.ld
|
||||
|
|
@ -1,26 +0,0 @@
|
|||
/*
|
||||
ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
|
||||
|
||||
Licensed under the Apache License, Version 2.0 (the "License");
|
||||
you may not use this file except in compliance with the License.
|
||||
You may obtain a copy of the License at
|
||||
|
||||
http://www.apache.org/licenses/LICENSE-2.0
|
||||
|
||||
Unless required by applicable law or agreed to in writing, software
|
||||
distributed under the License is distributed on an "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
See the License for the specific language governing permissions and
|
||||
limitations under the License.
|
||||
*/
|
||||
|
||||
/*
|
||||
* SPC56EL54 memory setup in LSM mode.
|
||||
*/
|
||||
MEMORY
|
||||
{
|
||||
flash : org = 0x00000000, len = 768k
|
||||
ram : org = 0x40000000, len = 128k
|
||||
}
|
||||
|
||||
INCLUDE rules_z4.ld
|
||||
|
|
@ -1,26 +0,0 @@
|
|||
/*
|
||||
ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
|
||||
|
||||
Licensed under the Apache License, Version 2.0 (the "License");
|
||||
you may not use this file except in compliance with the License.
|
||||
You may obtain a copy of the License at
|
||||
|
||||
http://www.apache.org/licenses/LICENSE-2.0
|
||||
|
||||
Unless required by applicable law or agreed to in writing, software
|
||||
distributed under the License is distributed on an "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
See the License for the specific language governing permissions and
|
||||
limitations under the License.
|
||||
*/
|
||||
|
||||
/*
|
||||
* SPC56EL60 memory setup in LSM mode.
|
||||
*/
|
||||
MEMORY
|
||||
{
|
||||
flash : org = 0x00000000, len = 1M
|
||||
ram : org = 0x40000000, len = 128k
|
||||
}
|
||||
|
||||
INCLUDE rules_z4.ld
|
||||
|
|
@ -1,26 +0,0 @@
|
|||
/*
|
||||
ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
|
||||
|
||||
Licensed under the Apache License, Version 2.0 (the "License");
|
||||
you may not use this file except in compliance with the License.
|
||||
You may obtain a copy of the License at
|
||||
|
||||
http://www.apache.org/licenses/LICENSE-2.0
|
||||
|
||||
Unless required by applicable law or agreed to in writing, software
|
||||
distributed under the License is distributed on an "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
See the License for the specific language governing permissions and
|
||||
limitations under the License.
|
||||
*/
|
||||
|
||||
/*
|
||||
* SPC56EL70 memory setup in LSM mode.
|
||||
*/
|
||||
MEMORY
|
||||
{
|
||||
flash : org = 0x00000000, len = 2M
|
||||
ram : org = 0x40000000, len = 192k
|
||||
}
|
||||
|
||||
INCLUDE rules_z4.ld
|
||||
|
|
@ -1,28 +0,0 @@
|
|||
/*
|
||||
ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
|
||||
|
||||
Licensed under the Apache License, Version 2.0 (the "License");
|
||||
you may not use this file except in compliance with the License.
|
||||
You may obtain a copy of the License at
|
||||
|
||||
http://www.apache.org/licenses/LICENSE-2.0
|
||||
|
||||
Unless required by applicable law or agreed to in writing, software
|
||||
distributed under the License is distributed on an "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
See the License for the specific language governing permissions and
|
||||
limitations under the License.
|
||||
*/
|
||||
|
||||
/*
|
||||
* SPC57EM80-HSM memory setup.
|
||||
*/
|
||||
MEMORY
|
||||
{
|
||||
flash : org = 0x0060C000, len = 144k
|
||||
dflash0 : org = 0x00680000, len = 16k
|
||||
dflash1 : org = 0x00684000, len = 16k
|
||||
ram : org = 0xA0000000, len = 40k
|
||||
}
|
||||
|
||||
INCLUDE rules_z0.ld
|
||||
|
|
@ -1,11 +0,0 @@
|
|||
# List of the ChibiOS e200z0 SPC560BCxx startup files.
|
||||
STARTUPSRC =
|
||||
|
||||
STARTUPASM = $(CHIBIOS)/os/common/ports/e200/devices/SPC560BCxx/boot.s \
|
||||
$(CHIBIOS)/os/common/ports/e200/compilers/GCC/vectors.s \
|
||||
$(CHIBIOS)/os/common/ports/e200/compilers/GCC/crt0.s
|
||||
|
||||
STARTUPINC = ${CHIBIOS}/os/common/ports/e200/compilers/GCC \
|
||||
${CHIBIOS}/os/common/ports/e200/devices/SPC560BCxx
|
||||
|
||||
STARTUPLD = ${CHIBIOS}/os/common/ports/e200/compilers/GCC/ld
|
||||
|
|
@ -1,11 +0,0 @@
|
|||
# List of the ChibiOS e200z0 SPC560Bxx startup files.
|
||||
STARTUPSRC =
|
||||
|
||||
STARTUPASM = $(CHIBIOS)/os/common/ports/e200/devices/SPC560Bxx/boot.s \
|
||||
$(CHIBIOS)/os/common/ports/e200/compilers/GCC/vectors.s \
|
||||
$(CHIBIOS)/os/common/ports/e200/compilers/GCC/crt0.s
|
||||
|
||||
STARTUPINC = ${CHIBIOS}/os/common/ports/e200/compilers/GCC \
|
||||
${CHIBIOS}/os/common/ports/e200/devices/SPC560Bxx
|
||||
|
||||
STARTUPLD = ${CHIBIOS}/os/common/ports/e200/compilers/GCC/ld
|
||||
|
|
@ -1,11 +0,0 @@
|
|||
# List of the ChibiOS e200z0 SPC560Dxx startup files.
|
||||
STARTUPSRC =
|
||||
|
||||
STARTUPASM = $(CHIBIOS)/os/common/ports/e200/devices/SPC560Dxx/boot.s \
|
||||
$(CHIBIOS)/os/common/ports/e200/compilers/GCC/vectors.s \
|
||||
$(CHIBIOS)/os/common/ports/e200/compilers/GCC/crt0.s
|
||||
|
||||
STARTUPINC = ${CHIBIOS}/os/common/ports/e200/compilers/GCC \
|
||||
${CHIBIOS}/os/common/ports/e200/devices/SPC560Dxx
|
||||
|
||||
STARTUPLD = ${CHIBIOS}/os/common/ports/e200/compilers/GCC/ld
|
||||
|
|
@ -1,11 +0,0 @@
|
|||
# List of the ChibiOS e200z0 SPC560Pxx startup files.
|
||||
STARTUPSRC =
|
||||
|
||||
STARTUPASM = $(CHIBIOS)/os/common/ports/e200/devices/SPC560Pxx/boot.s \
|
||||
$(CHIBIOS)/os/common/ports/e200/compilers/GCC/vectors.s \
|
||||
$(CHIBIOS)/os/common/ports/e200/compilers/GCC/crt0.s
|
||||
|
||||
STARTUPINC = ${CHIBIOS}/os/common/ports/e200/compilers/GCC \
|
||||
${CHIBIOS}/os/common/ports/e200/devices/SPC560Pxx
|
||||
|
||||
STARTUPLD = ${CHIBIOS}/os/common/ports/e200/compilers/GCC/ld
|
||||
|
|
@ -1,11 +0,0 @@
|
|||
# List of the ChibiOS e200z3 SPC563Mxx startup files.
|
||||
STARTUPSRC =
|
||||
|
||||
STARTUPASM = $(CHIBIOS)/os/common/ports/e200/devices/SPC563Mxx/boot.s \
|
||||
$(CHIBIOS)/os/common/ports/e200/compilers/GCC/vectors.s \
|
||||
$(CHIBIOS)/os/common/ports/e200/compilers/GCC/crt0.s
|
||||
|
||||
STARTUPINC = ${CHIBIOS}/os/common/ports/e200/compilers/GCC \
|
||||
${CHIBIOS}/os/common/ports/e200/devices/SPC563Mxx
|
||||
|
||||
STARTUPLD = ${CHIBIOS}/os/common/ports/e200/compilers/GCC/ld
|
||||
|
|
@ -1,11 +0,0 @@
|
|||
# List of the ChibiOS e200z4 SPC564Axx startup files.
|
||||
STARTUPSRC =
|
||||
|
||||
STARTUPASM = $(CHIBIOS)/os/common/ports/e200/devices/SPC564Axx/boot.s \
|
||||
$(CHIBIOS)/os/common/ports/e200/compilers/GCC/vectors.s \
|
||||
$(CHIBIOS)/os/common/ports/e200/compilers/GCC/crt0.s
|
||||
|
||||
STARTUPINC = ${CHIBIOS}/os/common/ports/e200/compilers/GCC \
|
||||
${CHIBIOS}/os/common/ports/e200/devices/SPC564Axx
|
||||
|
||||
STARTUPLD = ${CHIBIOS}/os/common/ports/e200/compilers/GCC/ld
|
||||
|
|
@ -1,11 +0,0 @@
|
|||
# List of the ChibiOS e200z4 SPC56ECxx startup files.
|
||||
STARTUPSRC =
|
||||
|
||||
STARTUPASM = $(CHIBIOS)/os/common/ports/e200/devices/SPC56ECxx/boot.s \
|
||||
$(CHIBIOS)/os/common/ports/e200/compilers/GCC/vectors.s \
|
||||
$(CHIBIOS)/os/common/ports/e200/compilers/GCC/crt0.s
|
||||
|
||||
STARTUPINC = ${CHIBIOS}/os/common/ports/e200/compilers/GCC \
|
||||
${CHIBIOS}/os/common/ports/e200/devices/SPC56ECxx
|
||||
|
||||
STARTUPLD = ${CHIBIOS}/os/common/ports/e200/compilers/GCC/ld
|
||||
|
|
@ -1,11 +0,0 @@
|
|||
# List of the ChibiOS e200z4 SPC56ELxx startup files.
|
||||
STARTUPSRC =
|
||||
|
||||
STARTUPASM = $(CHIBIOS)/os/common/ports/e200/devices/SPC56ELxx/boot.s \
|
||||
$(CHIBIOS)/os/common/ports/e200/compilers/GCC/vectors.s \
|
||||
$(CHIBIOS)/os/common/ports/e200/compilers/GCC/crt0.s
|
||||
|
||||
STARTUPINC = ${CHIBIOS}/os/common/ports/e200/compilers/GCC \
|
||||
${CHIBIOS}/os/common/ports/e200/devices/SPC56ELxx
|
||||
|
||||
STARTUPLD = ${CHIBIOS}/os/common/ports/e200/compilers/GCC/ld
|
||||
|
|
@ -1,159 +0,0 @@
|
|||
/*
|
||||
ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
|
||||
|
||||
Licensed under the Apache License, Version 2.0 (the "License");
|
||||
you may not use this file except in compliance with the License.
|
||||
You may obtain a copy of the License at
|
||||
|
||||
http://www.apache.org/licenses/LICENSE-2.0
|
||||
|
||||
Unless required by applicable law or agreed to in writing, software
|
||||
distributed under the License is distributed on an "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
See the License for the specific language governing permissions and
|
||||
limitations under the License.
|
||||
*/
|
||||
|
||||
__ram_size__ = LENGTH(ram);
|
||||
__ram_start__ = ORIGIN(ram);
|
||||
__ram_end__ = ORIGIN(ram) + LENGTH(ram);
|
||||
|
||||
ENTRY(_reset_address)
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
. = ORIGIN(flash);
|
||||
.boot0 : ALIGN(16) SUBALIGN(16)
|
||||
{
|
||||
KEEP(*(.boot))
|
||||
} > flash
|
||||
|
||||
.boot1 : ALIGN(16) SUBALIGN(16)
|
||||
{
|
||||
KEEP(*(.handlers))
|
||||
KEEP(*(.crt0))
|
||||
/* The vectors table requires a 2kB alignment.*/
|
||||
. = ALIGN(0x800);
|
||||
KEEP(*(.vectors))
|
||||
/* The IVPR register requires a 4kB alignment.*/
|
||||
. = ALIGN(0x1000);
|
||||
__ivpr_base__ = .;
|
||||
KEEP(*(.ivors))
|
||||
} > flash
|
||||
|
||||
constructors : ALIGN(4) SUBALIGN(4)
|
||||
{
|
||||
PROVIDE(__init_array_start = .);
|
||||
KEEP(*(SORT(.init_array.*)))
|
||||
KEEP(*(.init_array))
|
||||
PROVIDE(__init_array_end = .);
|
||||
} > flash
|
||||
|
||||
destructors : ALIGN(4) SUBALIGN(4)
|
||||
{
|
||||
PROVIDE(__fini_array_start = .);
|
||||
KEEP(*(.fini_array))
|
||||
KEEP(*(SORT(.fini_array.*)))
|
||||
PROVIDE(__fini_array_end = .);
|
||||
} > flash
|
||||
|
||||
.text_vle : ALIGN(16) SUBALIGN(16)
|
||||
{
|
||||
*(.text_vle)
|
||||
*(.text_vle.*)
|
||||
*(.gnu.linkonce.t_vle.*)
|
||||
} > flash
|
||||
|
||||
.text : ALIGN(16) SUBALIGN(16)
|
||||
{
|
||||
*(.text)
|
||||
*(.text.*)
|
||||
*(.gnu.linkonce.t.*)
|
||||
} > flash
|
||||
|
||||
.rodata : ALIGN(16) SUBALIGN(16)
|
||||
{
|
||||
*(.glue_7t)
|
||||
*(.glue_7)
|
||||
*(.gcc*)
|
||||
*(.rodata)
|
||||
*(.rodata.*)
|
||||
*(.rodata1)
|
||||
} > flash
|
||||
|
||||
.sdata2 : ALIGN(16) SUBALIGN(16)
|
||||
{
|
||||
__sdata2_start__ = . + 0x8000;
|
||||
*(.sdata2)
|
||||
*(.sdata2.*)
|
||||
*(.gnu.linkonce.s2.*)
|
||||
*(.sbss2)
|
||||
*(.sbss2.*)
|
||||
*(.gnu.linkonce.sb2.*)
|
||||
} > flash
|
||||
|
||||
.eh_frame_hdr :
|
||||
{
|
||||
*(.eh_frame_hdr)
|
||||
} > flash
|
||||
|
||||
.eh_frame : ONLY_IF_RO
|
||||
{
|
||||
*(.eh_frame)
|
||||
} > flash
|
||||
|
||||
.romdata : ALIGN(16) SUBALIGN(16)
|
||||
{
|
||||
__romdata_start__ = .;
|
||||
} > flash
|
||||
|
||||
.stacks : ALIGN(16) SUBALIGN(16)
|
||||
{
|
||||
. = ALIGN(8);
|
||||
__irq_stack_base__ = .;
|
||||
. += __irq_stack_size__;
|
||||
. = ALIGN(8);
|
||||
__irq_stack_end__ = .;
|
||||
__process_stack_base__ = .;
|
||||
__main_thread_stack_base__ = .;
|
||||
. += __process_stack_size__;
|
||||
. = ALIGN(8);
|
||||
__process_stack_end__ = .;
|
||||
__main_thread_stack_end__ = .;
|
||||
} > ram
|
||||
|
||||
.data : AT(__romdata_start__)
|
||||
{
|
||||
. = ALIGN(4);
|
||||
__data_start__ = .;
|
||||
*(.data)
|
||||
*(.data.*)
|
||||
*(.gnu.linkonce.d.*)
|
||||
__sdata_start__ = . + 0x8000;
|
||||
*(.sdata)
|
||||
*(.sdata.*)
|
||||
*(.gnu.linkonce.s.*)
|
||||
__data_end__ = .;
|
||||
} > ram
|
||||
|
||||
.sbss :
|
||||
{
|
||||
__bss_start__ = .;
|
||||
*(.sbss)
|
||||
*(.sbss.*)
|
||||
*(.gnu.linkonce.sb.*)
|
||||
*(.scommon)
|
||||
} > ram
|
||||
|
||||
.bss :
|
||||
{
|
||||
*(.bss)
|
||||
*(.bss.*)
|
||||
*(.gnu.linkonce.b.*)
|
||||
*(COMMON)
|
||||
__bss_end__ = .;
|
||||
} > ram
|
||||
|
||||
__heap_base__ = __bss_end__;
|
||||
__heap_end__ = __ram_end__;
|
||||
}
|
||||
|
|
@ -1,156 +0,0 @@
|
|||
/*
|
||||
ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
|
||||
|
||||
Licensed under the Apache License, Version 2.0 (the "License");
|
||||
you may not use this file except in compliance with the License.
|
||||
You may obtain a copy of the License at
|
||||
|
||||
http://www.apache.org/licenses/LICENSE-2.0
|
||||
|
||||
Unless required by applicable law or agreed to in writing, software
|
||||
distributed under the License is distributed on an "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
See the License for the specific language governing permissions and
|
||||
limitations under the License.
|
||||
*/
|
||||
|
||||
__ram_size__ = LENGTH(ram);
|
||||
__ram_start__ = ORIGIN(ram);
|
||||
__ram_end__ = ORIGIN(ram) + LENGTH(ram);
|
||||
|
||||
ENTRY(_reset_address)
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
. = ORIGIN(flash);
|
||||
.boot0 : ALIGN(16) SUBALIGN(16)
|
||||
{
|
||||
__ivpr_base__ = .;
|
||||
KEEP(*(.boot))
|
||||
} > flash
|
||||
|
||||
.boot1 : ALIGN(16) SUBALIGN(16)
|
||||
{
|
||||
KEEP(*(.handlers))
|
||||
KEEP(*(.crt0))
|
||||
/* The vectors table requires a 2kB alignment.*/
|
||||
. = ALIGN(0x800);
|
||||
KEEP(*(.vectors))
|
||||
} > flash
|
||||
|
||||
constructors : ALIGN(4) SUBALIGN(4)
|
||||
{
|
||||
PROVIDE(__init_array_start = .);
|
||||
KEEP(*(SORT(.init_array.*)))
|
||||
KEEP(*(.init_array))
|
||||
PROVIDE(__init_array_end = .);
|
||||
} > flash
|
||||
|
||||
destructors : ALIGN(4) SUBALIGN(4)
|
||||
{
|
||||
PROVIDE(__fini_array_start = .);
|
||||
KEEP(*(.fini_array))
|
||||
KEEP(*(SORT(.fini_array.*)))
|
||||
PROVIDE(__fini_array_end = .);
|
||||
} > flash
|
||||
|
||||
.text_vle : ALIGN(16) SUBALIGN(16)
|
||||
{
|
||||
*(.text_vle)
|
||||
*(.text_vle.*)
|
||||
*(.gnu.linkonce.t_vle.*)
|
||||
} > flash
|
||||
|
||||
.text : ALIGN(16) SUBALIGN(16)
|
||||
{
|
||||
*(.text)
|
||||
*(.text.*)
|
||||
*(.gnu.linkonce.t.*)
|
||||
} > flash
|
||||
|
||||
.rodata : ALIGN(16) SUBALIGN(16)
|
||||
{
|
||||
*(.glue_7t)
|
||||
*(.glue_7)
|
||||
*(.gcc*)
|
||||
*(.rodata)
|
||||
*(.rodata.*)
|
||||
*(.rodata1)
|
||||
} > flash
|
||||
|
||||
.sdata2 : ALIGN(16) SUBALIGN(16)
|
||||
{
|
||||
__sdata2_start__ = . + 0x8000;
|
||||
*(.sdata2)
|
||||
*(.sdata2.*)
|
||||
*(.gnu.linkonce.s2.*)
|
||||
*(.sbss2)
|
||||
*(.sbss2.*)
|
||||
*(.gnu.linkonce.sb2.*)
|
||||
} > flash
|
||||
|
||||
.eh_frame_hdr :
|
||||
{
|
||||
*(.eh_frame_hdr)
|
||||
} > flash
|
||||
|
||||
.eh_frame : ONLY_IF_RO
|
||||
{
|
||||
*(.eh_frame)
|
||||
} > flash
|
||||
|
||||
.romdata : ALIGN(16) SUBALIGN(16)
|
||||
{
|
||||
__romdata_start__ = .;
|
||||
} > flash
|
||||
|
||||
.stacks : ALIGN(16) SUBALIGN(16)
|
||||
{
|
||||
. = ALIGN(8);
|
||||
__irq_stack_base__ = .;
|
||||
. += __irq_stack_size__;
|
||||
. = ALIGN(8);
|
||||
__irq_stack_end__ = .;
|
||||
__process_stack_base__ = .;
|
||||
__main_thread_stack_base__ = .;
|
||||
. += __process_stack_size__;
|
||||
. = ALIGN(8);
|
||||
__process_stack_end__ = .;
|
||||
__main_thread_stack_end__ = .;
|
||||
} > ram
|
||||
|
||||
.data : AT(__romdata_start__)
|
||||
{
|
||||
. = ALIGN(4);
|
||||
__data_start__ = .;
|
||||
*(.data)
|
||||
*(.data.*)
|
||||
*(.gnu.linkonce.d.*)
|
||||
__sdata_start__ = . + 0x8000;
|
||||
*(.sdata)
|
||||
*(.sdata.*)
|
||||
*(.gnu.linkonce.s.*)
|
||||
__data_end__ = .;
|
||||
} > ram
|
||||
|
||||
.sbss :
|
||||
{
|
||||
__bss_start__ = .;
|
||||
*(.sbss)
|
||||
*(.sbss.*)
|
||||
*(.gnu.linkonce.sb.*)
|
||||
*(.scommon)
|
||||
} > ram
|
||||
|
||||
.bss :
|
||||
{
|
||||
*(.bss)
|
||||
*(.bss.*)
|
||||
*(.gnu.linkonce.b.*)
|
||||
*(COMMON)
|
||||
__bss_end__ = .;
|
||||
} > ram
|
||||
|
||||
__heap_base__ = __bss_end__;
|
||||
__heap_end__ = __ram_end__;
|
||||
}
|
||||
|
|
@ -1,156 +0,0 @@
|
|||
/*
|
||||
ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
|
||||
|
||||
Licensed under the Apache License, Version 2.0 (the "License");
|
||||
you may not use this file except in compliance with the License.
|
||||
You may obtain a copy of the License at
|
||||
|
||||
http://www.apache.org/licenses/LICENSE-2.0
|
||||
|
||||
Unless required by applicable law or agreed to in writing, software
|
||||
distributed under the License is distributed on an "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
See the License for the specific language governing permissions and
|
||||
limitations under the License.
|
||||
*/
|
||||
|
||||
__ram_size__ = LENGTH(ram);
|
||||
__ram_start__ = ORIGIN(ram);
|
||||
__ram_end__ = ORIGIN(ram) + LENGTH(ram);
|
||||
|
||||
ENTRY(_reset_address)
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
. = ORIGIN(flash);
|
||||
.boot0 : ALIGN(16) SUBALIGN(16)
|
||||
{
|
||||
__ivpr_base__ = .;
|
||||
KEEP(*(.boot))
|
||||
} > flash
|
||||
|
||||
.boot1 : ALIGN(16) SUBALIGN(16)
|
||||
{
|
||||
KEEP(*(.handlers))
|
||||
KEEP(*(.crt0))
|
||||
/* The vectors table requires a 2kB alignment.*/
|
||||
. = ALIGN(0x800);
|
||||
KEEP(*(.vectors))
|
||||
} > flash
|
||||
|
||||
constructors : ALIGN(4) SUBALIGN(4)
|
||||
{
|
||||
PROVIDE(__init_array_start = .);
|
||||
KEEP(*(SORT(.init_array.*)))
|
||||
KEEP(*(.init_array))
|
||||
PROVIDE(__init_array_end = .);
|
||||
} > flash
|
||||
|
||||
destructors : ALIGN(4) SUBALIGN(4)
|
||||
{
|
||||
PROVIDE(__fini_array_start = .);
|
||||
KEEP(*(.fini_array))
|
||||
KEEP(*(SORT(.fini_array.*)))
|
||||
PROVIDE(__fini_array_end = .);
|
||||
} > flash
|
||||
|
||||
.text_vle : ALIGN(16) SUBALIGN(16)
|
||||
{
|
||||
*(.text_vle)
|
||||
*(.text_vle.*)
|
||||
*(.gnu.linkonce.t_vle.*)
|
||||
} > flash
|
||||
|
||||
.text : ALIGN(16) SUBALIGN(16)
|
||||
{
|
||||
*(.text)
|
||||
*(.text.*)
|
||||
*(.gnu.linkonce.t.*)
|
||||
} > flash
|
||||
|
||||
.rodata : ALIGN(16) SUBALIGN(16)
|
||||
{
|
||||
*(.glue_7t)
|
||||
*(.glue_7)
|
||||
*(.gcc*)
|
||||
*(.rodata)
|
||||
*(.rodata.*)
|
||||
*(.rodata1)
|
||||
} > flash
|
||||
|
||||
.sdata2 : ALIGN(16) SUBALIGN(16)
|
||||
{
|
||||
__sdata2_start__ = . + 0x8000;
|
||||
*(.sdata2)
|
||||
*(.sdata2.*)
|
||||
*(.gnu.linkonce.s2.*)
|
||||
*(.sbss2)
|
||||
*(.sbss2.*)
|
||||
*(.gnu.linkonce.sb2.*)
|
||||
} > flash
|
||||
|
||||
.eh_frame_hdr :
|
||||
{
|
||||
*(.eh_frame_hdr)
|
||||
} > flash
|
||||
|
||||
.eh_frame : ONLY_IF_RO
|
||||
{
|
||||
*(.eh_frame)
|
||||
} > flash
|
||||
|
||||
.romdata : ALIGN(16) SUBALIGN(16)
|
||||
{
|
||||
__romdata_start__ = .;
|
||||
} > flash
|
||||
|
||||
.stacks : ALIGN(16) SUBALIGN(16)
|
||||
{
|
||||
. = ALIGN(8);
|
||||
__irq_stack_base__ = .;
|
||||
. += __irq_stack_size__;
|
||||
. = ALIGN(8);
|
||||
__irq_stack_end__ = .;
|
||||
__process_stack_base__ = .;
|
||||
__main_thread_stack_base__ = .;
|
||||
. += __process_stack_size__;
|
||||
. = ALIGN(8);
|
||||
__process_stack_end__ = .;
|
||||
__main_thread_stack_end__ = .;
|
||||
} > ram
|
||||
|
||||
.data : AT(__romdata_start__)
|
||||
{
|
||||
. = ALIGN(4);
|
||||
__data_start__ = .;
|
||||
*(.data)
|
||||
*(.data.*)
|
||||
*(.gnu.linkonce.d.*)
|
||||
__sdata_start__ = . + 0x8000;
|
||||
*(.sdata)
|
||||
*(.sdata.*)
|
||||
*(.gnu.linkonce.s.*)
|
||||
__data_end__ = .;
|
||||
} > ram
|
||||
|
||||
.sbss :
|
||||
{
|
||||
__bss_start__ = .;
|
||||
*(.sbss)
|
||||
*(.sbss.*)
|
||||
*(.gnu.linkonce.sb.*)
|
||||
*(.scommon)
|
||||
} > ram
|
||||
|
||||
.bss :
|
||||
{
|
||||
*(.bss)
|
||||
*(.bss.*)
|
||||
*(.gnu.linkonce.b.*)
|
||||
*(COMMON)
|
||||
__bss_end__ = .;
|
||||
} > ram
|
||||
|
||||
__heap_base__ = __bss_end__;
|
||||
__heap_end__ = __ram_end__;
|
||||
}
|
||||
|
|
@ -1,78 +0,0 @@
|
|||
/*
|
||||
ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
|
||||
|
||||
Licensed under the Apache License, Version 2.0 (the "License");
|
||||
you may not use this file except in compliance with the License.
|
||||
You may obtain a copy of the License at
|
||||
|
||||
http://www.apache.org/licenses/LICENSE-2.0
|
||||
|
||||
Unless required by applicable law or agreed to in writing, software
|
||||
distributed under the License is distributed on an "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
See the License for the specific language governing permissions and
|
||||
limitations under the License.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file vectors.h
|
||||
* @brief ISR vector module header.
|
||||
*
|
||||
* @addtogroup PPC_GCC_CORE
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifndef _VECTORS_H_
|
||||
#define _VECTORS_H_
|
||||
|
||||
#include "ppcparams.h"
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Module constants. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Module pre-compile time settings. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Derived constants and error checks. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Module data structures and types. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Module macros. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* External declarations. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/* The following code is not processed when the file is included from an
|
||||
asm module.*/
|
||||
#if !defined(_FROM_ASM_)
|
||||
|
||||
#if !defined(__DOXYGEN__)
|
||||
extern uint32_t _vectors[PPC_NUM_VECTORS];
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
void _unhandled_irq(void);
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* !defined(_FROM_ASM_) */
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Module inline functions. */
|
||||
/*===========================================================================*/
|
||||
|
||||
#endif /* _VECTORS_H_ */
|
||||
|
||||
/** @} */
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -1,114 +0,0 @@
|
|||
/*
|
||||
ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
|
||||
|
||||
Licensed under the Apache License, Version 2.0 (the "License");
|
||||
you may not use this file except in compliance with the License.
|
||||
You may obtain a copy of the License at
|
||||
|
||||
http://www.apache.org/licenses/LICENSE-2.0
|
||||
|
||||
Unless required by applicable law or agreed to in writing, software
|
||||
distributed under the License is distributed on an "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
See the License for the specific language governing permissions and
|
||||
limitations under the License.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file boot.h
|
||||
* @brief Boot parameters for the SPC560BCxx.
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifndef _BOOT_H_
|
||||
#define _BOOT_H_
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Module constants. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @name BUCSR registers definitions
|
||||
* @{
|
||||
*/
|
||||
#define BUCSR_BPEN 0x00000001
|
||||
#define BUCSR_BALLOC_BFI 0x00000200
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @name MSR register definitions
|
||||
* @{
|
||||
*/
|
||||
#define MSR_WE 0x00040000
|
||||
#define MSR_CE 0x00020000
|
||||
#define MSR_EE 0x00008000
|
||||
#define MSR_PR 0x00004000
|
||||
#define MSR_ME 0x00001000
|
||||
#define MSR_DE 0x00000200
|
||||
#define MSR_IS 0x00000020
|
||||
#define MSR_DS 0x00000010
|
||||
#define MSR_RI 0x00000002
|
||||
/** @} */
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Module pre-compile time settings. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*
|
||||
* BUCSR default settings.
|
||||
*/
|
||||
#if !defined(BOOT_BUCSR_DEFAULT) || defined(__DOXYGEN__)
|
||||
#define BOOT_BUCSR_DEFAULT (BUCSR_BPEN | BUCSR_BALLOC_BFI)
|
||||
#endif
|
||||
|
||||
/*
|
||||
* MSR default settings.
|
||||
*/
|
||||
#if !defined(BOOT_MSR_DEFAULT) || defined(__DOXYGEN__)
|
||||
#define BOOT_MSR_DEFAULT (MSR_WE | MSR_CE | MSR_ME)
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Boot default settings.
|
||||
*/
|
||||
#if !defined(BOOT_PERFORM_CORE_INIT) || defined(__DOXYGEN__)
|
||||
#define BOOT_PERFORM_CORE_INIT 1
|
||||
#endif
|
||||
|
||||
/*
|
||||
* VLE mode default settings.
|
||||
*/
|
||||
#if !defined(BOOT_USE_VLE) || defined(__DOXYGEN__)
|
||||
#define BOOT_USE_VLE 1
|
||||
#endif
|
||||
|
||||
/*
|
||||
* RAM relocation flag.
|
||||
*/
|
||||
#if !defined(BOOT_RELOCATE_IN_RAM) || defined(__DOXYGEN__)
|
||||
#define BOOT_RELOCATE_IN_RAM 0
|
||||
#endif
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Derived constants and error checks. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Module data structures and types. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Module macros. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* External declarations. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Module inline functions. */
|
||||
/*===========================================================================*/
|
||||
|
||||
#endif /* _BOOT_H_ */
|
||||
|
||||
/** @} */
|
||||
|
|
@ -1,214 +0,0 @@
|
|||
/*
|
||||
ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
|
||||
|
||||
Licensed under the Apache License, Version 2.0 (the "License");
|
||||
you may not use this file except in compliance with the License.
|
||||
You may obtain a copy of the License at
|
||||
|
||||
http://www.apache.org/licenses/LICENSE-2.0
|
||||
|
||||
Unless required by applicable law or agreed to in writing, software
|
||||
distributed under the License is distributed on an "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
See the License for the specific language governing permissions and
|
||||
limitations under the License.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file SPC560BCxx/boot.s
|
||||
* @brief SPC560BCxx boot-related code.
|
||||
*
|
||||
* @addtogroup PPC_BOOT
|
||||
* @{
|
||||
*/
|
||||
|
||||
#include "boot.h"
|
||||
|
||||
#if !defined(__DOXYGEN__)
|
||||
|
||||
/* BAM record.*/
|
||||
.section .boot, "ax"
|
||||
|
||||
.long 0x015A0000
|
||||
.long _reset_address
|
||||
|
||||
.align 2
|
||||
.globl _reset_address
|
||||
.type _reset_address, @function
|
||||
_reset_address:
|
||||
#if BOOT_PERFORM_CORE_INIT
|
||||
bl _coreinit
|
||||
#endif
|
||||
bl _ivinit
|
||||
|
||||
#if BOOT_RELOCATE_IN_RAM
|
||||
/*
|
||||
* Image relocation in RAM.
|
||||
*/
|
||||
lis %r4, __ram_reloc_start__@h
|
||||
ori %r4, %r4, __ram_reloc_start__@l
|
||||
lis %r5, __ram_reloc_dest__@h
|
||||
ori %r5, %r5, __ram_reloc_dest__@l
|
||||
lis %r6, __ram_reloc_end__@h
|
||||
ori %r6, %r6, __ram_reloc_end__@l
|
||||
.relloop:
|
||||
cmpl cr0, %r4, %r6
|
||||
bge cr0, .relend
|
||||
lwz %r7, 0(%r4)
|
||||
addi %r4, %r4, 4
|
||||
stw %r7, 0(%r5)
|
||||
addi %r5, %r5, 4
|
||||
b .relloop
|
||||
.relend:
|
||||
lis %r3, _boot_address@h
|
||||
ori %r3, %r3, _boot_address@l
|
||||
mtctr %r3
|
||||
bctrl
|
||||
#else
|
||||
b _boot_address
|
||||
#endif
|
||||
|
||||
#if BOOT_PERFORM_CORE_INIT
|
||||
.align 2
|
||||
_coreinit:
|
||||
/*
|
||||
* RAM clearing, this device requires a write to all RAM location in
|
||||
* order to initialize the ECC detection hardware, this is going to
|
||||
* slow down the startup but there is no way around.
|
||||
*/
|
||||
xor %r0, %r0, %r0
|
||||
xor %r1, %r1, %r1
|
||||
xor %r2, %r2, %r2
|
||||
xor %r3, %r3, %r3
|
||||
xor %r4, %r4, %r4
|
||||
xor %r5, %r5, %r5
|
||||
xor %r6, %r6, %r6
|
||||
xor %r7, %r7, %r7
|
||||
xor %r8, %r8, %r8
|
||||
xor %r9, %r9, %r9
|
||||
xor %r10, %r10, %r10
|
||||
xor %r11, %r11, %r11
|
||||
xor %r12, %r12, %r12
|
||||
xor %r13, %r13, %r13
|
||||
xor %r14, %r14, %r14
|
||||
xor %r15, %r15, %r15
|
||||
xor %r16, %r16, %r16
|
||||
xor %r17, %r17, %r17
|
||||
xor %r18, %r18, %r18
|
||||
xor %r19, %r19, %r19
|
||||
xor %r20, %r20, %r20
|
||||
xor %r21, %r21, %r21
|
||||
xor %r22, %r22, %r22
|
||||
xor %r23, %r23, %r23
|
||||
xor %r24, %r24, %r24
|
||||
xor %r25, %r25, %r25
|
||||
xor %r26, %r26, %r26
|
||||
xor %r27, %r27, %r27
|
||||
xor %r28, %r28, %r28
|
||||
xor %r29, %r29, %r29
|
||||
xor %r30, %r30, %r30
|
||||
xor %r31, %r31, %r31
|
||||
lis %r4, __ram_start__@h
|
||||
ori %r4, %r4, __ram_start__@l
|
||||
lis %r5, __ram_end__@h
|
||||
ori %r5, %r5, __ram_end__@l
|
||||
.cleareccloop:
|
||||
cmpl %cr0, %r4, %r5
|
||||
bge %cr0, .cleareccend
|
||||
stmw %r16, 0(%r4)
|
||||
addi %r4, %r4, 64
|
||||
b .cleareccloop
|
||||
.cleareccend:
|
||||
|
||||
/*
|
||||
* Branch prediction enabled.
|
||||
*/
|
||||
li %r3, BOOT_BUCSR_DEFAULT
|
||||
mtspr 1013, %r3 /* BUCSR */
|
||||
|
||||
blr
|
||||
#endif /* BOOT_PERFORM_CORE_INIT */
|
||||
|
||||
/*
|
||||
* Exception vectors initialization.
|
||||
*/
|
||||
.align 2
|
||||
_ivinit:
|
||||
/* MSR initialization.*/
|
||||
lis %r3, BOOT_MSR_DEFAULT@h
|
||||
ori %r3, %r3, BOOT_MSR_DEFAULT@l
|
||||
mtMSR %r3
|
||||
|
||||
/* IVPR initialization.*/
|
||||
lis %r3, __ivpr_base__@h
|
||||
ori %r3, %r3, __ivpr_base__@l
|
||||
mtIVPR %r3
|
||||
|
||||
blr
|
||||
|
||||
.section .ivors, "ax"
|
||||
|
||||
.globl IVORS
|
||||
IVORS:
|
||||
b _IVOR0
|
||||
.align 4
|
||||
b _IVOR1
|
||||
.align 4
|
||||
b _IVOR2
|
||||
.align 4
|
||||
b _IVOR3
|
||||
.align 4
|
||||
b _IVOR4
|
||||
.align 4
|
||||
b _IVOR5
|
||||
.align 4
|
||||
b _IVOR6
|
||||
.align 4
|
||||
b _IVOR7
|
||||
.align 4
|
||||
b _IVOR8
|
||||
.align 4
|
||||
b _IVOR9
|
||||
.align 4
|
||||
b _IVOR10
|
||||
.align 4
|
||||
b _IVOR11
|
||||
.align 4
|
||||
b _IVOR12
|
||||
.align 4
|
||||
b _IVOR13
|
||||
.align 4
|
||||
b _IVOR14
|
||||
.align 4
|
||||
b _IVOR15
|
||||
|
||||
.section .handlers, "ax"
|
||||
|
||||
/*
|
||||
* Default IVOR handlers.
|
||||
*/
|
||||
.align 2
|
||||
.weak _IVOR0, _IVOR1, _IVOR2, _IVOR3, _IVOR4, _IVOR5
|
||||
.weak _IVOR6, _IVOR7, _IVOR8, _IVOR9, _IVOR10, _IVOR11
|
||||
.weak _IVOR12, _IVOR13, _IVOR14, _IVOR15
|
||||
_IVOR0:
|
||||
_IVOR1:
|
||||
_IVOR2:
|
||||
_IVOR3:
|
||||
_IVOR5:
|
||||
_IVOR6:
|
||||
_IVOR7:
|
||||
_IVOR8:
|
||||
_IVOR9:
|
||||
_IVOR11:
|
||||
_IVOR12:
|
||||
_IVOR13:
|
||||
_IVOR14:
|
||||
_IVOR15:
|
||||
.global _unhandled_exception
|
||||
_unhandled_exception:
|
||||
b _unhandled_exception
|
||||
|
||||
#endif /* !defined(__DOXYGEN__) */
|
||||
|
||||
/** @} */
|
||||
|
|
@ -1,93 +0,0 @@
|
|||
/*
|
||||
ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
|
||||
|
||||
Licensed under the Apache License, Version 2.0 (the "License");
|
||||
you may not use this file except in compliance with the License.
|
||||
You may obtain a copy of the License at
|
||||
|
||||
http://www.apache.org/licenses/LICENSE-2.0
|
||||
|
||||
Unless required by applicable law or agreed to in writing, software
|
||||
distributed under the License is distributed on an "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
See the License for the specific language governing permissions and
|
||||
limitations under the License.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file SPC560BCxx/intc.h
|
||||
* @brief SPC560BCxx INTC module header.
|
||||
*
|
||||
* @addtogroup INTC
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifndef _INTC_H_
|
||||
#define _INTC_H_
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Module constants. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @name INTC addresses
|
||||
* @{
|
||||
*/
|
||||
#define INTC_BASE 0xFFF48000
|
||||
#define INTC_IACKR_ADDR (INTC_BASE + 0x10)
|
||||
#define INTC_EOIR_ADDR (INTC_BASE + 0x18)
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @brief INTC priority levels.
|
||||
*/
|
||||
#define INTC_PRIORITY_LEVELS 16U
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Module pre-compile time settings. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Derived constants and error checks. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Module data structures and types. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Module macros. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @name INTC-related macros
|
||||
* @{
|
||||
*/
|
||||
#define INTC_BCR (*((volatile uint32_t *)(INTC_BASE + 0)))
|
||||
#define INTC_CPR(n) (*((volatile uint32_t *)(INTC_BASE + 8 + ((n) * sizeof (uint32_t)))))
|
||||
#define INTC_IACKR(n) (*((volatile uint32_t *)(INTC_BASE + 0x10 + ((n) * sizeof (uint32_t)))))
|
||||
#define INTC_EOIR(n) (*((volatile uint32_t *)(INTC_BASE + 0x18 + ((n) * sizeof (uint32_t)))))
|
||||
#define INTC_PSR(n) (*((volatile uint8_t *)(INTC_BASE + 0x40 + ((n) * sizeof (uint8_t)))))
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @brief Core selection macros for PSR register.
|
||||
*/
|
||||
#define INTC_PSR_CORE0 0x00
|
||||
|
||||
/**
|
||||
* @brief PSR register content helper
|
||||
*/
|
||||
#define INTC_PSR_ENABLE(cores, prio) ((uint32_t)(cores) | (uint32_t)(prio))
|
||||
|
||||
/*===========================================================================*/
|
||||
/* External declarations. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Module inline functions. */
|
||||
/*===========================================================================*/
|
||||
|
||||
#endif /* _INTC_H_ */
|
||||
|
||||
/** @} */
|
||||
|
|
@ -1,83 +0,0 @@
|
|||
/*
|
||||
ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
|
||||
|
||||
Licensed under the Apache License, Version 2.0 (the "License");
|
||||
you may not use this file except in compliance with the License.
|
||||
You may obtain a copy of the License at
|
||||
|
||||
http://www.apache.org/licenses/LICENSE-2.0
|
||||
|
||||
Unless required by applicable law or agreed to in writing, software
|
||||
distributed under the License is distributed on an "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
See the License for the specific language governing permissions and
|
||||
limitations under the License.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file SPC560BCxx/ppcparams.h
|
||||
* @brief PowerPC parameters for the SPC560BCxx.
|
||||
*
|
||||
* @defgroup PPC_SPC560BCxx SPC560BCxx Specific Parameters
|
||||
* @ingroup PPC_SPECIFIC
|
||||
* @details This file contains the PowerPC specific parameters for the
|
||||
* SPC560BCxx platform.
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifndef _PPCPARAMS_H_
|
||||
#define _PPCPARAMS_H_
|
||||
|
||||
/**
|
||||
* @brief Family identification macro.
|
||||
*/
|
||||
#define PPC_SPC560BCxx
|
||||
|
||||
/**
|
||||
* @brief PPC core model.
|
||||
*/
|
||||
#define PPC_VARIANT PPC_VARIANT_e200z0
|
||||
|
||||
/**
|
||||
* @brief Number of cores.
|
||||
*/
|
||||
#define PPC_CORE_NUMBER 1
|
||||
|
||||
/**
|
||||
* @brief Number of writable bits in IVPR register.
|
||||
*/
|
||||
#define PPC_IVPR_BITS 20
|
||||
|
||||
/**
|
||||
* @brief IVORx registers support.
|
||||
*/
|
||||
#define PPC_SUPPORTS_IVORS FALSE
|
||||
|
||||
/**
|
||||
* @brief Book E instruction set support.
|
||||
*/
|
||||
#define PPC_SUPPORTS_BOOKE FALSE
|
||||
|
||||
/**
|
||||
* @brief VLE instruction set support.
|
||||
*/
|
||||
#define PPC_SUPPORTS_VLE TRUE
|
||||
|
||||
/**
|
||||
* @brief Supports VLS Load/Store Multiple Volatile instructions.
|
||||
*/
|
||||
#define PPC_SUPPORTS_VLE_MULTI TRUE
|
||||
|
||||
/**
|
||||
* @brief Supports the decrementer timer.
|
||||
*/
|
||||
#define PPC_SUPPORTS_DECREMENTER FALSE
|
||||
|
||||
/**
|
||||
* @brief Number of interrupt sources.
|
||||
*/
|
||||
#define PPC_NUM_VECTORS 217
|
||||
|
||||
#endif /* _PPCPARAMS_H_ */
|
||||
|
||||
/** @} */
|
||||
|
|
@ -1,114 +0,0 @@
|
|||
/*
|
||||
ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
|
||||
|
||||
Licensed under the Apache License, Version 2.0 (the "License");
|
||||
you may not use this file except in compliance with the License.
|
||||
You may obtain a copy of the License at
|
||||
|
||||
http://www.apache.org/licenses/LICENSE-2.0
|
||||
|
||||
Unless required by applicable law or agreed to in writing, software
|
||||
distributed under the License is distributed on an "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
See the License for the specific language governing permissions and
|
||||
limitations under the License.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file boot.h
|
||||
* @brief Boot parameters for the SPC560Bxx.
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifndef _BOOT_H_
|
||||
#define _BOOT_H_
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Module constants. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @name BUCSR registers definitions
|
||||
* @{
|
||||
*/
|
||||
#define BUCSR_BPEN 0x00000001
|
||||
#define BUCSR_BALLOC_BFI 0x00000200
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @name MSR register definitions
|
||||
* @{
|
||||
*/
|
||||
#define MSR_WE 0x00040000
|
||||
#define MSR_CE 0x00020000
|
||||
#define MSR_EE 0x00008000
|
||||
#define MSR_PR 0x00004000
|
||||
#define MSR_ME 0x00001000
|
||||
#define MSR_DE 0x00000200
|
||||
#define MSR_IS 0x00000020
|
||||
#define MSR_DS 0x00000010
|
||||
#define MSR_RI 0x00000002
|
||||
/** @} */
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Module pre-compile time settings. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*
|
||||
* BUCSR default settings.
|
||||
*/
|
||||
#if !defined(BOOT_BUCSR_DEFAULT) || defined(__DOXYGEN__)
|
||||
#define BOOT_BUCSR_DEFAULT (BUCSR_BPEN | BUCSR_BALLOC_BFI)
|
||||
#endif
|
||||
|
||||
/*
|
||||
* MSR default settings.
|
||||
*/
|
||||
#if !defined(BOOT_MSR_DEFAULT) || defined(__DOXYGEN__)
|
||||
#define BOOT_MSR_DEFAULT (MSR_WE | MSR_CE | MSR_ME)
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Boot default settings.
|
||||
*/
|
||||
#if !defined(BOOT_PERFORM_CORE_INIT) || defined(__DOXYGEN__)
|
||||
#define BOOT_PERFORM_CORE_INIT 1
|
||||
#endif
|
||||
|
||||
/*
|
||||
* VLE mode default settings.
|
||||
*/
|
||||
#if !defined(BOOT_USE_VLE) || defined(__DOXYGEN__)
|
||||
#define BOOT_USE_VLE 1
|
||||
#endif
|
||||
|
||||
/*
|
||||
* RAM relocation flag.
|
||||
*/
|
||||
#if !defined(BOOT_RELOCATE_IN_RAM) || defined(__DOXYGEN__)
|
||||
#define BOOT_RELOCATE_IN_RAM 0
|
||||
#endif
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Derived constants and error checks. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Module data structures and types. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Module macros. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* External declarations. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Module inline functions. */
|
||||
/*===========================================================================*/
|
||||
|
||||
#endif /* _BOOT_H_ */
|
||||
|
||||
/** @} */
|
||||
|
|
@ -1,214 +0,0 @@
|
|||
/*
|
||||
ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
|
||||
|
||||
Licensed under the Apache License, Version 2.0 (the "License");
|
||||
you may not use this file except in compliance with the License.
|
||||
You may obtain a copy of the License at
|
||||
|
||||
http://www.apache.org/licenses/LICENSE-2.0
|
||||
|
||||
Unless required by applicable law or agreed to in writing, software
|
||||
distributed under the License is distributed on an "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
See the License for the specific language governing permissions and
|
||||
limitations under the License.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file SPC560Bxx/boot.s
|
||||
* @brief SPC560Bxx boot-related code.
|
||||
*
|
||||
* @addtogroup PPC_BOOT
|
||||
* @{
|
||||
*/
|
||||
|
||||
#include "boot.h"
|
||||
|
||||
#if !defined(__DOXYGEN__)
|
||||
|
||||
/* BAM record.*/
|
||||
.section .boot, "ax"
|
||||
|
||||
.long 0x015A0000
|
||||
.long _reset_address
|
||||
|
||||
.align 2
|
||||
.globl _reset_address
|
||||
.type _reset_address, @function
|
||||
_reset_address:
|
||||
#if BOOT_PERFORM_CORE_INIT
|
||||
bl _coreinit
|
||||
#endif
|
||||
bl _ivinit
|
||||
|
||||
#if BOOT_RELOCATE_IN_RAM
|
||||
/*
|
||||
* Image relocation in RAM.
|
||||
*/
|
||||
lis %r4, __ram_reloc_start__@h
|
||||
ori %r4, %r4, __ram_reloc_start__@l
|
||||
lis %r5, __ram_reloc_dest__@h
|
||||
ori %r5, %r5, __ram_reloc_dest__@l
|
||||
lis %r6, __ram_reloc_end__@h
|
||||
ori %r6, %r6, __ram_reloc_end__@l
|
||||
.relloop:
|
||||
cmpl cr0, %r4, %r6
|
||||
bge cr0, .relend
|
||||
lwz %r7, 0(%r4)
|
||||
addi %r4, %r4, 4
|
||||
stw %r7, 0(%r5)
|
||||
addi %r5, %r5, 4
|
||||
b .relloop
|
||||
.relend:
|
||||
lis %r3, _boot_address@h
|
||||
ori %r3, %r3, _boot_address@l
|
||||
mtctr %r3
|
||||
bctrl
|
||||
#else
|
||||
b _boot_address
|
||||
#endif
|
||||
|
||||
#if BOOT_PERFORM_CORE_INIT
|
||||
.align 2
|
||||
_coreinit:
|
||||
/*
|
||||
* RAM clearing, this device requires a write to all RAM location in
|
||||
* order to initialize the ECC detection hardware, this is going to
|
||||
* slow down the startup but there is no way around.
|
||||
*/
|
||||
xor %r0, %r0, %r0
|
||||
xor %r1, %r1, %r1
|
||||
xor %r2, %r2, %r2
|
||||
xor %r3, %r3, %r3
|
||||
xor %r4, %r4, %r4
|
||||
xor %r5, %r5, %r5
|
||||
xor %r6, %r6, %r6
|
||||
xor %r7, %r7, %r7
|
||||
xor %r8, %r8, %r8
|
||||
xor %r9, %r9, %r9
|
||||
xor %r10, %r10, %r10
|
||||
xor %r11, %r11, %r11
|
||||
xor %r12, %r12, %r12
|
||||
xor %r13, %r13, %r13
|
||||
xor %r14, %r14, %r14
|
||||
xor %r15, %r15, %r15
|
||||
xor %r16, %r16, %r16
|
||||
xor %r17, %r17, %r17
|
||||
xor %r18, %r18, %r18
|
||||
xor %r19, %r19, %r19
|
||||
xor %r20, %r20, %r20
|
||||
xor %r21, %r21, %r21
|
||||
xor %r22, %r22, %r22
|
||||
xor %r23, %r23, %r23
|
||||
xor %r24, %r24, %r24
|
||||
xor %r25, %r25, %r25
|
||||
xor %r26, %r26, %r26
|
||||
xor %r27, %r27, %r27
|
||||
xor %r28, %r28, %r28
|
||||
xor %r29, %r29, %r29
|
||||
xor %r30, %r30, %r30
|
||||
xor %r31, %r31, %r31
|
||||
lis %r4, __ram_start__@h
|
||||
ori %r4, %r4, __ram_start__@l
|
||||
lis %r5, __ram_end__@h
|
||||
ori %r5, %r5, __ram_end__@l
|
||||
.cleareccloop:
|
||||
cmpl %cr0, %r4, %r5
|
||||
bge %cr0, .cleareccend
|
||||
stmw %r16, 0(%r4)
|
||||
addi %r4, %r4, 64
|
||||
b .cleareccloop
|
||||
.cleareccend:
|
||||
|
||||
/*
|
||||
* Branch prediction enabled.
|
||||
*/
|
||||
li %r3, BOOT_BUCSR_DEFAULT
|
||||
mtspr 1013, %r3 /* BUCSR */
|
||||
|
||||
blr
|
||||
#endif /* BOOT_PERFORM_CORE_INIT */
|
||||
|
||||
/*
|
||||
* Exception vectors initialization.
|
||||
*/
|
||||
.align 2
|
||||
_ivinit:
|
||||
/* MSR initialization.*/
|
||||
lis %r3, BOOT_MSR_DEFAULT@h
|
||||
ori %r3, %r3, BOOT_MSR_DEFAULT@l
|
||||
mtMSR %r3
|
||||
|
||||
/* IVPR initialization.*/
|
||||
lis %r3, __ivpr_base__@h
|
||||
ori %r3, %r3, __ivpr_base__@l
|
||||
mtIVPR %r3
|
||||
|
||||
blr
|
||||
|
||||
.section .ivors, "ax"
|
||||
|
||||
.globl IVORS
|
||||
IVORS:
|
||||
b _IVOR0
|
||||
.align 4
|
||||
b _IVOR1
|
||||
.align 4
|
||||
b _IVOR2
|
||||
.align 4
|
||||
b _IVOR3
|
||||
.align 4
|
||||
b _IVOR4
|
||||
.align 4
|
||||
b _IVOR5
|
||||
.align 4
|
||||
b _IVOR6
|
||||
.align 4
|
||||
b _IVOR7
|
||||
.align 4
|
||||
b _IVOR8
|
||||
.align 4
|
||||
b _IVOR9
|
||||
.align 4
|
||||
b _IVOR10
|
||||
.align 4
|
||||
b _IVOR11
|
||||
.align 4
|
||||
b _IVOR12
|
||||
.align 4
|
||||
b _IVOR13
|
||||
.align 4
|
||||
b _IVOR14
|
||||
.align 4
|
||||
b _IVOR15
|
||||
|
||||
.section .handlers, "ax"
|
||||
|
||||
/*
|
||||
* Default IVOR handlers.
|
||||
*/
|
||||
.align 2
|
||||
.weak _IVOR0, _IVOR1, _IVOR2, _IVOR3, _IVOR4, _IVOR5
|
||||
.weak _IVOR6, _IVOR7, _IVOR8, _IVOR9, _IVOR10, _IVOR11
|
||||
.weak _IVOR12, _IVOR13, _IVOR14, _IVOR15
|
||||
_IVOR0:
|
||||
_IVOR1:
|
||||
_IVOR2:
|
||||
_IVOR3:
|
||||
_IVOR5:
|
||||
_IVOR6:
|
||||
_IVOR7:
|
||||
_IVOR8:
|
||||
_IVOR9:
|
||||
_IVOR11:
|
||||
_IVOR12:
|
||||
_IVOR13:
|
||||
_IVOR14:
|
||||
_IVOR15:
|
||||
.global _unhandled_exception
|
||||
_unhandled_exception:
|
||||
b _unhandled_exception
|
||||
|
||||
#endif /* !defined(__DOXYGEN__) */
|
||||
|
||||
/** @} */
|
||||
|
|
@ -1,93 +0,0 @@
|
|||
/*
|
||||
ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
|
||||
|
||||
Licensed under the Apache License, Version 2.0 (the "License");
|
||||
you may not use this file except in compliance with the License.
|
||||
You may obtain a copy of the License at
|
||||
|
||||
http://www.apache.org/licenses/LICENSE-2.0
|
||||
|
||||
Unless required by applicable law or agreed to in writing, software
|
||||
distributed under the License is distributed on an "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
See the License for the specific language governing permissions and
|
||||
limitations under the License.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file SPC560Bxx/intc.h
|
||||
* @brief SPC560Bxx INTC module header.
|
||||
*
|
||||
* @addtogroup INTC
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifndef _INTC_H_
|
||||
#define _INTC_H_
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Module constants. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @name INTC addresses
|
||||
* @{
|
||||
*/
|
||||
#define INTC_BASE 0xFFF48000
|
||||
#define INTC_IACKR_ADDR (INTC_BASE + 0x10)
|
||||
#define INTC_EOIR_ADDR (INTC_BASE + 0x18)
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @brief INTC priority levels.
|
||||
*/
|
||||
#define INTC_PRIORITY_LEVELS 16U
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Module pre-compile time settings. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Derived constants and error checks. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Module data structures and types. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Module macros. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @name INTC-related macros
|
||||
* @{
|
||||
*/
|
||||
#define INTC_BCR (*((volatile uint32_t *)(INTC_BASE + 0)))
|
||||
#define INTC_CPR(n) (*((volatile uint32_t *)(INTC_BASE + 8 + ((n) * sizeof (uint32_t)))))
|
||||
#define INTC_IACKR(n) (*((volatile uint32_t *)(INTC_BASE + 0x10 + ((n) * sizeof (uint32_t)))))
|
||||
#define INTC_EOIR(n) (*((volatile uint32_t *)(INTC_BASE + 0x18 + ((n) * sizeof (uint32_t)))))
|
||||
#define INTC_PSR(n) (*((volatile uint8_t *)(INTC_BASE + 0x40 + ((n) * sizeof (uint8_t)))))
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @brief Core selection macros for PSR register.
|
||||
*/
|
||||
#define INTC_PSR_CORE0 0x00
|
||||
|
||||
/**
|
||||
* @brief PSR register content helper
|
||||
*/
|
||||
#define INTC_PSR_ENABLE(cores, prio) ((uint32_t)(cores) | (uint32_t)(prio))
|
||||
|
||||
/*===========================================================================*/
|
||||
/* External declarations. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Module inline functions. */
|
||||
/*===========================================================================*/
|
||||
|
||||
#endif /* _INTC_H_ */
|
||||
|
||||
/** @} */
|
||||
|
|
@ -1,83 +0,0 @@
|
|||
/*
|
||||
ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
|
||||
|
||||
Licensed under the Apache License, Version 2.0 (the "License");
|
||||
you may not use this file except in compliance with the License.
|
||||
You may obtain a copy of the License at
|
||||
|
||||
http://www.apache.org/licenses/LICENSE-2.0
|
||||
|
||||
Unless required by applicable law or agreed to in writing, software
|
||||
distributed under the License is distributed on an "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
See the License for the specific language governing permissions and
|
||||
limitations under the License.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file SPC560Bxx/ppcparams.h
|
||||
* @brief PowerPC parameters for the SPC560Bxx.
|
||||
*
|
||||
* @defgroup PPC_SPC560Bxx SPC560Bxx Specific Parameters
|
||||
* @ingroup PPC_SPECIFIC
|
||||
* @details This file contains the PowerPC specific parameters for the
|
||||
* SPC560Bxx platform.
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifndef _PPCPARAMS_H_
|
||||
#define _PPCPARAMS_H_
|
||||
|
||||
/**
|
||||
* @brief Family identification macro.
|
||||
*/
|
||||
#define PPC_SPC560Bxx
|
||||
|
||||
/**
|
||||
* @brief PPC core model.
|
||||
*/
|
||||
#define PPC_VARIANT PPC_VARIANT_e200z0
|
||||
|
||||
/**
|
||||
* @brief Number of cores.
|
||||
*/
|
||||
#define PPC_CORE_NUMBER 1
|
||||
|
||||
/**
|
||||
* @brief Number of writable bits in IVPR register.
|
||||
*/
|
||||
#define PPC_IVPR_BITS 20
|
||||
|
||||
/**
|
||||
* @brief IVORx registers support.
|
||||
*/
|
||||
#define PPC_SUPPORTS_IVORS FALSE
|
||||
|
||||
/**
|
||||
* @brief Book E instruction set support.
|
||||
*/
|
||||
#define PPC_SUPPORTS_BOOKE FALSE
|
||||
|
||||
/**
|
||||
* @brief VLE instruction set support.
|
||||
*/
|
||||
#define PPC_SUPPORTS_VLE TRUE
|
||||
|
||||
/**
|
||||
* @brief Supports VLS Load/Store Multiple Volatile instructions.
|
||||
*/
|
||||
#define PPC_SUPPORTS_VLE_MULTI TRUE
|
||||
|
||||
/**
|
||||
* @brief Supports the decrementer timer.
|
||||
*/
|
||||
#define PPC_SUPPORTS_DECREMENTER FALSE
|
||||
|
||||
/**
|
||||
* @brief Number of interrupt sources.
|
||||
*/
|
||||
#define PPC_NUM_VECTORS 234
|
||||
|
||||
#endif /* _PPCPARAMS_H_ */
|
||||
|
||||
/** @} */
|
||||
|
|
@ -1,114 +0,0 @@
|
|||
/*
|
||||
ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
|
||||
|
||||
Licensed under the Apache License, Version 2.0 (the "License");
|
||||
you may not use this file except in compliance with the License.
|
||||
You may obtain a copy of the License at
|
||||
|
||||
http://www.apache.org/licenses/LICENSE-2.0
|
||||
|
||||
Unless required by applicable law or agreed to in writing, software
|
||||
distributed under the License is distributed on an "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
See the License for the specific language governing permissions and
|
||||
limitations under the License.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file boot.h
|
||||
* @brief Boot parameters for the SPC560Dxx.
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifndef _BOOT_H_
|
||||
#define _BOOT_H_
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Module constants. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @name BUCSR registers definitions
|
||||
* @{
|
||||
*/
|
||||
#define BUCSR_BPEN 0x00000001
|
||||
#define BUCSR_BALLOC_BFI 0x00000200
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @name MSR register definitions
|
||||
* @{
|
||||
*/
|
||||
#define MSR_WE 0x00040000
|
||||
#define MSR_CE 0x00020000
|
||||
#define MSR_EE 0x00008000
|
||||
#define MSR_PR 0x00004000
|
||||
#define MSR_ME 0x00001000
|
||||
#define MSR_DE 0x00000200
|
||||
#define MSR_IS 0x00000020
|
||||
#define MSR_DS 0x00000010
|
||||
#define MSR_RI 0x00000002
|
||||
/** @} */
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Module pre-compile time settings. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*
|
||||
* BUCSR default settings.
|
||||
*/
|
||||
#if !defined(BOOT_BUCSR_DEFAULT) || defined(__DOXYGEN__)
|
||||
#define BOOT_BUCSR_DEFAULT (BUCSR_BPEN | BUCSR_BALLOC_BFI)
|
||||
#endif
|
||||
|
||||
/*
|
||||
* MSR default settings.
|
||||
*/
|
||||
#if !defined(BOOT_MSR_DEFAULT) || defined(__DOXYGEN__)
|
||||
#define BOOT_MSR_DEFAULT (MSR_WE | MSR_CE | MSR_ME)
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Boot default settings.
|
||||
*/
|
||||
#if !defined(BOOT_PERFORM_CORE_INIT) || defined(__DOXYGEN__)
|
||||
#define BOOT_PERFORM_CORE_INIT 1
|
||||
#endif
|
||||
|
||||
/*
|
||||
* VLE mode default settings.
|
||||
*/
|
||||
#if !defined(BOOT_USE_VLE) || defined(__DOXYGEN__)
|
||||
#define BOOT_USE_VLE 1
|
||||
#endif
|
||||
|
||||
/*
|
||||
* RAM relocation flag.
|
||||
*/
|
||||
#if !defined(BOOT_RELOCATE_IN_RAM) || defined(__DOXYGEN__)
|
||||
#define BOOT_RELOCATE_IN_RAM 0
|
||||
#endif
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Derived constants and error checks. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Module data structures and types. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Module macros. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* External declarations. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Module inline functions. */
|
||||
/*===========================================================================*/
|
||||
|
||||
#endif /* _BOOT_H_ */
|
||||
|
||||
/** @} */
|
||||
|
|
@ -1,214 +0,0 @@
|
|||
/*
|
||||
ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
|
||||
|
||||
Licensed under the Apache License, Version 2.0 (the "License");
|
||||
you may not use this file except in compliance with the License.
|
||||
You may obtain a copy of the License at
|
||||
|
||||
http://www.apache.org/licenses/LICENSE-2.0
|
||||
|
||||
Unless required by applicable law or agreed to in writing, software
|
||||
distributed under the License is distributed on an "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
See the License for the specific language governing permissions and
|
||||
limitations under the License.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file SPC560Dxx/boot.s
|
||||
* @brief SPC560Dxx boot-related code.
|
||||
*
|
||||
* @addtogroup PPC_BOOT
|
||||
* @{
|
||||
*/
|
||||
|
||||
#include "boot.h"
|
||||
|
||||
#if !defined(__DOXYGEN__)
|
||||
|
||||
/* BAM record.*/
|
||||
.section .boot, "ax"
|
||||
|
||||
.long 0x015A0000
|
||||
.long _reset_address
|
||||
|
||||
.align 2
|
||||
.globl _reset_address
|
||||
.type _reset_address, @function
|
||||
_reset_address:
|
||||
#if BOOT_PERFORM_CORE_INIT
|
||||
bl _coreinit
|
||||
#endif
|
||||
bl _ivinit
|
||||
|
||||
#if BOOT_RELOCATE_IN_RAM
|
||||
/*
|
||||
* Image relocation in RAM.
|
||||
*/
|
||||
lis r4, __ram_reloc_start__@h
|
||||
ori r4, r4, __ram_reloc_start__@l
|
||||
lis r5, __ram_reloc_dest__@h
|
||||
ori r5, r5, __ram_reloc_dest__@l
|
||||
lis r6, __ram_reloc_end__@h
|
||||
ori r6, r6, __ram_reloc_end__@l
|
||||
.relloop:
|
||||
cmpl cr0, r4, r6
|
||||
bge cr0, .relend
|
||||
lwz r7, 0(r4)
|
||||
addi r4, r4, 4
|
||||
stw r7, 0(r5)
|
||||
addi r5, r5, 4
|
||||
b .relloop
|
||||
.relend:
|
||||
lis r3, _boot_address@h
|
||||
ori r3, r3, _boot_address@l
|
||||
mtctr r3
|
||||
bctrl
|
||||
#else
|
||||
b _boot_address
|
||||
#endif
|
||||
|
||||
#if BOOT_PERFORM_CORE_INIT
|
||||
.align 2
|
||||
_coreinit:
|
||||
/*
|
||||
* RAM clearing, this device requires a write to all RAM location in
|
||||
* order to initialize the ECC detection hardware, this is going to
|
||||
* slow down the startup but there is no way around.
|
||||
*/
|
||||
xor r0, r0, r0
|
||||
xor r1, r1, r1
|
||||
xor r2, r2, r2
|
||||
xor r3, r3, r3
|
||||
xor r4, r4, r4
|
||||
xor r5, r5, r5
|
||||
xor r6, r6, r6
|
||||
xor r7, r7, r7
|
||||
xor r8, r8, r8
|
||||
xor r9, r9, r9
|
||||
xor r10, r10, r10
|
||||
xor r11, r11, r11
|
||||
xor r12, r12, r12
|
||||
xor r13, r13, r13
|
||||
xor r14, r14, r14
|
||||
xor r15, r15, r15
|
||||
xor r16, r16, r16
|
||||
xor r17, r17, r17
|
||||
xor r18, r18, r18
|
||||
xor r19, r19, r19
|
||||
xor r20, r20, r20
|
||||
xor r21, r21, r21
|
||||
xor r22, r22, r22
|
||||
xor r23, r23, r23
|
||||
xor r24, r24, r24
|
||||
xor r25, r25, r25
|
||||
xor r26, r26, r26
|
||||
xor r27, r27, r27
|
||||
xor r28, r28, r28
|
||||
xor r29, r29, r29
|
||||
xor r30, r30, r30
|
||||
xor r31, r31, r31
|
||||
lis r4, __ram_start__@h
|
||||
ori r4, r4, __ram_start__@l
|
||||
lis r5, __ram_end__@h
|
||||
ori r5, r5, __ram_end__@l
|
||||
.cleareccloop:
|
||||
cmpl cr0, r4, r5
|
||||
bge cr0, .cleareccend
|
||||
stmw r16, 0(r4)
|
||||
addi r4, r4, 64
|
||||
b .cleareccloop
|
||||
.cleareccend:
|
||||
|
||||
/*
|
||||
* Branch prediction enabled.
|
||||
*/
|
||||
li r3, BOOT_BUCSR_DEFAULT
|
||||
mtspr 1013, r3 /* BUCSR */
|
||||
|
||||
blr
|
||||
#endif /* BOOT_PERFORM_CORE_INIT */
|
||||
|
||||
/*
|
||||
* Exception vectors initialization.
|
||||
*/
|
||||
.align 2
|
||||
_ivinit:
|
||||
/* MSR initialization.*/
|
||||
lis r3, BOOT_MSR_DEFAULT@h
|
||||
ori r3, r3, BOOT_MSR_DEFAULT@l
|
||||
mtMSR r3
|
||||
|
||||
/* IVPR initialization.*/
|
||||
lis r3, __ivpr_base__@h
|
||||
ori r3, r3, __ivpr_base__@l
|
||||
mtIVPR r3
|
||||
|
||||
blr
|
||||
|
||||
.section .ivors, "ax"
|
||||
|
||||
.globl IVORS
|
||||
IVORS:
|
||||
b _IVOR0
|
||||
.align 4
|
||||
b _IVOR1
|
||||
.align 4
|
||||
b _IVOR2
|
||||
.align 4
|
||||
b _IVOR3
|
||||
.align 4
|
||||
b _IVOR4
|
||||
.align 4
|
||||
b _IVOR5
|
||||
.align 4
|
||||
b _IVOR6
|
||||
.align 4
|
||||
b _IVOR7
|
||||
.align 4
|
||||
b _IVOR8
|
||||
.align 4
|
||||
b _IVOR9
|
||||
.align 4
|
||||
b _IVOR10
|
||||
.align 4
|
||||
b _IVOR11
|
||||
.align 4
|
||||
b _IVOR12
|
||||
.align 4
|
||||
b _IVOR13
|
||||
.align 4
|
||||
b _IVOR14
|
||||
.align 4
|
||||
b _IVOR15
|
||||
|
||||
.section .handlers, "ax"
|
||||
|
||||
/*
|
||||
* Default IVOR handlers.
|
||||
*/
|
||||
.align 2
|
||||
.weak _IVOR0, _IVOR1, _IVOR2, _IVOR3, _IVOR4, _IVOR5
|
||||
.weak _IVOR6, _IVOR7, _IVOR8, _IVOR9, _IVOR10, _IVOR11
|
||||
.weak _IVOR12, _IVOR13, _IVOR14, _IVOR15
|
||||
_IVOR0:
|
||||
_IVOR1:
|
||||
_IVOR2:
|
||||
_IVOR3:
|
||||
_IVOR5:
|
||||
_IVOR6:
|
||||
_IVOR7:
|
||||
_IVOR8:
|
||||
_IVOR9:
|
||||
_IVOR11:
|
||||
_IVOR12:
|
||||
_IVOR13:
|
||||
_IVOR14:
|
||||
_IVOR15:
|
||||
.global _unhandled_exception
|
||||
_unhandled_exception:
|
||||
b _unhandled_exception
|
||||
|
||||
#endif /* !defined(__DOXYGEN__) */
|
||||
|
||||
/** @} */
|
||||
|
|
@ -1,200 +0,0 @@
|
|||
/*
|
||||
ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
|
||||
|
||||
Licensed under the Apache License, Version 2.0 (the "License");
|
||||
you may not use this file except in compliance with the License.
|
||||
You may obtain a copy of the License at
|
||||
|
||||
http://www.apache.org/licenses/LICENSE-2.0
|
||||
|
||||
Unless required by applicable law or agreed to in writing, software
|
||||
distributed under the License is distributed on an "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
See the License for the specific language governing permissions and
|
||||
limitations under the License.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file SPC560Dxx/boot.s
|
||||
* @brief SPC560Dxx boot-related code.
|
||||
*
|
||||
* @addtogroup PPC_BOOT
|
||||
* @{
|
||||
*/
|
||||
|
||||
#include "boot.h"
|
||||
|
||||
#if !defined(__DOXYGEN__)
|
||||
|
||||
.extern _boot_address
|
||||
.extern __ram_start__
|
||||
.extern __ram_end__
|
||||
.extern __ivpr_base__
|
||||
|
||||
.extern _IVOR0, _IVOR1, _IVOR2, _IVOR3, _IVOR4, _IVOR5
|
||||
.extern _IVOR6, _IVOR7, _IVOR8, _IVOR9, _IVOR10, _IVOR11
|
||||
.extern _IVOR12, _IVOR13, _IVOR14, _IVOR15
|
||||
|
||||
/* BAM record.*/
|
||||
.section .boot, 16
|
||||
|
||||
.long 0x015A0000
|
||||
.long _reset_address
|
||||
|
||||
.align 4
|
||||
.globl _reset_address
|
||||
.type _reset_address, @function
|
||||
_reset_address:
|
||||
#if BOOT_PERFORM_CORE_INIT
|
||||
se_bl _coreinit
|
||||
#endif
|
||||
se_bl _ivinit
|
||||
|
||||
#if BOOT_RELOCATE_IN_RAM
|
||||
/*
|
||||
* Image relocation in RAM.
|
||||
*/
|
||||
e_lis r4, __ram_reloc_start__@h
|
||||
e_or2i r4, r4, __ram_reloc_start__@l
|
||||
e_lis r5, __ram_reloc_dest__@h
|
||||
e_or2i r5, r5, __ram_reloc_dest__@l
|
||||
e_lis r6, __ram_reloc_end__@h
|
||||
e_or2i r6, r6, __ram_reloc_end__@l
|
||||
.relloop:
|
||||
se_cmpl r4, r6
|
||||
se_bge .relend
|
||||
se_lwz r7, 0(r4)
|
||||
se_addi r4, 4
|
||||
se_stw r7, 0(r5)
|
||||
se_addi r5, 4
|
||||
se_b .relloop
|
||||
.relend:
|
||||
e_lis r3, _boot_address@h
|
||||
e_or2i r3, _boot_address@l
|
||||
mtctr r3
|
||||
se_bctrl
|
||||
#else
|
||||
e_b _boot_address
|
||||
#endif
|
||||
|
||||
#if BOOT_PERFORM_CORE_INIT
|
||||
.align 4
|
||||
_coreinit:
|
||||
/*
|
||||
* RAM clearing, this device requires a write to all RAM location in
|
||||
* order to initialize the ECC detection hardware, this is going to
|
||||
* slow down the startup but there is no way around.
|
||||
*/
|
||||
xor r0, r0, r0
|
||||
xor r1, r1, r1
|
||||
xor r2, r2, r2
|
||||
xor r3, r3, r3
|
||||
xor r4, r4, r4
|
||||
xor r5, r5, r5
|
||||
xor r6, r6, r6
|
||||
xor r7, r7, r7
|
||||
xor r8, r8, r8
|
||||
xor r9, r9, r9
|
||||
xor r10, r10, r10
|
||||
xor r11, r11, r11
|
||||
xor r12, r12, r12
|
||||
xor r13, r13, r13
|
||||
xor r14, r14, r14
|
||||
xor r15, r15, r15
|
||||
xor r16, r16, r16
|
||||
xor r17, r17, r17
|
||||
xor r18, r18, r18
|
||||
xor r19, r19, r19
|
||||
xor r20, r20, r20
|
||||
xor r21, r21, r21
|
||||
xor r22, r22, r22
|
||||
xor r23, r23, r23
|
||||
xor r24, r24, r24
|
||||
xor r25, r25, r25
|
||||
xor r26, r26, r26
|
||||
xor r27, r27, r27
|
||||
xor r28, r28, r28
|
||||
xor r29, r29, r29
|
||||
xor r30, r30, r30
|
||||
xor r31, r31, r31
|
||||
e_lis r4, __ram_start__@h
|
||||
e_or2i r4, __ram_start__@l
|
||||
e_lis r5, __ram_end__@h
|
||||
e_or2i r5, __ram_end__@l
|
||||
.cleareccloop:
|
||||
se_cmpl r4, r5
|
||||
se_bge .cleareccend
|
||||
e_stmw r16, 0(r4)
|
||||
e_addi r4, r4, 64
|
||||
se_b .cleareccloop
|
||||
.cleareccend:
|
||||
|
||||
/*
|
||||
* Branch prediction enabled.
|
||||
*/
|
||||
e_li r3, BOOT_BUCSR_DEFAULT
|
||||
mtspr 1013, r3 /* BUCSR */
|
||||
|
||||
se_blr
|
||||
#endif /* BOOT_PERFORM_CORE_INIT */
|
||||
|
||||
/*
|
||||
* Exception vectors initialization.
|
||||
*/
|
||||
.align 4
|
||||
_ivinit:
|
||||
/* MSR initialization.*/
|
||||
e_lis r3, BOOT_MSR_DEFAULT@h
|
||||
e_ori r3, r3, BOOT_MSR_DEFAULT@l
|
||||
mtMSR r3
|
||||
|
||||
/* IVPR initialization.*/
|
||||
e_lis r3, __ivpr_base__@h
|
||||
e_or2i r3, __ivpr_base__@l
|
||||
mtIVPR r3
|
||||
|
||||
se_blr
|
||||
|
||||
.section .ivors, text_vle
|
||||
.align 16
|
||||
.globl IVORS
|
||||
IVORS:
|
||||
e_b _IVOR0
|
||||
.align 16
|
||||
e_b _IVOR1
|
||||
.align 16
|
||||
e_b _IVOR2
|
||||
.align 16
|
||||
e_b _IVOR3
|
||||
.align 16
|
||||
e_b _IVOR4
|
||||
.align 16
|
||||
e_b _IVOR5
|
||||
.align 16
|
||||
e_b _IVOR6
|
||||
.align 16
|
||||
e_b _IVOR7
|
||||
.align 16
|
||||
e_b _IVOR8
|
||||
.align 16
|
||||
e_b _IVOR9
|
||||
.align 16
|
||||
e_b _IVOR10
|
||||
.align 16
|
||||
e_b _IVOR11
|
||||
.align 16
|
||||
e_b _IVOR12
|
||||
.align 16
|
||||
e_b _IVOR13
|
||||
.align 16
|
||||
e_b _IVOR14
|
||||
.align 16
|
||||
e_b _IVOR15
|
||||
|
||||
.section .handlers, text_vle
|
||||
.align 16
|
||||
|
||||
|
||||
#endif /* !defined(__DOXYGEN__) */
|
||||
|
||||
/** @} */
|
||||
|
|
@ -1,93 +0,0 @@
|
|||
/*
|
||||
ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
|
||||
|
||||
Licensed under the Apache License, Version 2.0 (the "License");
|
||||
you may not use this file except in compliance with the License.
|
||||
You may obtain a copy of the License at
|
||||
|
||||
http://www.apache.org/licenses/LICENSE-2.0
|
||||
|
||||
Unless required by applicable law or agreed to in writing, software
|
||||
distributed under the License is distributed on an "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
See the License for the specific language governing permissions and
|
||||
limitations under the License.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file SPC560Dxx/intc.h
|
||||
* @brief SPC560Dxx INTC module header.
|
||||
*
|
||||
* @addtogroup INTC
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifndef _INTC_H_
|
||||
#define _INTC_H_
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Module constants. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @name INTC addresses
|
||||
* @{
|
||||
*/
|
||||
#define INTC_BASE 0xFFF48000
|
||||
#define INTC_IACKR_ADDR (INTC_BASE + 0x10)
|
||||
#define INTC_EOIR_ADDR (INTC_BASE + 0x18)
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @brief INTC priority levels.
|
||||
*/
|
||||
#define INTC_PRIORITY_LEVELS 16U
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Module pre-compile time settings. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Derived constants and error checks. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Module data structures and types. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Module macros. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @name INTC-related macros
|
||||
* @{
|
||||
*/
|
||||
#define INTC_BCR (*((volatile uint32_t *)(INTC_BASE + 0)))
|
||||
#define INTC_CPR(n) (*((volatile uint32_t *)(INTC_BASE + 8 + ((n) * sizeof (uint32_t)))))
|
||||
#define INTC_IACKR(n) (*((volatile uint32_t *)(INTC_BASE + 0x10 + ((n) * sizeof (uint32_t)))))
|
||||
#define INTC_EOIR(n) (*((volatile uint32_t *)(INTC_BASE + 0x18 + ((n) * sizeof (uint32_t)))))
|
||||
#define INTC_PSR(n) (*((volatile uint8_t *)(INTC_BASE + 0x40 + ((n) * sizeof (uint8_t)))))
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @brief Core selection macros for PSR register.
|
||||
*/
|
||||
#define INTC_PSR_CORE0 0x00
|
||||
|
||||
/**
|
||||
* @brief PSR register content helper
|
||||
*/
|
||||
#define INTC_PSR_ENABLE(cores, prio) ((uint32_t)(cores) | (uint32_t)(prio))
|
||||
|
||||
/*===========================================================================*/
|
||||
/* External declarations. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Module inline functions. */
|
||||
/*===========================================================================*/
|
||||
|
||||
#endif /* _INTC_H_ */
|
||||
|
||||
/** @} */
|
||||
|
|
@ -1,83 +0,0 @@
|
|||
/*
|
||||
ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
|
||||
|
||||
Licensed under the Apache License, Version 2.0 (the "License");
|
||||
you may not use this file except in compliance with the License.
|
||||
You may obtain a copy of the License at
|
||||
|
||||
http://www.apache.org/licenses/LICENSE-2.0
|
||||
|
||||
Unless required by applicable law or agreed to in writing, software
|
||||
distributed under the License is distributed on an "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
See the License for the specific language governing permissions and
|
||||
limitations under the License.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file SPC560Dxx/ppcparams.h
|
||||
* @brief PowerPC parameters for the SPC560Dxx.
|
||||
*
|
||||
* @defgroup PPC_SPC560Dxx SPC560Dxx Specific Parameters
|
||||
* @ingroup PPC_SPECIFIC
|
||||
* @details This file contains the PowerPC specific parameters for the
|
||||
* SPC560Dxx platform.
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifndef _PPCPARAMS_H_
|
||||
#define _PPCPARAMS_H_
|
||||
|
||||
/**
|
||||
* @brief Family identification macro.
|
||||
*/
|
||||
#define PPC_SPC560Dxx
|
||||
|
||||
/**
|
||||
* @brief PPC core model.
|
||||
*/
|
||||
#define PPC_VARIANT PPC_VARIANT_e200z0
|
||||
|
||||
/**
|
||||
* @brief Number of cores.
|
||||
*/
|
||||
#define PPC_CORE_NUMBER 1
|
||||
|
||||
/**
|
||||
* @brief Number of writable bits in IVPR register.
|
||||
*/
|
||||
#define PPC_IVPR_BITS 20
|
||||
|
||||
/**
|
||||
* @brief IVORx registers support.
|
||||
*/
|
||||
#define PPC_SUPPORTS_IVORS FALSE
|
||||
|
||||
/**
|
||||
* @brief Book E instruction set support.
|
||||
*/
|
||||
#define PPC_SUPPORTS_BOOKE FALSE
|
||||
|
||||
/**
|
||||
* @brief VLE instruction set support.
|
||||
*/
|
||||
#define PPC_SUPPORTS_VLE TRUE
|
||||
|
||||
/**
|
||||
* @brief Supports VLS Load/Store Multiple Volatile instructions.
|
||||
*/
|
||||
#define PPC_SUPPORTS_VLE_MULTI TRUE
|
||||
|
||||
/**
|
||||
* @brief Supports the decrementer timer.
|
||||
*/
|
||||
#define PPC_SUPPORTS_DECREMENTER FALSE
|
||||
|
||||
/**
|
||||
* @brief Number of interrupt sources.
|
||||
*/
|
||||
#define PPC_NUM_VECTORS 155
|
||||
|
||||
#endif /* _PPCPARAMS_H_ */
|
||||
|
||||
/** @} */
|
||||
|
|
@ -1,114 +0,0 @@
|
|||
/*
|
||||
ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
|
||||
|
||||
Licensed under the Apache License, Version 2.0 (the "License");
|
||||
you may not use this file except in compliance with the License.
|
||||
You may obtain a copy of the License at
|
||||
|
||||
http://www.apache.org/licenses/LICENSE-2.0
|
||||
|
||||
Unless required by applicable law or agreed to in writing, software
|
||||
distributed under the License is distributed on an "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
See the License for the specific language governing permissions and
|
||||
limitations under the License.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file boot.h
|
||||
* @brief Boot parameters for the SPC560Pxx.
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifndef _BOOT_H_
|
||||
#define _BOOT_H_
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Module constants. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @name BUCSR registers definitions
|
||||
* @{
|
||||
*/
|
||||
#define BUCSR_BPEN 0x00000001
|
||||
#define BUCSR_BALLOC_BFI 0x00000200
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @name MSR register definitions
|
||||
* @{
|
||||
*/
|
||||
#define MSR_WE 0x00040000
|
||||
#define MSR_CE 0x00020000
|
||||
#define MSR_EE 0x00008000
|
||||
#define MSR_PR 0x00004000
|
||||
#define MSR_ME 0x00001000
|
||||
#define MSR_DE 0x00000200
|
||||
#define MSR_IS 0x00000020
|
||||
#define MSR_DS 0x00000010
|
||||
#define MSR_RI 0x00000002
|
||||
/** @} */
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Module pre-compile time settings. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*
|
||||
* BUCSR default settings.
|
||||
*/
|
||||
#if !defined(BOOT_BUCSR_DEFAULT) || defined(__DOXYGEN__)
|
||||
#define BOOT_BUCSR_DEFAULT (BUCSR_BPEN | BUCSR_BALLOC_BFI)
|
||||
#endif
|
||||
|
||||
/*
|
||||
* MSR default settings.
|
||||
*/
|
||||
#if !defined(BOOT_MSR_DEFAULT) || defined(__DOXYGEN__)
|
||||
#define BOOT_MSR_DEFAULT (MSR_WE | MSR_CE | MSR_ME)
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Boot default settings.
|
||||
*/
|
||||
#if !defined(BOOT_PERFORM_CORE_INIT) || defined(__DOXYGEN__)
|
||||
#define BOOT_PERFORM_CORE_INIT 1
|
||||
#endif
|
||||
|
||||
/*
|
||||
* VLE mode default settings.
|
||||
*/
|
||||
#if !defined(BOOT_USE_VLE) || defined(__DOXYGEN__)
|
||||
#define BOOT_USE_VLE 1
|
||||
#endif
|
||||
|
||||
/*
|
||||
* RAM relocation flag.
|
||||
*/
|
||||
#if !defined(BOOT_RELOCATE_IN_RAM) || defined(__DOXYGEN__)
|
||||
#define BOOT_RELOCATE_IN_RAM 0
|
||||
#endif
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Derived constants and error checks. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Module data structures and types. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Module macros. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* External declarations. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Module inline functions. */
|
||||
/*===========================================================================*/
|
||||
|
||||
#endif /* _BOOT_H_ */
|
||||
|
||||
/** @} */
|
||||
|
|
@ -1,214 +0,0 @@
|
|||
/*
|
||||
ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
|
||||
|
||||
Licensed under the Apache License, Version 2.0 (the "License");
|
||||
you may not use this file except in compliance with the License.
|
||||
You may obtain a copy of the License at
|
||||
|
||||
http://www.apache.org/licenses/LICENSE-2.0
|
||||
|
||||
Unless required by applicable law or agreed to in writing, software
|
||||
distributed under the License is distributed on an "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
See the License for the specific language governing permissions and
|
||||
limitations under the License.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file SPC560Pxx/boot.s
|
||||
* @brief SPC560Pxx boot-related code.
|
||||
*
|
||||
* @addtogroup PPC_BOOT
|
||||
* @{
|
||||
*/
|
||||
|
||||
#include "boot.h"
|
||||
|
||||
#if !defined(__DOXYGEN__)
|
||||
|
||||
/* BAM record.*/
|
||||
.section .boot, "ax"
|
||||
|
||||
.long 0x015A0000
|
||||
.long _reset_address
|
||||
|
||||
.align 2
|
||||
.globl _reset_address
|
||||
.type _reset_address, @function
|
||||
_reset_address:
|
||||
#if BOOT_PERFORM_CORE_INIT
|
||||
bl _coreinit
|
||||
#endif
|
||||
bl _ivinit
|
||||
|
||||
#if BOOT_RELOCATE_IN_RAM
|
||||
/*
|
||||
* Image relocation in RAM.
|
||||
*/
|
||||
lis %r4, __ram_reloc_start__@h
|
||||
ori %r4, %r4, __ram_reloc_start__@l
|
||||
lis %r5, __ram_reloc_dest__@h
|
||||
ori %r5, %r5, __ram_reloc_dest__@l
|
||||
lis %r6, __ram_reloc_end__@h
|
||||
ori %r6, %r6, __ram_reloc_end__@l
|
||||
.relloop:
|
||||
cmpl cr0, %r4, %r6
|
||||
bge cr0, .relend
|
||||
lwz %r7, 0(%r4)
|
||||
addi %r4, %r4, 4
|
||||
stw %r7, 0(%r5)
|
||||
addi %r5, %r5, 4
|
||||
b .relloop
|
||||
.relend:
|
||||
lis %r3, _boot_address@h
|
||||
ori %r3, %r3, _boot_address@l
|
||||
mtctr %r3
|
||||
bctrl
|
||||
#else
|
||||
b _boot_address
|
||||
#endif
|
||||
|
||||
#if BOOT_PERFORM_CORE_INIT
|
||||
.align 2
|
||||
_coreinit:
|
||||
/*
|
||||
* RAM clearing, this device requires a write to all RAM location in
|
||||
* order to initialize the ECC detection hardware, this is going to
|
||||
* slow down the startup but there is no way around.
|
||||
*/
|
||||
xor %r0, %r0, %r0
|
||||
xor %r1, %r1, %r1
|
||||
xor %r2, %r2, %r2
|
||||
xor %r3, %r3, %r3
|
||||
xor %r4, %r4, %r4
|
||||
xor %r5, %r5, %r5
|
||||
xor %r6, %r6, %r6
|
||||
xor %r7, %r7, %r7
|
||||
xor %r8, %r8, %r8
|
||||
xor %r9, %r9, %r9
|
||||
xor %r10, %r10, %r10
|
||||
xor %r11, %r11, %r11
|
||||
xor %r12, %r12, %r12
|
||||
xor %r13, %r13, %r13
|
||||
xor %r14, %r14, %r14
|
||||
xor %r15, %r15, %r15
|
||||
xor %r16, %r16, %r16
|
||||
xor %r17, %r17, %r17
|
||||
xor %r18, %r18, %r18
|
||||
xor %r19, %r19, %r19
|
||||
xor %r20, %r20, %r20
|
||||
xor %r21, %r21, %r21
|
||||
xor %r22, %r22, %r22
|
||||
xor %r23, %r23, %r23
|
||||
xor %r24, %r24, %r24
|
||||
xor %r25, %r25, %r25
|
||||
xor %r26, %r26, %r26
|
||||
xor %r27, %r27, %r27
|
||||
xor %r28, %r28, %r28
|
||||
xor %r29, %r29, %r29
|
||||
xor %r30, %r30, %r30
|
||||
xor %r31, %r31, %r31
|
||||
lis %r4, __ram_start__@h
|
||||
ori %r4, %r4, __ram_start__@l
|
||||
lis %r5, __ram_end__@h
|
||||
ori %r5, %r5, __ram_end__@l
|
||||
.cleareccloop:
|
||||
cmpl %cr0, %r4, %r5
|
||||
bge %cr0, .cleareccend
|
||||
stmw %r16, 0(%r4)
|
||||
addi %r4, %r4, 64
|
||||
b .cleareccloop
|
||||
.cleareccend:
|
||||
|
||||
/*
|
||||
* Branch prediction enabled.
|
||||
*/
|
||||
li %r3, BOOT_BUCSR_DEFAULT
|
||||
mtspr 1013, %r3 /* BUCSR */
|
||||
|
||||
blr
|
||||
#endif /* BOOT_PERFORM_CORE_INIT */
|
||||
|
||||
/*
|
||||
* Exception vectors initialization.
|
||||
*/
|
||||
.align 2
|
||||
_ivinit:
|
||||
/* MSR initialization.*/
|
||||
lis %r3, BOOT_MSR_DEFAULT@h
|
||||
ori %r3, %r3, BOOT_MSR_DEFAULT@l
|
||||
mtMSR %r3
|
||||
|
||||
/* IVPR initialization.*/
|
||||
lis %r3, __ivpr_base__@h
|
||||
ori %r3, %r3, __ivpr_base__@l
|
||||
mtIVPR %r3
|
||||
|
||||
blr
|
||||
|
||||
.section .ivors, "ax"
|
||||
|
||||
.globl IVORS
|
||||
IVORS:
|
||||
b _IVOR0
|
||||
.align 4
|
||||
b _IVOR1
|
||||
.align 4
|
||||
b _IVOR2
|
||||
.align 4
|
||||
b _IVOR3
|
||||
.align 4
|
||||
b _IVOR4
|
||||
.align 4
|
||||
b _IVOR5
|
||||
.align 4
|
||||
b _IVOR6
|
||||
.align 4
|
||||
b _IVOR7
|
||||
.align 4
|
||||
b _IVOR8
|
||||
.align 4
|
||||
b _IVOR9
|
||||
.align 4
|
||||
b _IVOR10
|
||||
.align 4
|
||||
b _IVOR11
|
||||
.align 4
|
||||
b _IVOR12
|
||||
.align 4
|
||||
b _IVOR13
|
||||
.align 4
|
||||
b _IVOR14
|
||||
.align 4
|
||||
b _IVOR15
|
||||
|
||||
.section .handlers, "ax"
|
||||
|
||||
/*
|
||||
* Default IVOR handlers.
|
||||
*/
|
||||
.align 2
|
||||
.weak _IVOR0, _IVOR1, _IVOR2, _IVOR3, _IVOR4, _IVOR5
|
||||
.weak _IVOR6, _IVOR7, _IVOR8, _IVOR9, _IVOR10, _IVOR11
|
||||
.weak _IVOR12, _IVOR13, _IVOR14, _IVOR15
|
||||
_IVOR0:
|
||||
_IVOR1:
|
||||
_IVOR2:
|
||||
_IVOR3:
|
||||
_IVOR5:
|
||||
_IVOR6:
|
||||
_IVOR7:
|
||||
_IVOR8:
|
||||
_IVOR9:
|
||||
_IVOR11:
|
||||
_IVOR12:
|
||||
_IVOR13:
|
||||
_IVOR14:
|
||||
_IVOR15:
|
||||
.global _unhandled_exception
|
||||
_unhandled_exception:
|
||||
b _unhandled_exception
|
||||
|
||||
#endif /* !defined(__DOXYGEN__) */
|
||||
|
||||
/** @} */
|
||||
|
|
@ -1,93 +0,0 @@
|
|||
/*
|
||||
ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
|
||||
|
||||
Licensed under the Apache License, Version 2.0 (the "License");
|
||||
you may not use this file except in compliance with the License.
|
||||
You may obtain a copy of the License at
|
||||
|
||||
http://www.apache.org/licenses/LICENSE-2.0
|
||||
|
||||
Unless required by applicable law or agreed to in writing, software
|
||||
distributed under the License is distributed on an "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
See the License for the specific language governing permissions and
|
||||
limitations under the License.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file SPC560Pxx/intc.h
|
||||
* @brief SPC560Pxx INTC module header.
|
||||
*
|
||||
* @addtogroup INTC
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifndef _INTC_H_
|
||||
#define _INTC_H_
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Module constants. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @name INTC addresses
|
||||
* @{
|
||||
*/
|
||||
#define INTC_BASE 0xFFF48000
|
||||
#define INTC_IACKR_ADDR (INTC_BASE + 0x10)
|
||||
#define INTC_EOIR_ADDR (INTC_BASE + 0x18)
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @brief INTC priority levels.
|
||||
*/
|
||||
#define INTC_PRIORITY_LEVELS 16U
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Module pre-compile time settings. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Derived constants and error checks. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Module data structures and types. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Module macros. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @name INTC-related macros
|
||||
* @{
|
||||
*/
|
||||
#define INTC_BCR (*((volatile uint32_t *)(INTC_BASE + 0)))
|
||||
#define INTC_CPR(n) (*((volatile uint32_t *)(INTC_BASE + 8 + ((n) * sizeof (uint32_t)))))
|
||||
#define INTC_IACKR(n) (*((volatile uint32_t *)(INTC_BASE + 0x10 + ((n) * sizeof (uint32_t)))))
|
||||
#define INTC_EOIR(n) (*((volatile uint32_t *)(INTC_BASE + 0x18 + ((n) * sizeof (uint32_t)))))
|
||||
#define INTC_PSR(n) (*((volatile uint8_t *)(INTC_BASE + 0x40 + ((n) * sizeof (uint8_t)))))
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @brief Core selection macros for PSR register.
|
||||
*/
|
||||
#define INTC_PSR_CORE0 0x00
|
||||
|
||||
/**
|
||||
* @brief PSR register content helper
|
||||
*/
|
||||
#define INTC_PSR_ENABLE(cores, prio) ((uint32_t)(cores) | (uint32_t)(prio))
|
||||
|
||||
/*===========================================================================*/
|
||||
/* External declarations. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Module inline functions. */
|
||||
/*===========================================================================*/
|
||||
|
||||
#endif /* _INTC_H_ */
|
||||
|
||||
/** @} */
|
||||
|
|
@ -1,83 +0,0 @@
|
|||
/*
|
||||
ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
|
||||
|
||||
Licensed under the Apache License, Version 2.0 (the "License");
|
||||
you may not use this file except in compliance with the License.
|
||||
You may obtain a copy of the License at
|
||||
|
||||
http://www.apache.org/licenses/LICENSE-2.0
|
||||
|
||||
Unless required by applicable law or agreed to in writing, software
|
||||
distributed under the License is distributed on an "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
See the License for the specific language governing permissions and
|
||||
limitations under the License.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file SPC560Pxx/ppcparams.h
|
||||
* @brief PowerPC parameters for the SPC560Pxx.
|
||||
*
|
||||
* @defgroup PPC_SPC560Pxx SPC560Pxx Specific Parameters
|
||||
* @ingroup PPC_SPECIFIC
|
||||
* @details This file contains the PowerPC specific parameters for the
|
||||
* SPC560Pxx platform.
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifndef _PPCPARAMS_H_
|
||||
#define _PPCPARAMS_H_
|
||||
|
||||
/**
|
||||
* @brief Family identification macro.
|
||||
*/
|
||||
#define PPC_SPC560Pxx
|
||||
|
||||
/**
|
||||
* @brief PPC core model.
|
||||
*/
|
||||
#define PPC_VARIANT PPC_VARIANT_e200z0
|
||||
|
||||
/**
|
||||
* @brief Number of cores.
|
||||
*/
|
||||
#define PPC_CORE_NUMBER 1
|
||||
|
||||
/**
|
||||
* @brief Number of writable bits in IVPR register.
|
||||
*/
|
||||
#define PPC_IVPR_BITS 20
|
||||
|
||||
/**
|
||||
* @brief IVORx registers support.
|
||||
*/
|
||||
#define PPC_SUPPORTS_IVORS FALSE
|
||||
|
||||
/**
|
||||
* @brief Book E instruction set support.
|
||||
*/
|
||||
#define PPC_SUPPORTS_BOOKE FALSE
|
||||
|
||||
/**
|
||||
* @brief VLE instruction set support.
|
||||
*/
|
||||
#define PPC_SUPPORTS_VLE TRUE
|
||||
|
||||
/**
|
||||
* @brief Supports VLS Load/Store Multiple Volatile instructions.
|
||||
*/
|
||||
#define PPC_SUPPORTS_VLE_MULTI TRUE
|
||||
|
||||
/**
|
||||
* @brief Supports the decrementer timer.
|
||||
*/
|
||||
#define PPC_SUPPORTS_DECREMENTER FALSE
|
||||
|
||||
/**
|
||||
* @brief Number of interrupt sources.
|
||||
*/
|
||||
#define PPC_NUM_VECTORS 261
|
||||
|
||||
#endif /* _PPCPARAMS_H_ */
|
||||
|
||||
/** @} */
|
||||
|
|
@ -1,119 +0,0 @@
|
|||
/*
|
||||
ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
|
||||
|
||||
Licensed under the Apache License, Version 2.0 (the "License");
|
||||
you may not use this file except in compliance with the License.
|
||||
You may obtain a copy of the License at
|
||||
|
||||
http://www.apache.org/licenses/LICENSE-2.0
|
||||
|
||||
Unless required by applicable law or agreed to in writing, software
|
||||
distributed under the License is distributed on an "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
See the License for the specific language governing permissions and
|
||||
limitations under the License.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file boot.h
|
||||
* @brief Boot parameters for the SPC563Mxx.
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifndef _BOOT_H_
|
||||
#define _BOOT_H_
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Module constants. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @name BUCSR registers definitions
|
||||
* @{
|
||||
*/
|
||||
#define BUCSR_BPEN 0x00000001
|
||||
#define BUCSR_BALLOC_BFI 0x00000200
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @name MSR register definitions
|
||||
* @{
|
||||
*/
|
||||
#define MSR_UCLE 0x04000000
|
||||
#define MSR_SPE 0x02000000
|
||||
#define MSR_WE 0x00040000
|
||||
#define MSR_CE 0x00020000
|
||||
#define MSR_EE 0x00008000
|
||||
#define MSR_PR 0x00004000
|
||||
#define MSR_FP 0x00002000
|
||||
#define MSR_ME 0x00001000
|
||||
#define MSR_FE0 0x00000800
|
||||
#define MSR_DE 0x00000200
|
||||
#define MSR_FE1 0x00000100
|
||||
#define MSR_IS 0x00000020
|
||||
#define MSR_DS 0x00000010
|
||||
#define MSR_RI 0x00000002
|
||||
/** @} */
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Module pre-compile time settings. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*
|
||||
* BUCSR default settings.
|
||||
*/
|
||||
#if !defined(BOOT_BUCSR_DEFAULT) || defined(__DOXYGEN__)
|
||||
#define BOOT_BUCSR_DEFAULT (BUCSR_BPEN | BUCSR_BALLOC_BFI)
|
||||
#endif
|
||||
|
||||
/*
|
||||
* MSR default settings.
|
||||
*/
|
||||
#if !defined(BOOT_MSR_DEFAULT) || defined(__DOXYGEN__)
|
||||
#define BOOT_MSR_DEFAULT (MSR_SPE | MSR_WE | MSR_CE | MSR_ME)
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Boot default settings.
|
||||
*/
|
||||
#if !defined(BOOT_PERFORM_CORE_INIT) || defined(__DOXYGEN__)
|
||||
#define BOOT_PERFORM_CORE_INIT 1
|
||||
#endif
|
||||
|
||||
/*
|
||||
* VLE mode default settings.
|
||||
*/
|
||||
#if !defined(BOOT_USE_VLE) || defined(__DOXYGEN__)
|
||||
#define BOOT_USE_VLE 1
|
||||
#endif
|
||||
|
||||
/*
|
||||
* RAM relocation flag.
|
||||
*/
|
||||
#if !defined(BOOT_RELOCATE_IN_RAM) || defined(__DOXYGEN__)
|
||||
#define BOOT_RELOCATE_IN_RAM 0
|
||||
#endif
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Derived constants and error checks. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Module data structures and types. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Module macros. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* External declarations. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Module inline functions. */
|
||||
/*===========================================================================*/
|
||||
|
||||
#endif /* _BOOT_H_ */
|
||||
|
||||
/** @} */
|
||||
|
|
@ -1,188 +0,0 @@
|
|||
/*
|
||||
ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
|
||||
|
||||
Licensed under the Apache License, Version 2.0 (the "License");
|
||||
you may not use this file except in compliance with the License.
|
||||
You may obtain a copy of the License at
|
||||
|
||||
http://www.apache.org/licenses/LICENSE-2.0
|
||||
|
||||
Unless required by applicable law or agreed to in writing, software
|
||||
distributed under the License is distributed on an "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
See the License for the specific language governing permissions and
|
||||
limitations under the License.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file SPC563Mxx/boot.s
|
||||
* @brief SPC563Mxx boot-related code.
|
||||
*
|
||||
* @addtogroup PPC_BOOT
|
||||
* @{
|
||||
*/
|
||||
|
||||
#include "boot.h"
|
||||
|
||||
#if !defined(__DOXYGEN__)
|
||||
|
||||
/* BAM record.*/
|
||||
.section .boot, "ax"
|
||||
|
||||
#if BOOT_USE_VLE
|
||||
.long 0x015A0000
|
||||
#else
|
||||
.long 0x005A0000
|
||||
#endif
|
||||
.long _reset_address
|
||||
|
||||
.align 2
|
||||
.globl _reset_address
|
||||
.type _reset_address, @function
|
||||
_reset_address:
|
||||
#if BOOT_PERFORM_CORE_INIT
|
||||
bl _coreinit
|
||||
#endif
|
||||
bl _ivinit
|
||||
|
||||
#if BOOT_RELOCATE_IN_RAM
|
||||
/*
|
||||
* Image relocation in RAM.
|
||||
*/
|
||||
lis %r4, __ram_reloc_start__@h
|
||||
ori %r4, %r4, __ram_reloc_start__@l
|
||||
lis %r5, __ram_reloc_dest__@h
|
||||
ori %r5, %r5, __ram_reloc_dest__@l
|
||||
lis %r6, __ram_reloc_end__@h
|
||||
ori %r6, %r6, __ram_reloc_end__@l
|
||||
.relloop:
|
||||
cmpl cr0, %r4, %r6
|
||||
bge cr0, .relend
|
||||
lwz %r7, 0(%r4)
|
||||
addi %r4, %r4, 4
|
||||
stw %r7, 0(%r5)
|
||||
addi %r5, %r5, 4
|
||||
b .relloop
|
||||
.relend:
|
||||
lis %r3, _boot_address@h
|
||||
ori %r3, %r3, _boot_address@l
|
||||
mtctr %r3
|
||||
bctrl
|
||||
#else
|
||||
b _boot_address
|
||||
#endif
|
||||
|
||||
#if BOOT_PERFORM_CORE_INIT
|
||||
.align 2
|
||||
_coreinit:
|
||||
/*
|
||||
* RAM clearing, this device requires a write to all RAM location in
|
||||
* order to initialize the ECC detection hardware, this is going to
|
||||
* slow down the startup but there is no way around.
|
||||
*/
|
||||
xor %r0, %r0, %r0
|
||||
xor %r1, %r1, %r1
|
||||
xor %r2, %r2, %r2
|
||||
xor %r3, %r3, %r3
|
||||
xor %r4, %r4, %r4
|
||||
xor %r5, %r5, %r5
|
||||
xor %r6, %r6, %r6
|
||||
xor %r7, %r7, %r7
|
||||
xor %r8, %r8, %r8
|
||||
xor %r9, %r9, %r9
|
||||
xor %r10, %r10, %r10
|
||||
xor %r11, %r11, %r11
|
||||
xor %r12, %r12, %r12
|
||||
xor %r13, %r13, %r13
|
||||
xor %r14, %r14, %r14
|
||||
xor %r15, %r15, %r15
|
||||
xor %r16, %r16, %r16
|
||||
xor %r17, %r17, %r17
|
||||
xor %r18, %r18, %r18
|
||||
xor %r19, %r19, %r19
|
||||
xor %r20, %r20, %r20
|
||||
xor %r21, %r21, %r21
|
||||
xor %r22, %r22, %r22
|
||||
xor %r23, %r23, %r23
|
||||
xor %r24, %r24, %r24
|
||||
xor %r25, %r25, %r25
|
||||
xor %r26, %r26, %r26
|
||||
xor %r27, %r27, %r27
|
||||
xor %r28, %r28, %r28
|
||||
xor %r29, %r29, %r29
|
||||
xor %r30, %r30, %r30
|
||||
xor %r31, %r31, %r31
|
||||
lis %r4, __ram_start__@h
|
||||
ori %r4, %r4, __ram_start__@l
|
||||
lis %r5, __ram_end__@h
|
||||
ori %r5, %r5, __ram_end__@l
|
||||
.cleareccloop:
|
||||
cmpl %cr0, %r4, %r5
|
||||
bge %cr0, .cleareccend
|
||||
stmw %r16, 0(%r4)
|
||||
addi %r4, %r4, 64
|
||||
b .cleareccloop
|
||||
.cleareccend:
|
||||
|
||||
/*
|
||||
* Branch prediction enabled.
|
||||
*/
|
||||
li %r3, BOOT_BUCSR_DEFAULT
|
||||
mtspr 1013, %r3 /* BUCSR */
|
||||
|
||||
blr
|
||||
#endif /* BOOT_PERFORM_CORE_INIT */
|
||||
|
||||
/*
|
||||
* Exception vectors initialization.
|
||||
*/
|
||||
_ivinit:
|
||||
/* MSR initialization.*/
|
||||
lis %r3, BOOT_MSR_DEFAULT@h
|
||||
ori %r3, %r3, BOOT_MSR_DEFAULT@l
|
||||
mtMSR %r3
|
||||
|
||||
/* IVPR initialization.*/
|
||||
lis %r3, __ivpr_base__@h
|
||||
ori %r3, %r3, __ivpr_base__@l
|
||||
mtIVPR %r3
|
||||
|
||||
/* IVORs initialization.*/
|
||||
lis %r3, _unhandled_exception@h
|
||||
ori %r3, %r3, _unhandled_exception@l
|
||||
|
||||
mtspr 400, %r3 /* IVOR0-15 */
|
||||
mtspr 401, %r3
|
||||
mtspr 402, %r3
|
||||
mtspr 403, %r3
|
||||
mtspr 404, %r3
|
||||
mtspr 405, %r3
|
||||
mtspr 406, %r3
|
||||
mtspr 407, %r3
|
||||
mtspr 408, %r3
|
||||
mtspr 409, %r3
|
||||
mtspr 410, %r3
|
||||
mtspr 411, %r3
|
||||
mtspr 412, %r3
|
||||
mtspr 413, %r3
|
||||
mtspr 414, %r3
|
||||
mtspr 415, %r3
|
||||
mtspr 528, %r3 /* IVOR32-34 */
|
||||
mtspr 529, %r3
|
||||
mtspr 530, %r3
|
||||
|
||||
blr
|
||||
|
||||
.section .handlers, "ax"
|
||||
|
||||
/*
|
||||
* Unhandled exceptions handler.
|
||||
*/
|
||||
.weak _unhandled_exception
|
||||
.type _unhandled_exception, @function
|
||||
_unhandled_exception:
|
||||
b _unhandled_exception
|
||||
|
||||
#endif /* !defined(__DOXYGEN__) */
|
||||
|
||||
/** @} */
|
||||
|
|
@ -1,93 +0,0 @@
|
|||
/*
|
||||
ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
|
||||
|
||||
Licensed under the Apache License, Version 2.0 (the "License");
|
||||
you may not use this file except in compliance with the License.
|
||||
You may obtain a copy of the License at
|
||||
|
||||
http://www.apache.org/licenses/LICENSE-2.0
|
||||
|
||||
Unless required by applicable law or agreed to in writing, software
|
||||
distributed under the License is distributed on an "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
See the License for the specific language governing permissions and
|
||||
limitations under the License.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file SPC563Mxx/intc.h
|
||||
* @brief SPC563Mxx INTC module header.
|
||||
*
|
||||
* @addtogroup INTC
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifndef _INTC_H_
|
||||
#define _INTC_H_
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Module constants. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @name INTC addresses
|
||||
* @{
|
||||
*/
|
||||
#define INTC_BASE 0xFFF48000
|
||||
#define INTC_IACKR_ADDR (INTC_BASE + 0x10)
|
||||
#define INTC_EOIR_ADDR (INTC_BASE + 0x18)
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @brief INTC priority levels.
|
||||
*/
|
||||
#define INTC_PRIORITY_LEVELS 16U
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Module pre-compile time settings. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Derived constants and error checks. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Module data structures and types. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Module macros. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @name INTC-related macros
|
||||
* @{
|
||||
*/
|
||||
#define INTC_BCR (*((volatile uint32_t *)(INTC_BASE + 0)))
|
||||
#define INTC_CPR(n) (*((volatile uint32_t *)(INTC_BASE + 8 + ((n) * sizeof (uint32_t)))))
|
||||
#define INTC_IACKR(n) (*((volatile uint32_t *)(INTC_BASE + 0x10 + ((n) * sizeof (uint32_t)))))
|
||||
#define INTC_EOIR(n) (*((volatile uint32_t *)(INTC_BASE + 0x18 + ((n) * sizeof (uint32_t)))))
|
||||
#define INTC_PSR(n) (*((volatile uint8_t *)(INTC_BASE + 0x40 + ((n) * sizeof (uint8_t)))))
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @brief Core selection macros for PSR register.
|
||||
*/
|
||||
#define INTC_PSR_CORE0 0x00
|
||||
|
||||
/**
|
||||
* @brief PSR register content helper
|
||||
*/
|
||||
#define INTC_PSR_ENABLE(cores, prio) ((uint32_t)(cores) | (uint32_t)(prio))
|
||||
|
||||
/*===========================================================================*/
|
||||
/* External declarations. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Module inline functions. */
|
||||
/*===========================================================================*/
|
||||
|
||||
#endif /* _INTC_H_ */
|
||||
|
||||
/** @} */
|
||||
|
|
@ -1,83 +0,0 @@
|
|||
/*
|
||||
ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
|
||||
|
||||
Licensed under the Apache License, Version 2.0 (the "License");
|
||||
you may not use this file except in compliance with the License.
|
||||
You may obtain a copy of the License at
|
||||
|
||||
http://www.apache.org/licenses/LICENSE-2.0
|
||||
|
||||
Unless required by applicable law or agreed to in writing, software
|
||||
distributed under the License is distributed on an "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
See the License for the specific language governing permissions and
|
||||
limitations under the License.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file SPC563Mxx/ppcparams.h
|
||||
* @brief PowerPC parameters for the SPC563Mxx.
|
||||
*
|
||||
* @defgroup PPC_SPC563Mxx SPC563Mxx Specific Parameters
|
||||
* @ingroup PPC_SPECIFIC
|
||||
* @details This file contains the PowerPC specific parameters for the
|
||||
* SPC563Mxx platform.
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifndef _PPCPARAMS_H_
|
||||
#define _PPCPARAMS_H_
|
||||
|
||||
/**
|
||||
* @brief Family identification macro.
|
||||
*/
|
||||
#define PPC_SPC563Mxx
|
||||
|
||||
/**
|
||||
* @brief PPC core model.
|
||||
*/
|
||||
#define PPC_VARIANT PPC_VARIANT_e200z3
|
||||
|
||||
/**
|
||||
* @brief Number of cores.
|
||||
*/
|
||||
#define PPC_CORE_NUMBER 1
|
||||
|
||||
/**
|
||||
* @brief Number of writable bits in IVPR register.
|
||||
*/
|
||||
#define PPC_IVPR_BITS 16
|
||||
|
||||
/**
|
||||
* @brief IVORx registers support.
|
||||
*/
|
||||
#define PPC_SUPPORTS_IVORS TRUE
|
||||
|
||||
/**
|
||||
* @brief Book E instruction set support.
|
||||
*/
|
||||
#define PPC_SUPPORTS_BOOKE TRUE
|
||||
|
||||
/**
|
||||
* @brief VLE instruction set support.
|
||||
*/
|
||||
#define PPC_SUPPORTS_VLE TRUE
|
||||
|
||||
/**
|
||||
* @brief Supports VLS Load/Store Multiple Volatile instructions.
|
||||
*/
|
||||
#define PPC_SUPPORTS_VLE_MULTI TRUE
|
||||
|
||||
/**
|
||||
* @brief Supports the decrementer timer.
|
||||
*/
|
||||
#define PPC_SUPPORTS_DECREMENTER TRUE
|
||||
|
||||
/**
|
||||
* @brief Number of interrupt sources.
|
||||
*/
|
||||
#define PPC_NUM_VECTORS 360
|
||||
|
||||
#endif /* _PPCPARAMS_H_ */
|
||||
|
||||
/** @} */
|
||||
|
|
@ -1,242 +0,0 @@
|
|||
/*
|
||||
ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
|
||||
|
||||
Licensed under the Apache License, Version 2.0 (the "License");
|
||||
you may not use this file except in compliance with the License.
|
||||
You may obtain a copy of the License at
|
||||
|
||||
http://www.apache.org/licenses/LICENSE-2.0
|
||||
|
||||
Unless required by applicable law or agreed to in writing, software
|
||||
distributed under the License is distributed on an "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
See the License for the specific language governing permissions and
|
||||
limitations under the License.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file boot.h
|
||||
* @brief Boot parameters for the SPC564Axx.
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifndef _BOOT_H_
|
||||
#define _BOOT_H_
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Module constants. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @name MASx registers definitions
|
||||
* @{
|
||||
*/
|
||||
#define MAS0_TBLMAS_TBL 0x10000000
|
||||
#define MAS0_ESEL_MASK 0x000F0000
|
||||
#define MAS0_ESEL(n) ((n) << 16)
|
||||
|
||||
#define MAS1_VALID 0x80000000
|
||||
#define MAS1_IPROT 0x40000000
|
||||
#define MAS1_TID_MASK 0x00FF0000
|
||||
#define MAS1_TS 0x00001000
|
||||
#define MAS1_TSISE_MASK 0x00000F80
|
||||
#define MAS1_TSISE_1K 0x00000000
|
||||
#define MAS1_TSISE_2K 0x00000080
|
||||
#define MAS1_TSISE_4K 0x00000100
|
||||
#define MAS1_TSISE_8K 0x00000180
|
||||
#define MAS1_TSISE_16K 0x00000200
|
||||
#define MAS1_TSISE_32K 0x00000280
|
||||
#define MAS1_TSISE_64K 0x00000300
|
||||
#define MAS1_TSISE_128K 0x00000380
|
||||
#define MAS1_TSISE_256K 0x00000400
|
||||
#define MAS1_TSISE_512K 0x00000480
|
||||
#define MAS1_TSISE_1M 0x00000500
|
||||
#define MAS1_TSISE_2M 0x00000580
|
||||
#define MAS1_TSISE_4M 0x00000600
|
||||
#define MAS1_TSISE_8M 0x00000680
|
||||
#define MAS1_TSISE_16M 0x00000700
|
||||
#define MAS1_TSISE_32M 0x00000780
|
||||
#define MAS1_TSISE_64M 0x00000800
|
||||
#define MAS1_TSISE_128M 0x00000880
|
||||
#define MAS1_TSISE_256M 0x00000900
|
||||
#define MAS1_TSISE_512M 0x00000980
|
||||
#define MAS1_TSISE_1G 0x00000A00
|
||||
#define MAS1_TSISE_2G 0x00000A80
|
||||
#define MAS1_TSISE_4G 0x00000B00
|
||||
|
||||
#define MAS2_EPN_MASK 0xFFFFFC00
|
||||
#define MAS2_EPN(n) ((n) & MAS2_EPN_MASK)
|
||||
#define MAS2_EBOOK 0x00000000
|
||||
#define MAS2_VLE 0x00000020
|
||||
#define MAS2_W 0x00000010
|
||||
#define MAS2_I 0x00000008
|
||||
#define MAS2_M 0x00000004
|
||||
#define MAS2_G 0x00000002
|
||||
#define MAS2_E 0x00000001
|
||||
|
||||
#define MAS3_RPN_MASK 0xFFFFFC00
|
||||
#define MAS3_RPN(n) ((n) & MAS3_RPN_MASK)
|
||||
#define MAS3_U0 0x00000200
|
||||
#define MAS3_U1 0x00000100
|
||||
#define MAS3_U2 0x00000080
|
||||
#define MAS3_U3 0x00000040
|
||||
#define MAS3_UX 0x00000020
|
||||
#define MAS3_SX 0x00000010
|
||||
#define MAS3_UW 0x00000008
|
||||
#define MAS3_SW 0x00000004
|
||||
#define MAS3_UR 0x00000002
|
||||
#define MAS3_SR 0x00000001
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @name BUCSR registers definitions
|
||||
* @{
|
||||
*/
|
||||
#define BUCSR_BPEN 0x00000001
|
||||
#define BUCSR_BPRED_MASK 0x00000006
|
||||
#define BUCSR_BPRED_0 0x00000000
|
||||
#define BUCSR_BPRED_1 0x00000002
|
||||
#define BUCSR_BPRED_2 0x00000004
|
||||
#define BUCSR_BPRED_3 0x00000006
|
||||
#define BUCSR_BALLOC_MASK 0x00000030
|
||||
#define BUCSR_BALLOC_0 0x00000000
|
||||
#define BUCSR_BALLOC_1 0x00000010
|
||||
#define BUCSR_BALLOC_2 0x00000020
|
||||
#define BUCSR_BALLOC_3 0x00000030
|
||||
#define BUCSR_BALLOC_BFI 0x00000200
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @name LICSR1 registers definitions
|
||||
* @{
|
||||
*/
|
||||
#define LICSR1_ICE 0x00000001
|
||||
#define LICSR1_ICINV 0x00000002
|
||||
#define LICSR1_ICORG 0x00000010
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @name MSR register definitions
|
||||
* @{
|
||||
*/
|
||||
#define MSR_UCLE 0x04000000
|
||||
#define MSR_SPE 0x02000000
|
||||
#define MSR_WE 0x00040000
|
||||
#define MSR_CE 0x00020000
|
||||
#define MSR_EE 0x00008000
|
||||
#define MSR_PR 0x00004000
|
||||
#define MSR_FP 0x00002000
|
||||
#define MSR_ME 0x00001000
|
||||
#define MSR_FE0 0x00000800
|
||||
#define MSR_DE 0x00000200
|
||||
#define MSR_FE1 0x00000100
|
||||
#define MSR_IS 0x00000020
|
||||
#define MSR_DS 0x00000010
|
||||
#define MSR_RI 0x00000002
|
||||
/** @} */
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Module pre-compile time settings. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*
|
||||
* TLB default settings.
|
||||
*/
|
||||
#define TLB0_MAS0 (MAS0_TBLMAS_TBL | MAS0_ESEL(0))
|
||||
#define TLB0_MAS1 (MAS1_VALID | MAS1_IPROT | MAS1_TSISE_256K)
|
||||
#define TLB0_MAS2 (MAS2_EPN(0x40000000) | MAS2_VLE)
|
||||
#define TLB0_MAS3 (MAS3_RPN(0x40000000) | \
|
||||
MAS3_UX | MAS3_SX | MAS3_UW | MAS3_SW | \
|
||||
MAS3_UR | MAS3_SR)
|
||||
|
||||
#define TLB1_MAS0 (MAS0_TBLMAS_TBL | MAS0_ESEL(1))
|
||||
#define TLB1_MAS1 (MAS1_VALID | MAS1_IPROT | MAS1_TSISE_4M)
|
||||
#define TLB1_MAS2 (MAS2_EPN(0x00000000) | MAS2_VLE)
|
||||
#define TLB1_MAS3 (MAS3_RPN(0x00000000) | \
|
||||
MAS3_UX | MAS3_SX | MAS3_UW | MAS3_SW | \
|
||||
MAS3_UR | MAS3_SR)
|
||||
|
||||
#define TLB2_MAS0 (MAS0_TBLMAS_TBL | MAS0_ESEL(2))
|
||||
#define TLB2_MAS1 (MAS1_VALID | MAS1_IPROT | MAS1_TSISE_1M)
|
||||
#define TLB2_MAS2 (MAS2_EPN(0xC3F00000) | MAS2_I)
|
||||
#define TLB2_MAS3 (MAS3_RPN(0xC3F00000) | \
|
||||
MAS3_UW | MAS3_SW | MAS3_UR | MAS3_SR)
|
||||
|
||||
#define TLB3_MAS0 (MAS0_TBLMAS_TBL | MAS0_ESEL(3))
|
||||
#define TLB3_MAS1 (MAS1_VALID | MAS1_IPROT | MAS1_TSISE_1M)
|
||||
#define TLB3_MAS2 (MAS2_EPN(0xFFE00000) | MAS2_I)
|
||||
#define TLB3_MAS3 (MAS3_RPN(0xFFE00000) | \
|
||||
MAS3_UW | MAS3_SW | MAS3_UR | MAS3_SR)
|
||||
|
||||
#define TLB4_MAS0 (MAS0_TBLMAS_TBL | MAS0_ESEL(4))
|
||||
#define TLB4_MAS1 (MAS1_VALID | MAS1_IPROT | MAS1_TSISE_1M)
|
||||
#define TLB4_MAS2 (MAS2_EPN(0xFFF00000) | MAS2_I)
|
||||
#define TLB4_MAS3 (MAS3_RPN(0xFFF00000) | \
|
||||
MAS3_UW | MAS3_SW | MAS3_UR | MAS3_SR)
|
||||
|
||||
/*
|
||||
* BUCSR default settings.
|
||||
*/
|
||||
#if !defined(BOOT_BUCSR_DEFAULT) || defined(__DOXYGEN__)
|
||||
#define BOOT_BUCSR_DEFAULT (BUCSR_BPEN | BUCSR_BPRED_0 | \
|
||||
BUCSR_BALLOC_0 | BUCSR_BALLOC_BFI)
|
||||
#endif
|
||||
|
||||
/*
|
||||
* LICSR1 default settings.
|
||||
*/
|
||||
#if !defined(BOOT_LICSR1_DEFAULT) || defined(__DOXYGEN__)
|
||||
#define BOOT_LICSR1_DEFAULT (LICSR1_ICE | LICSR1_ICORG)
|
||||
#endif
|
||||
|
||||
/*
|
||||
* MSR default settings.
|
||||
*/
|
||||
#if !defined(BOOT_MSR_DEFAULT) || defined(__DOXYGEN__)
|
||||
#define BOOT_MSR_DEFAULT (MSR_SPE | MSR_WE | MSR_CE | MSR_ME)
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Boot default settings.
|
||||
*/
|
||||
#if !defined(BOOT_PERFORM_CORE_INIT) || defined(__DOXYGEN__)
|
||||
#define BOOT_PERFORM_CORE_INIT 1
|
||||
#endif
|
||||
|
||||
/*
|
||||
* VLE mode default settings.
|
||||
*/
|
||||
#if !defined(BOOT_USE_VLE) || defined(__DOXYGEN__)
|
||||
#define BOOT_USE_VLE 1
|
||||
#endif
|
||||
|
||||
/*
|
||||
* RAM relocation flag.
|
||||
*/
|
||||
#if !defined(BOOT_RELOCATE_IN_RAM) || defined(__DOXYGEN__)
|
||||
#define BOOT_RELOCATE_IN_RAM 0
|
||||
#endif
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Derived constants and error checks. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Module data structures and types. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Module macros. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* External declarations. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Module inline functions. */
|
||||
/*===========================================================================*/
|
||||
|
||||
#endif /* _BOOT_H_ */
|
||||
|
||||
/** @} */
|
||||
|
|
@ -1,353 +0,0 @@
|
|||
/*
|
||||
ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
|
||||
|
||||
Licensed under the Apache License, Version 2.0 (the "License");
|
||||
you may not use this file except in compliance with the License.
|
||||
You may obtain a copy of the License at
|
||||
|
||||
http://www.apache.org/licenses/LICENSE-2.0
|
||||
|
||||
Unless required by applicable law or agreed to in writing, software
|
||||
distributed under the License is distributed on an "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
See the License for the specific language governing permissions and
|
||||
limitations under the License.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file SPC564Axx/boot.s
|
||||
* @brief SPC564Axx boot-related code.
|
||||
*
|
||||
* @addtogroup PPC_BOOT
|
||||
* @{
|
||||
*/
|
||||
|
||||
#include "boot.h"
|
||||
|
||||
#if !defined(__DOXYGEN__)
|
||||
|
||||
/* BAM record.*/
|
||||
.section .boot, "ax"
|
||||
|
||||
#if BOOT_USE_VLE
|
||||
.long 0x015A0000
|
||||
#else
|
||||
.long 0x005A0000
|
||||
#endif
|
||||
.long _reset_address
|
||||
|
||||
.align 2
|
||||
.globl _reset_address
|
||||
.type _reset_address, @function
|
||||
_reset_address:
|
||||
#if BOOT_PERFORM_CORE_INIT
|
||||
bl _coreinit
|
||||
#endif
|
||||
bl _ivinit
|
||||
|
||||
#if BOOT_RELOCATE_IN_RAM
|
||||
/*
|
||||
* Image relocation in RAM.
|
||||
*/
|
||||
lis %r4, __ram_reloc_start__@h
|
||||
ori %r4, %r4, __ram_reloc_start__@l
|
||||
lis %r5, __ram_reloc_dest__@h
|
||||
ori %r5, %r5, __ram_reloc_dest__@l
|
||||
lis %r6, __ram_reloc_end__@h
|
||||
ori %r6, %r6, __ram_reloc_end__@l
|
||||
.relloop:
|
||||
cmpl cr0, %r4, %r6
|
||||
bge cr0, .relend
|
||||
lwz %r7, 0(%r4)
|
||||
addi %r4, %r4, 4
|
||||
stw %r7, 0(%r5)
|
||||
addi %r5, %r5, 4
|
||||
b .relloop
|
||||
.relend:
|
||||
lis %r3, _boot_address@h
|
||||
ori %r3, %r3, _boot_address@l
|
||||
mtctr %r3
|
||||
bctrl
|
||||
#else
|
||||
b _boot_address
|
||||
#endif
|
||||
|
||||
#if BOOT_PERFORM_CORE_INIT
|
||||
.align 2
|
||||
_ramcode:
|
||||
tlbwe
|
||||
isync
|
||||
blr
|
||||
|
||||
.align 2
|
||||
_coreinit:
|
||||
/*
|
||||
* Invalidating all TLBs except TLB1.
|
||||
*/
|
||||
lis %r3, 0
|
||||
mtspr 625, %r3 /* MAS1 */
|
||||
mtspr 626, %r3 /* MAS2 */
|
||||
mtspr 627, %r3 /* MAS3 */
|
||||
lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(0))@h
|
||||
mtspr 624, %r3 /* MAS0 */
|
||||
tlbwe
|
||||
lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(2))@h
|
||||
mtspr 624, %r3 /* MAS0 */
|
||||
tlbwe
|
||||
lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(3))@h
|
||||
mtspr 624, %r3 /* MAS0 */
|
||||
tlbwe
|
||||
lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(4))@h
|
||||
mtspr 624, %r3 /* MAS0 */
|
||||
tlbwe
|
||||
lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(5))@h
|
||||
mtspr 624, %r3 /* MAS0 */
|
||||
tlbwe
|
||||
lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(6))@h
|
||||
mtspr 624, %r3 /* MAS0 */
|
||||
tlbwe
|
||||
lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(7))@h
|
||||
mtspr 624, %r3 /* MAS0 */
|
||||
tlbwe
|
||||
lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(8))@h
|
||||
mtspr 624, %r3 /* MAS0 */
|
||||
tlbwe
|
||||
lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(9))@h
|
||||
mtspr 624, %r3 /* MAS0 */
|
||||
tlbwe
|
||||
lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(10))@h
|
||||
mtspr 624, %r3 /* MAS0 */
|
||||
tlbwe
|
||||
lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(11))@h
|
||||
mtspr 624, %r3 /* MAS0 */
|
||||
tlbwe
|
||||
lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(12))@h
|
||||
mtspr 624, %r3 /* MAS0 */
|
||||
tlbwe
|
||||
lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(13))@h
|
||||
mtspr 624, %r3 /* MAS0 */
|
||||
tlbwe
|
||||
lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(14))@h
|
||||
mtspr 624, %r3 /* MAS0 */
|
||||
tlbwe
|
||||
lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(15))@h
|
||||
mtspr 624, %r3 /* MAS0 */
|
||||
tlbwe
|
||||
|
||||
/*
|
||||
* TLB0 allocated to internal RAM.
|
||||
*/
|
||||
lis %r3, TLB0_MAS0@h
|
||||
mtspr 624, %r3 /* MAS0 */
|
||||
lis %r3, TLB0_MAS1@h
|
||||
ori %r3, %r3, TLB0_MAS1@l
|
||||
mtspr 625, %r3 /* MAS1 */
|
||||
lis %r3, TLB0_MAS2@h
|
||||
ori %r3, %r3, TLB0_MAS2@l
|
||||
mtspr 626, %r3 /* MAS2 */
|
||||
lis %r3, TLB0_MAS3@h
|
||||
ori %r3, %r3, TLB0_MAS3@l
|
||||
mtspr 627, %r3 /* MAS3 */
|
||||
tlbwe
|
||||
|
||||
/*
|
||||
* TLB2 allocated to internal Peripherals Bridge A.
|
||||
*/
|
||||
lis %r3, TLB2_MAS0@h
|
||||
mtspr 624, %r3 /* MAS0 */
|
||||
lis %r3, TLB2_MAS1@h
|
||||
ori %r3, %r3, TLB2_MAS1@l
|
||||
mtspr 625, %r3 /* MAS1 */
|
||||
lis %r3, TLB2_MAS2@h
|
||||
ori %r3, %r3, TLB2_MAS2@l
|
||||
mtspr 626, %r3 /* MAS2 */
|
||||
lis %r3, TLB2_MAS3@h
|
||||
ori %r3, %r3, TLB2_MAS3@l
|
||||
mtspr 627, %r3 /* MAS3 */
|
||||
tlbwe
|
||||
|
||||
/*
|
||||
* TLB3 allocated to internal Peripherals Bridge B.
|
||||
*/
|
||||
lis %r3, TLB3_MAS0@h
|
||||
mtspr 624, %r3 /* MAS0 */
|
||||
lis %r3, TLB3_MAS1@h
|
||||
ori %r3, %r3, TLB3_MAS1@l
|
||||
mtspr 625, %r3 /* MAS1 */
|
||||
lis %r3, TLB3_MAS2@h
|
||||
ori %r3, %r3, TLB3_MAS2@l
|
||||
mtspr 626, %r3 /* MAS2 */
|
||||
lis %r3, TLB3_MAS3@h
|
||||
ori %r3, %r3, TLB3_MAS3@l
|
||||
mtspr 627, %r3 /* MAS3 */
|
||||
tlbwe
|
||||
|
||||
/*
|
||||
* TLB4 allocated to on-platform peripherals.
|
||||
*/
|
||||
lis %r3, TLB4_MAS0@h
|
||||
mtspr 624, %r3 /* MAS0 */
|
||||
lis %r3, TLB4_MAS1@h
|
||||
ori %r3, %r3, TLB4_MAS1@l
|
||||
mtspr 625, %r3 /* MAS1 */
|
||||
lis %r3, TLB4_MAS2@h
|
||||
ori %r3, %r3, TLB4_MAS2@l
|
||||
mtspr 626, %r3 /* MAS2 */
|
||||
lis %r3, TLB4_MAS3@h
|
||||
ori %r3, %r3, TLB4_MAS3@l
|
||||
mtspr 627, %r3 /* MAS3 */
|
||||
tlbwe
|
||||
|
||||
/*
|
||||
* RAM clearing, this device requires a write to all RAM location in
|
||||
* order to initialize the ECC detection hardware, this is going to
|
||||
* slow down the startup but there is no way around.
|
||||
*/
|
||||
xor %r0, %r0, %r0
|
||||
xor %r1, %r1, %r1
|
||||
xor %r2, %r2, %r2
|
||||
xor %r3, %r3, %r3
|
||||
xor %r4, %r4, %r4
|
||||
xor %r5, %r5, %r5
|
||||
xor %r6, %r6, %r6
|
||||
xor %r7, %r7, %r7
|
||||
xor %r8, %r8, %r8
|
||||
xor %r9, %r9, %r9
|
||||
xor %r10, %r10, %r10
|
||||
xor %r11, %r11, %r11
|
||||
xor %r12, %r12, %r12
|
||||
xor %r13, %r13, %r13
|
||||
xor %r14, %r14, %r14
|
||||
xor %r15, %r15, %r15
|
||||
xor %r16, %r16, %r16
|
||||
xor %r17, %r17, %r17
|
||||
xor %r18, %r18, %r18
|
||||
xor %r19, %r19, %r19
|
||||
xor %r20, %r20, %r20
|
||||
xor %r21, %r21, %r21
|
||||
xor %r22, %r22, %r22
|
||||
xor %r23, %r23, %r23
|
||||
xor %r24, %r24, %r24
|
||||
xor %r25, %r25, %r25
|
||||
xor %r26, %r26, %r26
|
||||
xor %r27, %r27, %r27
|
||||
xor %r28, %r28, %r28
|
||||
xor %r29, %r29, %r29
|
||||
xor %r30, %r30, %r30
|
||||
xor %r31, %r31, %r31
|
||||
lis %r4, __ram_start__@h
|
||||
ori %r4, %r4, __ram_start__@l
|
||||
lis %r5, __ram_end__@h
|
||||
ori %r5, %r5, __ram_end__@l
|
||||
.cleareccloop:
|
||||
cmpl %cr0, %r4, %r5
|
||||
bge %cr0, .cleareccend
|
||||
stmw %r16, 0(%r4)
|
||||
addi %r4, %r4, 64
|
||||
b .cleareccloop
|
||||
.cleareccend:
|
||||
|
||||
/*
|
||||
* *Finally* the TLB1 is re-allocated to flash, note, the final phase
|
||||
* is executed from RAM.
|
||||
*/
|
||||
lis %r3, TLB1_MAS0@h
|
||||
mtspr 624, %r3 /* MAS0 */
|
||||
lis %r3, TLB1_MAS1@h
|
||||
ori %r3, %r3, TLB1_MAS1@l
|
||||
mtspr 625, %r3 /* MAS1 */
|
||||
lis %r3, TLB1_MAS2@h
|
||||
ori %r3, %r3, TLB1_MAS2@l
|
||||
mtspr 626, %r3 /* MAS2 */
|
||||
lis %r3, TLB1_MAS3@h
|
||||
ori %r3, %r3, TLB1_MAS3@l
|
||||
mtspr 627, %r3 /* MAS3 */
|
||||
mflr %r4
|
||||
lis %r6, _ramcode@h
|
||||
ori %r6, %r6, _ramcode@l
|
||||
lis %r7, 0x40010000@h
|
||||
mtctr %r7
|
||||
lwz %r3, 0(%r6)
|
||||
stw %r3, 0(%r7)
|
||||
lwz %r3, 4(%r6)
|
||||
stw %r3, 4(%r7)
|
||||
lwz %r3, 8(%r6)
|
||||
stw %r3, 8(%r7)
|
||||
bctrl
|
||||
mtlr %r4
|
||||
|
||||
/*
|
||||
* Branch prediction enabled.
|
||||
*/
|
||||
li %r3, BOOT_BUCSR_DEFAULT
|
||||
mtspr 1013, %r3 /* BUCSR */
|
||||
|
||||
/*
|
||||
* Cache invalidated and then enabled.
|
||||
*/
|
||||
li %r3, LICSR1_ICINV
|
||||
mtspr 1011, %r3 /* LICSR1 */
|
||||
.inv: mfspr %r3, 1011 /* LICSR1 */
|
||||
andi. %r3, %r3, LICSR1_ICINV
|
||||
bne .inv
|
||||
lis %r3, BOOT_LICSR1_DEFAULT@h
|
||||
ori %r3, %r3, BOOT_LICSR1_DEFAULT@l
|
||||
mtspr 1011, %r3 /* LICSR1 */
|
||||
|
||||
blr
|
||||
#endif /* BOOT_PERFORM_CORE_INIT */
|
||||
|
||||
/*
|
||||
* Exception vectors initialization.
|
||||
*/
|
||||
.align 2
|
||||
_ivinit:
|
||||
/* MSR initialization.*/
|
||||
lis %r3, BOOT_MSR_DEFAULT@h
|
||||
ori %r3, %r3, BOOT_MSR_DEFAULT@l
|
||||
mtMSR %r3
|
||||
|
||||
/* IVPR initialization.*/
|
||||
lis %r3, __ivpr_base__@h
|
||||
ori %r3, %r3, __ivpr_base__@l
|
||||
mtIVPR %r3
|
||||
|
||||
/* IVORs initialization.*/
|
||||
lis %r3, _unhandled_exception@h
|
||||
ori %r3, %r3, _unhandled_exception@l
|
||||
|
||||
mtspr 400, %r3 /* IVOR0-15 */
|
||||
mtspr 401, %r3
|
||||
mtspr 402, %r3
|
||||
mtspr 403, %r3
|
||||
mtspr 404, %r3
|
||||
mtspr 405, %r3
|
||||
mtspr 406, %r3
|
||||
mtspr 407, %r3
|
||||
mtspr 408, %r3
|
||||
mtspr 409, %r3
|
||||
mtspr 410, %r3
|
||||
mtspr 411, %r3
|
||||
mtspr 412, %r3
|
||||
mtspr 413, %r3
|
||||
mtspr 414, %r3
|
||||
mtspr 415, %r3
|
||||
mtspr 528, %r3 /* IVOR32-34 */
|
||||
mtspr 529, %r3
|
||||
mtspr 530, %r3
|
||||
|
||||
blr
|
||||
|
||||
.section .handlers, "ax"
|
||||
|
||||
/*
|
||||
* Unhandled exceptions handler.
|
||||
*/
|
||||
.weak _unhandled_exception
|
||||
.type _unhandled_exception, @function
|
||||
_unhandled_exception:
|
||||
b _unhandled_exception
|
||||
|
||||
#endif /* !defined(__DOXYGEN__) */
|
||||
|
||||
/** @} */
|
||||
|
|
@ -1,93 +0,0 @@
|
|||
/*
|
||||
ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
|
||||
|
||||
Licensed under the Apache License, Version 2.0 (the "License");
|
||||
you may not use this file except in compliance with the License.
|
||||
You may obtain a copy of the License at
|
||||
|
||||
http://www.apache.org/licenses/LICENSE-2.0
|
||||
|
||||
Unless required by applicable law or agreed to in writing, software
|
||||
distributed under the License is distributed on an "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
See the License for the specific language governing permissions and
|
||||
limitations under the License.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file SPC564Axx/intc.h
|
||||
* @brief SPC564Axx INTC module header.
|
||||
*
|
||||
* @addtogroup INTC
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifndef _INTC_H_
|
||||
#define _INTC_H_
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Module constants. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @name INTC addresses
|
||||
* @{
|
||||
*/
|
||||
#define INTC_BASE 0xFFF48000
|
||||
#define INTC_IACKR_ADDR (INTC_BASE + 0x10)
|
||||
#define INTC_EOIR_ADDR (INTC_BASE + 0x18)
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @brief INTC priority levels.
|
||||
*/
|
||||
#define INTC_PRIORITY_LEVELS 16U
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Module pre-compile time settings. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Derived constants and error checks. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Module data structures and types. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Module macros. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @name INTC-related macros
|
||||
* @{
|
||||
*/
|
||||
#define INTC_BCR (*((volatile uint32_t *)(INTC_BASE + 0)))
|
||||
#define INTC_CPR(n) (*((volatile uint32_t *)(INTC_BASE + 8 + ((n) * sizeof (uint32_t)))))
|
||||
#define INTC_IACKR(n) (*((volatile uint32_t *)(INTC_BASE + 0x10 + ((n) * sizeof (uint32_t)))))
|
||||
#define INTC_EOIR(n) (*((volatile uint32_t *)(INTC_BASE + 0x18 + ((n) * sizeof (uint32_t)))))
|
||||
#define INTC_PSR(n) (*((volatile uint8_t *)(INTC_BASE + 0x40 + ((n) * sizeof (uint8_t)))))
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @brief Core selection macros for PSR register.
|
||||
*/
|
||||
#define INTC_PSR_CORE0 0x00
|
||||
|
||||
/**
|
||||
* @brief PSR register content helper
|
||||
*/
|
||||
#define INTC_PSR_ENABLE(cores, prio) ((uint32_t)(cores) | (uint32_t)(prio))
|
||||
|
||||
/*===========================================================================*/
|
||||
/* External declarations. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Module inline functions. */
|
||||
/*===========================================================================*/
|
||||
|
||||
#endif /* _INTC_H_ */
|
||||
|
||||
/** @} */
|
||||
|
|
@ -1,83 +0,0 @@
|
|||
/*
|
||||
ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
|
||||
|
||||
Licensed under the Apache License, Version 2.0 (the "License");
|
||||
you may not use this file except in compliance with the License.
|
||||
You may obtain a copy of the License at
|
||||
|
||||
http://www.apache.org/licenses/LICENSE-2.0
|
||||
|
||||
Unless required by applicable law or agreed to in writing, software
|
||||
distributed under the License is distributed on an "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
See the License for the specific language governing permissions and
|
||||
limitations under the License.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file SPC564Axx/ppcparams.h
|
||||
* @brief PowerPC parameters for the SPC564Axx.
|
||||
*
|
||||
* @defgroup PPC_SPC564Axx SPC564Axx Specific Parameters
|
||||
* @ingroup PPC_SPECIFIC
|
||||
* @details This file contains the PowerPC specific parameters for the
|
||||
* SPC564Axx platform.
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifndef _PPCPARAMS_H_
|
||||
#define _PPCPARAMS_H_
|
||||
|
||||
/**
|
||||
* @brief Family identification macro.
|
||||
*/
|
||||
#define PPC_SPC564Axx
|
||||
|
||||
/**
|
||||
* @brief PPC core model.
|
||||
*/
|
||||
#define PPC_VARIANT PPC_VARIANT_e200z4
|
||||
|
||||
/**
|
||||
* @brief Number of cores.
|
||||
*/
|
||||
#define PPC_CORE_NUMBER 1
|
||||
|
||||
/**
|
||||
* @brief Number of writable bits in IVPR register.
|
||||
*/
|
||||
#define PPC_IVPR_BITS 16
|
||||
|
||||
/**
|
||||
* @brief IVORx registers support.
|
||||
*/
|
||||
#define PPC_SUPPORTS_IVORS TRUE
|
||||
|
||||
/**
|
||||
* @brief Book E instruction set support.
|
||||
*/
|
||||
#define PPC_SUPPORTS_BOOKE TRUE
|
||||
|
||||
/**
|
||||
* @brief VLE instruction set support.
|
||||
*/
|
||||
#define PPC_SUPPORTS_VLE TRUE
|
||||
|
||||
/**
|
||||
* @brief Supports VLS Load/Store Multiple Volatile instructions.
|
||||
*/
|
||||
#define PPC_SUPPORTS_VLE_MULTI TRUE
|
||||
|
||||
/**
|
||||
* @brief Supports the decrementer timer.
|
||||
*/
|
||||
#define PPC_SUPPORTS_DECREMENTER TRUE
|
||||
|
||||
/**
|
||||
* @brief Number of interrupt sources.
|
||||
*/
|
||||
#define PPC_NUM_VECTORS 486
|
||||
|
||||
#endif /* _PPCPARAMS_H_ */
|
||||
|
||||
/** @} */
|
||||
|
|
@ -1,248 +0,0 @@
|
|||
/*
|
||||
ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
|
||||
|
||||
Licensed under the Apache License, Version 2.0 (the "License");
|
||||
you may not use this file except in compliance with the License.
|
||||
You may obtain a copy of the License at
|
||||
|
||||
http://www.apache.org/licenses/LICENSE-2.0
|
||||
|
||||
Unless required by applicable law or agreed to in writing, software
|
||||
distributed under the License is distributed on an "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
See the License for the specific language governing permissions and
|
||||
limitations under the License.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file boot.h
|
||||
* @brief Boot parameters for the SPC56ECxx.
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifndef _BOOT_H_
|
||||
#define _BOOT_H_
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Module constants. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @name MASx registers definitions
|
||||
* @{
|
||||
*/
|
||||
#define MAS0_TBLMAS_TBL 0x10000000
|
||||
#define MAS0_ESEL_MASK 0x000F0000
|
||||
#define MAS0_ESEL(n) ((n) << 16)
|
||||
|
||||
#define MAS1_VALID 0x80000000
|
||||
#define MAS1_IPROT 0x40000000
|
||||
#define MAS1_TID_MASK 0x00FF0000
|
||||
#define MAS1_TS 0x00001000
|
||||
#define MAS1_TSISE_MASK 0x00000F80
|
||||
#define MAS1_TSISE_1K 0x00000000
|
||||
#define MAS1_TSISE_2K 0x00000080
|
||||
#define MAS1_TSISE_4K 0x00000100
|
||||
#define MAS1_TSISE_8K 0x00000180
|
||||
#define MAS1_TSISE_16K 0x00000200
|
||||
#define MAS1_TSISE_32K 0x00000280
|
||||
#define MAS1_TSISE_64K 0x00000300
|
||||
#define MAS1_TSISE_128K 0x00000380
|
||||
#define MAS1_TSISE_256K 0x00000400
|
||||
#define MAS1_TSISE_512K 0x00000480
|
||||
#define MAS1_TSISE_1M 0x00000500
|
||||
#define MAS1_TSISE_2M 0x00000580
|
||||
#define MAS1_TSISE_4M 0x00000600
|
||||
#define MAS1_TSISE_8M 0x00000680
|
||||
#define MAS1_TSISE_16M 0x00000700
|
||||
#define MAS1_TSISE_32M 0x00000780
|
||||
#define MAS1_TSISE_64M 0x00000800
|
||||
#define MAS1_TSISE_128M 0x00000880
|
||||
#define MAS1_TSISE_256M 0x00000900
|
||||
#define MAS1_TSISE_512M 0x00000980
|
||||
#define MAS1_TSISE_1G 0x00000A00
|
||||
#define MAS1_TSISE_2G 0x00000A80
|
||||
#define MAS1_TSISE_4G 0x00000B00
|
||||
|
||||
#define MAS2_EPN_MASK 0xFFFFFC00
|
||||
#define MAS2_EPN(n) ((n) & MAS2_EPN_MASK)
|
||||
#define MAS2_EBOOK 0x00000000
|
||||
#define MAS2_VLE 0x00000020
|
||||
#define MAS2_W 0x00000010
|
||||
#define MAS2_I 0x00000008
|
||||
#define MAS2_M 0x00000004
|
||||
#define MAS2_G 0x00000002
|
||||
#define MAS2_E 0x00000001
|
||||
|
||||
#define MAS3_RPN_MASK 0xFFFFFC00
|
||||
#define MAS3_RPN(n) ((n) & MAS3_RPN_MASK)
|
||||
#define MAS3_U0 0x00000200
|
||||
#define MAS3_U1 0x00000100
|
||||
#define MAS3_U2 0x00000080
|
||||
#define MAS3_U3 0x00000040
|
||||
#define MAS3_UX 0x00000020
|
||||
#define MAS3_SX 0x00000010
|
||||
#define MAS3_UW 0x00000008
|
||||
#define MAS3_SW 0x00000004
|
||||
#define MAS3_UR 0x00000002
|
||||
#define MAS3_SR 0x00000001
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @name BUCSR registers definitions
|
||||
* @{
|
||||
*/
|
||||
#define BUCSR_BPEN 0x00000001
|
||||
#define BUCSR_BPRED_MASK 0x00000006
|
||||
#define BUCSR_BPRED_0 0x00000000
|
||||
#define BUCSR_BPRED_1 0x00000002
|
||||
#define BUCSR_BPRED_2 0x00000004
|
||||
#define BUCSR_BPRED_3 0x00000006
|
||||
#define BUCSR_BALLOC_MASK 0x00000030
|
||||
#define BUCSR_BALLOC_0 0x00000000
|
||||
#define BUCSR_BALLOC_1 0x00000010
|
||||
#define BUCSR_BALLOC_2 0x00000020
|
||||
#define BUCSR_BALLOC_3 0x00000030
|
||||
#define BUCSR_BALLOC_BFI 0x00000200
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @name LICSR1 registers definitions
|
||||
* @{
|
||||
*/
|
||||
#define LICSR1_ICE 0x00000001
|
||||
#define LICSR1_ICINV 0x00000002
|
||||
#define LICSR1_ICORG 0x00000010
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @name MSR register definitions
|
||||
* @{
|
||||
*/
|
||||
#define MSR_UCLE 0x04000000
|
||||
#define MSR_SPE 0x02000000
|
||||
#define MSR_WE 0x00040000
|
||||
#define MSR_CE 0x00020000
|
||||
#define MSR_EE 0x00008000
|
||||
#define MSR_PR 0x00004000
|
||||
#define MSR_FP 0x00002000
|
||||
#define MSR_ME 0x00001000
|
||||
#define MSR_FE0 0x00000800
|
||||
#define MSR_DE 0x00000200
|
||||
#define MSR_FE1 0x00000100
|
||||
#define MSR_IS 0x00000020
|
||||
#define MSR_DS 0x00000010
|
||||
#define MSR_RI 0x00000002
|
||||
/** @} */
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Module pre-compile time settings. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*
|
||||
* TLB default settings.
|
||||
*/
|
||||
#define TLB0_MAS0 (MAS0_TBLMAS_TBL | MAS0_ESEL(0))
|
||||
#define TLB0_MAS1 (MAS1_VALID | MAS1_IPROT | MAS1_TSISE_4M)
|
||||
#define TLB0_MAS2 (MAS2_EPN(0x00000000) | MAS2_VLE)
|
||||
#define TLB0_MAS3 (MAS3_RPN(0x00000000) | \
|
||||
MAS3_UX | MAS3_SX | MAS3_UW | MAS3_SW | \
|
||||
MAS3_UR | MAS3_SR)
|
||||
|
||||
#define TLB1_MAS0 (MAS0_TBLMAS_TBL | MAS0_ESEL(1))
|
||||
#define TLB1_MAS1 (MAS1_VALID | MAS1_IPROT | MAS1_TSISE_256K)
|
||||
#define TLB1_MAS2 (MAS2_EPN(0x40000000) | MAS2_VLE)
|
||||
#define TLB1_MAS3 (MAS3_RPN(0x40000000) | \
|
||||
MAS3_UX | MAS3_SX | MAS3_UW | MAS3_SW | \
|
||||
MAS3_UR | MAS3_SR)
|
||||
|
||||
#define TLB2_MAS0 (MAS0_TBLMAS_TBL | MAS0_ESEL(2))
|
||||
#define TLB2_MAS1 (MAS1_VALID | MAS1_IPROT | MAS1_TSISE_1M)
|
||||
#define TLB2_MAS2 (MAS2_EPN(0xC3F00000) | MAS2_I)
|
||||
#define TLB2_MAS3 (MAS3_RPN(0xC3F00000) | \
|
||||
MAS3_UW | MAS3_SW | MAS3_UR | MAS3_SR)
|
||||
|
||||
#define TLB3_MAS0 (MAS0_TBLMAS_TBL | MAS0_ESEL(3))
|
||||
#define TLB3_MAS1 (MAS1_VALID | MAS1_IPROT | MAS1_TSISE_1M)
|
||||
#define TLB3_MAS2 (MAS2_EPN(0xFFE00000) | MAS2_I)
|
||||
#define TLB3_MAS3 (MAS3_RPN(0xFFE00000) | \
|
||||
MAS3_UW | MAS3_SW | MAS3_UR | MAS3_SR)
|
||||
|
||||
#define TLB4_MAS0 (MAS0_TBLMAS_TBL | MAS0_ESEL(4))
|
||||
#define TLB4_MAS1 (MAS1_VALID | MAS1_IPROT | MAS1_TSISE_1M)
|
||||
#define TLB4_MAS2 (MAS2_EPN(0x8FF00000) | MAS2_I)
|
||||
#define TLB4_MAS3 (MAS3_RPN(0x8FF00000) | \
|
||||
MAS3_UW | MAS3_SW | MAS3_UR | MAS3_SR)
|
||||
|
||||
#define TLB5_MAS0 (MAS0_TBLMAS_TBL | MAS0_ESEL(5))
|
||||
#define TLB5_MAS1 (MAS1_VALID | MAS1_IPROT | MAS1_TSISE_1M)
|
||||
#define TLB5_MAS2 (MAS2_EPN(0xFFF00000) | MAS2_I)
|
||||
#define TLB5_MAS3 (MAS3_RPN(0xFFF00000) | \
|
||||
MAS3_UW | MAS3_SW | MAS3_UR | MAS3_SR)
|
||||
|
||||
/*
|
||||
* BUCSR default settings.
|
||||
*/
|
||||
#if !defined(BOOT_BUCSR_DEFAULT) || defined(__DOXYGEN__)
|
||||
#define BOOT_BUCSR_DEFAULT (BUCSR_BPEN | BUCSR_BPRED_0 | \
|
||||
BUCSR_BALLOC_0 | BUCSR_BALLOC_BFI)
|
||||
#endif
|
||||
|
||||
/*
|
||||
* LICSR1 default settings.
|
||||
*/
|
||||
#if !defined(BOOT_LICSR1_DEFAULT) || defined(__DOXYGEN__)
|
||||
#define BOOT_LICSR1_DEFAULT (LICSR1_ICE | LICSR1_ICORG)
|
||||
#endif
|
||||
|
||||
/*
|
||||
* MSR default settings.
|
||||
*/
|
||||
#if !defined(BOOT_MSR_DEFAULT) || defined(__DOXYGEN__)
|
||||
#define BOOT_MSR_DEFAULT (MSR_SPE | MSR_WE | MSR_CE | MSR_ME)
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Boot default settings.
|
||||
*/
|
||||
#if !defined(BOOT_PERFORM_CORE_INIT) || defined(__DOXYGEN__)
|
||||
#define BOOT_PERFORM_CORE_INIT 1
|
||||
#endif
|
||||
|
||||
/*
|
||||
* VLE mode default settings.
|
||||
*/
|
||||
#if !defined(BOOT_USE_VLE) || defined(__DOXYGEN__)
|
||||
#define BOOT_USE_VLE 1
|
||||
#endif
|
||||
|
||||
/*
|
||||
* RAM relocation flag.
|
||||
*/
|
||||
#if !defined(BOOT_RELOCATE_IN_RAM) || defined(__DOXYGEN__)
|
||||
#define BOOT_RELOCATE_IN_RAM 0
|
||||
#endif
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Derived constants and error checks. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Module data structures and types. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Module macros. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* External declarations. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Module inline functions. */
|
||||
/*===========================================================================*/
|
||||
|
||||
#endif /* _BOOT_H_ */
|
||||
|
||||
/** @} */
|
||||
|
|
@ -1,403 +0,0 @@
|
|||
/*
|
||||
ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
|
||||
|
||||
Licensed under the Apache License, Version 2.0 (the "License");
|
||||
you may not use this file except in compliance with the License.
|
||||
You may obtain a copy of the License at
|
||||
|
||||
http://www.apache.org/licenses/LICENSE-2.0
|
||||
|
||||
Unless required by applicable law or agreed to in writing, software
|
||||
distributed under the License is distributed on an "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
See the License for the specific language governing permissions and
|
||||
limitations under the License.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file SPC56ECxx/boot.s
|
||||
* @brief SPC56ECxx boot-related code.
|
||||
*
|
||||
* @addtogroup PPC_BOOT
|
||||
* @{
|
||||
*/
|
||||
|
||||
#include "boot.h"
|
||||
|
||||
#if !defined(__DOXYGEN__)
|
||||
|
||||
/* BAM record.*/
|
||||
.section .boot, "ax"
|
||||
|
||||
#if BOOT_USE_VLE
|
||||
.long 0x015A0000
|
||||
#else
|
||||
.long 0x005A0000
|
||||
#endif
|
||||
.long _reset_address
|
||||
|
||||
.align 2
|
||||
.globl _reset_address
|
||||
.type _reset_address, @function
|
||||
_reset_address:
|
||||
#if BOOT_PERFORM_CORE_INIT
|
||||
bl _coreinit
|
||||
#endif
|
||||
bl _ivinit
|
||||
|
||||
#if BOOT_RELOCATE_IN_RAM
|
||||
/*
|
||||
* Image relocation in RAM.
|
||||
*/
|
||||
lis %r4, __ram_reloc_start__@h
|
||||
ori %r4, %r4, __ram_reloc_start__@l
|
||||
lis %r5, __ram_reloc_dest__@h
|
||||
ori %r5, %r5, __ram_reloc_dest__@l
|
||||
lis %r6, __ram_reloc_end__@h
|
||||
ori %r6, %r6, __ram_reloc_end__@l
|
||||
.relloop:
|
||||
cmpl cr0, %r4, %r6
|
||||
bge cr0, .relend
|
||||
lwz %r7, 0(%r4)
|
||||
addi %r4, %r4, 4
|
||||
stw %r7, 0(%r5)
|
||||
addi %r5, %r5, 4
|
||||
b .relloop
|
||||
.relend:
|
||||
lis %r3, _boot_address@h
|
||||
ori %r3, %r3, _boot_address@l
|
||||
mtctr %r3
|
||||
bctrl
|
||||
#else
|
||||
b _boot_address
|
||||
#endif
|
||||
|
||||
#if BOOT_PERFORM_CORE_INIT
|
||||
.align 2
|
||||
_ramcode:
|
||||
tlbwe
|
||||
isync
|
||||
blr
|
||||
|
||||
.align 2
|
||||
_coreinit:
|
||||
/*
|
||||
* Invalidating all TLBs except TLB0.
|
||||
*/
|
||||
lis %r3, 0
|
||||
mtspr 625, %r3 /* MAS1 */
|
||||
mtspr 626, %r3 /* MAS2 */
|
||||
mtspr 627, %r3 /* MAS3 */
|
||||
lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(1))@h
|
||||
mtspr 624, %r3 /* MAS0 */
|
||||
tlbwe
|
||||
lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(2))@h
|
||||
mtspr 624, %r3 /* MAS0 */
|
||||
tlbwe
|
||||
lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(3))@h
|
||||
mtspr 624, %r3 /* MAS0 */
|
||||
tlbwe
|
||||
lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(4))@h
|
||||
mtspr 624, %r3 /* MAS0 */
|
||||
tlbwe
|
||||
lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(5))@h
|
||||
mtspr 624, %r3 /* MAS0 */
|
||||
tlbwe
|
||||
lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(6))@h
|
||||
mtspr 624, %r3 /* MAS0 */
|
||||
tlbwe
|
||||
lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(7))@h
|
||||
mtspr 624, %r3 /* MAS0 */
|
||||
tlbwe
|
||||
lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(8))@h
|
||||
mtspr 624, %r3 /* MAS0 */
|
||||
tlbwe
|
||||
lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(9))@h
|
||||
mtspr 624, %r3 /* MAS0 */
|
||||
tlbwe
|
||||
lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(10))@h
|
||||
mtspr 624, %r3 /* MAS0 */
|
||||
tlbwe
|
||||
lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(11))@h
|
||||
mtspr 624, %r3 /* MAS0 */
|
||||
tlbwe
|
||||
lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(12))@h
|
||||
mtspr 624, %r3 /* MAS0 */
|
||||
tlbwe
|
||||
lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(13))@h
|
||||
mtspr 624, %r3 /* MAS0 */
|
||||
tlbwe
|
||||
lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(14))@h
|
||||
mtspr 624, %r3 /* MAS0 */
|
||||
tlbwe
|
||||
lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(15))@h
|
||||
mtspr 624, %r3 /* MAS0 */
|
||||
tlbwe
|
||||
|
||||
/*
|
||||
* TLB1 allocated to internal RAM.
|
||||
*/
|
||||
lis %r3, TLB1_MAS0@h
|
||||
mtspr 624, %r3 /* MAS0 */
|
||||
lis %r3, TLB1_MAS1@h
|
||||
ori %r3, %r3, TLB1_MAS1@l
|
||||
mtspr 625, %r3 /* MAS1 */
|
||||
lis %r3, TLB1_MAS2@h
|
||||
ori %r3, %r3, TLB1_MAS2@l
|
||||
mtspr 626, %r3 /* MAS2 */
|
||||
lis %r3, TLB1_MAS3@h
|
||||
ori %r3, %r3, TLB1_MAS3@l
|
||||
mtspr 627, %r3 /* MAS3 */
|
||||
tlbwe
|
||||
|
||||
/*
|
||||
* TLB2 allocated to internal Peripherals Bridge A.
|
||||
*/
|
||||
lis %r3, TLB2_MAS0@h
|
||||
mtspr 624, %r3 /* MAS0 */
|
||||
lis %r3, TLB2_MAS1@h
|
||||
ori %r3, %r3, TLB2_MAS1@l
|
||||
mtspr 625, %r3 /* MAS1 */
|
||||
lis %r3, TLB2_MAS2@h
|
||||
ori %r3, %r3, TLB2_MAS2@l
|
||||
mtspr 626, %r3 /* MAS2 */
|
||||
lis %r3, TLB2_MAS3@h
|
||||
ori %r3, %r3, TLB2_MAS3@l
|
||||
mtspr 627, %r3 /* MAS3 */
|
||||
tlbwe
|
||||
|
||||
/*
|
||||
* TLB3 allocated to internal Peripherals Bridge B.
|
||||
*/
|
||||
lis %r3, TLB3_MAS0@h
|
||||
mtspr 624, %r3 /* MAS0 */
|
||||
lis %r3, TLB3_MAS1@h
|
||||
ori %r3, %r3, TLB3_MAS1@l
|
||||
mtspr 625, %r3 /* MAS1 */
|
||||
lis %r3, TLB3_MAS2@h
|
||||
ori %r3, %r3, TLB3_MAS2@l
|
||||
mtspr 626, %r3 /* MAS2 */
|
||||
lis %r3, TLB3_MAS3@h
|
||||
ori %r3, %r3, TLB3_MAS3@l
|
||||
mtspr 627, %r3 /* MAS3 */
|
||||
tlbwe
|
||||
|
||||
/*
|
||||
* TLB4 allocated to on-platform peripherals.
|
||||
*/
|
||||
lis %r3, TLB4_MAS0@h
|
||||
mtspr 624, %r3 /* MAS0 */
|
||||
lis %r3, TLB4_MAS1@h
|
||||
ori %r3, %r3, TLB4_MAS1@l
|
||||
mtspr 625, %r3 /* MAS1 */
|
||||
lis %r3, TLB4_MAS2@h
|
||||
ori %r3, %r3, TLB4_MAS2@l
|
||||
mtspr 626, %r3 /* MAS2 */
|
||||
lis %r3, TLB4_MAS3@h
|
||||
ori %r3, %r3, TLB4_MAS3@l
|
||||
mtspr 627, %r3 /* MAS3 */
|
||||
tlbwe
|
||||
|
||||
/*
|
||||
* TLB5 allocated to on-platform peripherals.
|
||||
*/
|
||||
lis %r3, TLB5_MAS0@h
|
||||
mtspr 624, %r3 /* MAS0 */
|
||||
lis %r3, TLB5_MAS1@h
|
||||
ori %r3, %r3, TLB5_MAS1@l
|
||||
mtspr 625, %r3 /* MAS1 */
|
||||
lis %r3, TLB5_MAS2@h
|
||||
ori %r3, %r3, TLB5_MAS2@l
|
||||
mtspr 626, %r3 /* MAS2 */
|
||||
lis %r3, TLB5_MAS3@h
|
||||
ori %r3, %r3, TLB5_MAS3@l
|
||||
mtspr 627, %r3 /* MAS3 */
|
||||
tlbwe
|
||||
|
||||
/*
|
||||
* RAM clearing, this device requires a write to all RAM location in
|
||||
* order to initialize the ECC detection hardware, this is going to
|
||||
* slow down the startup but there is no way around.
|
||||
*/
|
||||
xor %r0, %r0, %r0
|
||||
xor %r1, %r1, %r1
|
||||
xor %r2, %r2, %r2
|
||||
xor %r3, %r3, %r3
|
||||
xor %r4, %r4, %r4
|
||||
xor %r5, %r5, %r5
|
||||
xor %r6, %r6, %r6
|
||||
xor %r7, %r7, %r7
|
||||
xor %r8, %r8, %r8
|
||||
xor %r9, %r9, %r9
|
||||
xor %r10, %r10, %r10
|
||||
xor %r11, %r11, %r11
|
||||
xor %r12, %r12, %r12
|
||||
xor %r13, %r13, %r13
|
||||
xor %r14, %r14, %r14
|
||||
xor %r15, %r15, %r15
|
||||
xor %r16, %r16, %r16
|
||||
xor %r17, %r17, %r17
|
||||
xor %r18, %r18, %r18
|
||||
xor %r19, %r19, %r19
|
||||
xor %r20, %r20, %r20
|
||||
xor %r21, %r21, %r21
|
||||
xor %r22, %r22, %r22
|
||||
xor %r23, %r23, %r23
|
||||
xor %r24, %r24, %r24
|
||||
xor %r25, %r25, %r25
|
||||
xor %r26, %r26, %r26
|
||||
xor %r27, %r27, %r27
|
||||
xor %r28, %r28, %r28
|
||||
xor %r29, %r29, %r29
|
||||
xor %r30, %r30, %r30
|
||||
xor %r31, %r31, %r31
|
||||
lis %r4, __ram_start__@h
|
||||
ori %r4, %r4, __ram_start__@l
|
||||
lis %r5, __ram_end__@h
|
||||
ori %r5, %r5, __ram_end__@l
|
||||
.cleareccloop:
|
||||
cmpl %cr0, %r4, %r5
|
||||
bge %cr0, .cleareccend
|
||||
stmw %r16, 0(%r4)
|
||||
addi %r4, %r4, 64
|
||||
b .cleareccloop
|
||||
.cleareccend:
|
||||
|
||||
/*
|
||||
* Special function registers clearing, required in order to avoid
|
||||
* possible problems with lockstep mode.
|
||||
*/
|
||||
mtcrf 0xFF, %r31
|
||||
mtspr 9, %r31 /* CTR */
|
||||
mtspr 22, %r31 /* DEC */
|
||||
mtspr 26, %r31 /* SRR0-1 */
|
||||
mtspr 27, %r31
|
||||
mtspr 54, %r31 /* DECAR */
|
||||
mtspr 58, %r31 /* CSRR0-1 */
|
||||
mtspr 59, %r31
|
||||
mtspr 61, %r31 /* DEAR */
|
||||
mtspr 256, %r31 /* USPRG0 */
|
||||
mtspr 272, %r31 /* SPRG1-7 */
|
||||
mtspr 273, %r31
|
||||
mtspr 274, %r31
|
||||
mtspr 275, %r31
|
||||
mtspr 276, %r31
|
||||
mtspr 277, %r31
|
||||
mtspr 278, %r31
|
||||
mtspr 279, %r31
|
||||
mtspr 285, %r31 /* TBU */
|
||||
mtspr 284, %r31 /* TBL */
|
||||
#if 0
|
||||
mtspr 318, %r31 /* DVC1-2 */
|
||||
mtspr 319, %r31
|
||||
#endif
|
||||
mtspr 562, %r31 /* DBCNT */
|
||||
mtspr 570, %r31 /* MCSRR0 */
|
||||
mtspr 571, %r31 /* MCSRR1 */
|
||||
mtspr 604, %r31 /* SPRG8-9 */
|
||||
mtspr 605, %r31
|
||||
|
||||
/*
|
||||
* *Finally* the TLB0 is re-allocated to flash, note, the final phase
|
||||
* is executed from RAM.
|
||||
*/
|
||||
lis %r3, TLB0_MAS0@h
|
||||
mtspr 624, %r3 /* MAS0 */
|
||||
lis %r3, TLB0_MAS1@h
|
||||
ori %r3, %r3, TLB0_MAS1@l
|
||||
mtspr 625, %r3 /* MAS1 */
|
||||
lis %r3, TLB0_MAS2@h
|
||||
ori %r3, %r3, TLB0_MAS2@l
|
||||
mtspr 626, %r3 /* MAS2 */
|
||||
lis %r3, TLB0_MAS3@h
|
||||
ori %r3, %r3, TLB0_MAS3@l
|
||||
mtspr 627, %r3 /* MAS3 */
|
||||
mflr %r4
|
||||
lis %r6, _ramcode@h
|
||||
ori %r6, %r6, _ramcode@l
|
||||
lis %r7, 0x40010000@h
|
||||
mtctr %r7
|
||||
lwz %r3, 0(%r6)
|
||||
stw %r3, 0(%r7)
|
||||
lwz %r3, 4(%r6)
|
||||
stw %r3, 4(%r7)
|
||||
lwz %r3, 8(%r6)
|
||||
stw %r3, 8(%r7)
|
||||
bctrl
|
||||
mtlr %r4
|
||||
|
||||
/*
|
||||
* Branch prediction enabled.
|
||||
*/
|
||||
li %r3, BOOT_BUCSR_DEFAULT
|
||||
mtspr 1013, %r3 /* BUCSR */
|
||||
|
||||
/*
|
||||
* Cache invalidated and then enabled.
|
||||
*/
|
||||
li %r3, LICSR1_ICINV
|
||||
mtspr 1011, %r3 /* LICSR1 */
|
||||
.inv: mfspr %r3, 1011 /* LICSR1 */
|
||||
andi. %r3, %r3, LICSR1_ICINV
|
||||
bne .inv
|
||||
lis %r3, BOOT_LICSR1_DEFAULT@h
|
||||
ori %r3, %r3, BOOT_LICSR1_DEFAULT@l
|
||||
mtspr 1011, %r3 /* LICSR1 */
|
||||
|
||||
blr
|
||||
#endif /* BOOT_PERFORM_CORE_INIT */
|
||||
|
||||
/*
|
||||
* Exception vectors initialization.
|
||||
*/
|
||||
.align 2
|
||||
_ivinit:
|
||||
/* MSR initialization.*/
|
||||
lis %r3, BOOT_MSR_DEFAULT@h
|
||||
ori %r3, %r3, BOOT_MSR_DEFAULT@l
|
||||
mtMSR %r3
|
||||
|
||||
/* IVPR initialization.*/
|
||||
lis %r3, __ivpr_base__@h
|
||||
ori %r3, %r3, __ivpr_base__@l
|
||||
mtIVPR %r3
|
||||
|
||||
/* IVORs initialization.*/
|
||||
lis %r3, _unhandled_exception@h
|
||||
ori %r3, %r3, _unhandled_exception@l
|
||||
|
||||
mtspr 400, %r3 /* IVOR0-15 */
|
||||
mtspr 401, %r3
|
||||
mtspr 402, %r3
|
||||
mtspr 403, %r3
|
||||
mtspr 404, %r3
|
||||
mtspr 405, %r3
|
||||
mtspr 406, %r3
|
||||
mtspr 407, %r3
|
||||
mtspr 408, %r3
|
||||
mtspr 409, %r3
|
||||
mtspr 410, %r3
|
||||
mtspr 411, %r3
|
||||
mtspr 412, %r3
|
||||
mtspr 413, %r3
|
||||
mtspr 414, %r3
|
||||
mtspr 415, %r3
|
||||
mtspr 528, %r3 /* IVOR32-34 */
|
||||
mtspr 529, %r3
|
||||
mtspr 530, %r3
|
||||
|
||||
blr
|
||||
|
||||
.section .handlers, "ax"
|
||||
|
||||
/*
|
||||
* Unhandled exceptions handler.
|
||||
*/
|
||||
.weak _unhandled_exception
|
||||
.type _unhandled_exception, @function
|
||||
_unhandled_exception:
|
||||
b _unhandled_exception
|
||||
|
||||
#endif /* !defined(__DOXYGEN__) */
|
||||
|
||||
/** @} */
|
||||
|
|
@ -1,400 +0,0 @@
|
|||
/*
|
||||
ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
|
||||
|
||||
Licensed under the Apache License, Version 2.0 (the "License");
|
||||
you may not use this file except in compliance with the License.
|
||||
You may obtain a copy of the License at
|
||||
|
||||
http://www.apache.org/licenses/LICENSE-2.0
|
||||
|
||||
Unless required by applicable law or agreed to in writing, software
|
||||
distributed under the License is distributed on an "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
See the License for the specific language governing permissions and
|
||||
limitations under the License.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file SPC56ECxx/boot.s
|
||||
* @brief SPC56ECxx boot-related code.
|
||||
*
|
||||
* @addtogroup PPC_BOOT
|
||||
* @{
|
||||
*/
|
||||
|
||||
#include "boot.h"
|
||||
|
||||
#if !defined(__DOXYGEN__)
|
||||
|
||||
.extern _boot_address
|
||||
.extern __ram_start__
|
||||
.extern __ram_end__
|
||||
.extern __ivpr_base__
|
||||
|
||||
.extern _unhandled_exception
|
||||
|
||||
/* BAM record.*/
|
||||
.section .boot, 16
|
||||
|
||||
#if BOOT_USE_VLE
|
||||
.long 0x015A0000
|
||||
#else
|
||||
.long 0x005A0000
|
||||
#endif
|
||||
.long _reset_address
|
||||
|
||||
.align 4
|
||||
.globl _reset_address
|
||||
.type _reset_address, @function
|
||||
_reset_address:
|
||||
#if BOOT_PERFORM_CORE_INIT
|
||||
e_bl _coreinit
|
||||
#endif
|
||||
e_bl _ivinit
|
||||
|
||||
#if BOOT_RELOCATE_IN_RAM
|
||||
/*
|
||||
* Image relocation in RAM.
|
||||
*/
|
||||
e_lis r4, __ram_reloc_start__@h
|
||||
e_or2i r4, r4, __ram_reloc_start__@l
|
||||
e_lis r5, __ram_reloc_dest__@h
|
||||
e_or2i r5, r5, __ram_reloc_dest__@l
|
||||
e_lis r6, __ram_reloc_end__@h
|
||||
e_or2i r6, r6, __ram_reloc_end__@l
|
||||
.relloop:
|
||||
se_cmpl r4, r6
|
||||
se_bge .relend
|
||||
se_lwz r7, 0(r4)
|
||||
se_addi r4, 4
|
||||
se_stw r7, 0(r5)
|
||||
se_addi r5, 4
|
||||
se_b .relloop
|
||||
.relend:
|
||||
e_lis r3, _boot_address@h
|
||||
e_or2i r3, _boot_address@l
|
||||
mtctr r3
|
||||
se_bctrl
|
||||
#else
|
||||
e_b _boot_address
|
||||
#endif
|
||||
|
||||
#if BOOT_PERFORM_CORE_INIT
|
||||
.align 4
|
||||
_ramcode:
|
||||
tlbwe
|
||||
se_isync
|
||||
se_blr
|
||||
|
||||
.align 2
|
||||
_coreinit:
|
||||
/*
|
||||
* Invalidating all TLBs except TLB0.
|
||||
*/
|
||||
e_lis r3, 0
|
||||
mtspr 625, r3 /* MAS1 */
|
||||
mtspr 626, r3 /* MAS2 */
|
||||
mtspr 627, r3 /* MAS3 */
|
||||
e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(1))@h
|
||||
mtspr 624, r3 /* MAS0 */
|
||||
tlbwe
|
||||
e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(2))@h
|
||||
mtspr 624, r3 /* MAS0 */
|
||||
tlbwe
|
||||
e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(3))@h
|
||||
mtspr 624, r3 /* MAS0 */
|
||||
tlbwe
|
||||
e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(4))@h
|
||||
mtspr 624, r3 /* MAS0 */
|
||||
tlbwe
|
||||
e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(5))@h
|
||||
mtspr 624, r3 /* MAS0 */
|
||||
tlbwe
|
||||
e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(6))@h
|
||||
mtspr 624, r3 /* MAS0 */
|
||||
tlbwe
|
||||
e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(7))@h
|
||||
mtspr 624, r3 /* MAS0 */
|
||||
tlbwe
|
||||
e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(8))@h
|
||||
mtspr 624, r3 /* MAS0 */
|
||||
tlbwe
|
||||
e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(9))@h
|
||||
mtspr 624, r3 /* MAS0 */
|
||||
tlbwe
|
||||
e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(10))@h
|
||||
mtspr 624, r3 /* MAS0 */
|
||||
tlbwe
|
||||
e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(11))@h
|
||||
mtspr 624, r3 /* MAS0 */
|
||||
tlbwe
|
||||
e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(12))@h
|
||||
mtspr 624, r3 /* MAS0 */
|
||||
tlbwe
|
||||
e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(13))@h
|
||||
mtspr 624, r3 /* MAS0 */
|
||||
tlbwe
|
||||
e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(14))@h
|
||||
mtspr 624, r3 /* MAS0 */
|
||||
tlbwe
|
||||
e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(15))@h
|
||||
mtspr 624, r3 /* MAS0 */
|
||||
tlbwe
|
||||
|
||||
/*
|
||||
* TLB1 allocated to internal RAM.
|
||||
*/
|
||||
e_lis r3, TLB1_MAS0@h
|
||||
mtspr 624, r3 /* MAS0 */
|
||||
e_lis r3, TLB1_MAS1@h
|
||||
e_or2i r3, TLB1_MAS1@l
|
||||
mtspr 625, r3 /* MAS1 */
|
||||
e_lis r3, TLB1_MAS2@h
|
||||
e_or2i r3, TLB1_MAS2@l
|
||||
mtspr 626, r3 /* MAS2 */
|
||||
e_lis r3, TLB1_MAS3@h
|
||||
e_or2i r3, TLB1_MAS3@l
|
||||
mtspr 627, r3 /* MAS3 */
|
||||
tlbwe
|
||||
|
||||
/*
|
||||
* TLB2 allocated to internal Peripherals Bridge A.
|
||||
*/
|
||||
e_lis r3, TLB2_MAS0@h
|
||||
mtspr 624, r3 /* MAS0 */
|
||||
e_lis r3, TLB2_MAS1@h
|
||||
e_or2i r3, TLB2_MAS1@l
|
||||
mtspr 625, r3 /* MAS1 */
|
||||
e_lis r3, TLB2_MAS2@h
|
||||
e_or2i r3, TLB2_MAS2@l
|
||||
mtspr 626, r3 /* MAS2 */
|
||||
e_lis r3, TLB2_MAS3@h
|
||||
e_or2i r3, TLB2_MAS3@l
|
||||
mtspr 627, r3 /* MAS3 */
|
||||
tlbwe
|
||||
|
||||
/*
|
||||
* TLB3 allocated to internal Peripherals Bridge B.
|
||||
*/
|
||||
e_lis r3, TLB3_MAS0@h
|
||||
mtspr 624, r3 /* MAS0 */
|
||||
e_lis r3, TLB3_MAS1@h
|
||||
e_or2i r3, TLB3_MAS1@l
|
||||
mtspr 625, r3 /* MAS1 */
|
||||
e_lis r3, TLB3_MAS2@h
|
||||
e_or2i r3, TLB3_MAS2@l
|
||||
mtspr 626, r3 /* MAS2 */
|
||||
e_lis r3, TLB3_MAS3@h
|
||||
e_or2i r3, TLB3_MAS3@l
|
||||
mtspr 627, r3 /* MAS3 */
|
||||
tlbwe
|
||||
|
||||
/*
|
||||
* TLB4 allocated to on-platform peripherals.
|
||||
*/
|
||||
e_lis r3, TLB4_MAS0@h
|
||||
mtspr 624, r3 /* MAS0 */
|
||||
e_lis r3, TLB4_MAS1@h
|
||||
e_or2i r3, TLB4_MAS1@l
|
||||
mtspr 625, r3 /* MAS1 */
|
||||
e_lis r3, TLB4_MAS2@h
|
||||
e_or2i r3, TLB4_MAS2@l
|
||||
mtspr 626, r3 /* MAS2 */
|
||||
e_lis r3, TLB4_MAS3@h
|
||||
e_or2i r3, TLB4_MAS3@l
|
||||
mtspr 627, r3 /* MAS3 */
|
||||
tlbwe
|
||||
|
||||
/*
|
||||
* TLB5 allocated to on-platform peripherals.
|
||||
*/
|
||||
e_lis r3, TLB5_MAS0@h
|
||||
mtspr 624, r3 /* MAS0 */
|
||||
e_lis r3, TLB5_MAS1@h
|
||||
e_or2i r3, TLB5_MAS1@l
|
||||
mtspr 625, r3 /* MAS1 */
|
||||
e_lis r3, TLB5_MAS2@h
|
||||
e_or2i r3, TLB5_MAS2@l
|
||||
mtspr 626, r3 /* MAS2 */
|
||||
e_lis r3, TLB5_MAS3@h
|
||||
e_or2i r3, TLB5_MAS3@l
|
||||
mtspr 627, r3 /* MAS3 */
|
||||
tlbwe
|
||||
|
||||
/*
|
||||
* RAM clearing, this device requires a write to all RAM location in
|
||||
* order to initialize the ECC detection hardware, this is going to
|
||||
* slow down the startup but there is no way around.
|
||||
*/
|
||||
xor r0, r0, r0
|
||||
xor r1, r1, r1
|
||||
xor r2, r2, r2
|
||||
xor r3, r3, r3
|
||||
xor r4, r4, r4
|
||||
xor r5, r5, r5
|
||||
xor r6, r6, r6
|
||||
xor r7, r7, r7
|
||||
xor r8, r8, r8
|
||||
xor r9, r9, r9
|
||||
xor r10, r10, r10
|
||||
xor r11, r11, r11
|
||||
xor r12, r12, r12
|
||||
xor r13, r13, r13
|
||||
xor r14, r14, r14
|
||||
xor r15, r15, r15
|
||||
xor r16, r16, r16
|
||||
xor r17, r17, r17
|
||||
xor r18, r18, r18
|
||||
xor r19, r19, r19
|
||||
xor r20, r20, r20
|
||||
xor r21, r21, r21
|
||||
xor r22, r22, r22
|
||||
xor r23, r23, r23
|
||||
xor r24, r24, r24
|
||||
xor r25, r25, r25
|
||||
xor r26, r26, r26
|
||||
xor r27, r27, r27
|
||||
xor r28, r28, r28
|
||||
xor r29, r29, r29
|
||||
xor r30, r30, r30
|
||||
xor r31, r31, r31
|
||||
e_lis r4, __ram_start__@h
|
||||
e_or2i r4, __ram_start__@l
|
||||
e_lis r5, __ram_end__@h
|
||||
e_or2i r5, __ram_end__@l
|
||||
.cleareccloop:
|
||||
se_cmpl r4, r5
|
||||
se_bge .cleareccend
|
||||
e_stmw r16, 0(r4)
|
||||
e_addi r4, r4, 64
|
||||
se_b .cleareccloop
|
||||
.cleareccend:
|
||||
|
||||
/*
|
||||
* Special function registers clearing, required in order to avoid
|
||||
* possible problems with lockstep mode.
|
||||
*/
|
||||
mtcrf 0xFF, r31
|
||||
mtspr 9, r31 /* CTR */
|
||||
mtspr 22, r31 /* DEC */
|
||||
mtspr 26, r31 /* SRR0-1 */
|
||||
mtspr 27, r31
|
||||
mtspr 54, r31 /* DECAR */
|
||||
mtspr 58, r31 /* CSRR0-1 */
|
||||
mtspr 59, r31
|
||||
mtspr 61, r31 /* DEAR */
|
||||
mtspr 256, r31 /* USPRG0 */
|
||||
mtspr 272, r31 /* SPRG1-7 */
|
||||
mtspr 273, r31
|
||||
mtspr 274, r31
|
||||
mtspr 275, r31
|
||||
mtspr 276, r31
|
||||
mtspr 277, r31
|
||||
mtspr 278, r31
|
||||
mtspr 279, r31
|
||||
mtspr 285, r31 /* TBU */
|
||||
mtspr 284, r31 /* TBL */
|
||||
#if 0
|
||||
mtspr 318, r31 /* DVC1-2 */
|
||||
mtspr 319, r31
|
||||
#endif
|
||||
mtspr 562, r31 /* DBCNT */
|
||||
mtspr 570, r31 /* MCSRR0 */
|
||||
mtspr 571, r31 /* MCSRR1 */
|
||||
mtspr 604, r31 /* SPRG8-9 */
|
||||
mtspr 605, r31
|
||||
|
||||
/*
|
||||
* *Finally* the TLB0 is re-allocated to flash, note, the final phase
|
||||
* is executed from RAM.
|
||||
*/
|
||||
e_lis r3, TLB0_MAS0@h
|
||||
mtspr 624, r3 /* MAS0 */
|
||||
e_lis r3, TLB0_MAS1@h
|
||||
e_or2i r3, TLB0_MAS1@l
|
||||
mtspr 625, r3 /* MAS1 */
|
||||
e_lis r3, TLB0_MAS2@h
|
||||
e_or2i r3, TLB0_MAS2@l
|
||||
mtspr 626, r3 /* MAS2 */
|
||||
e_lis r3, TLB0_MAS3@h
|
||||
e_or2i r3, TLB0_MAS3@l
|
||||
mtspr 627, r3 /* MAS3 */
|
||||
se_mflr r4
|
||||
e_lis r6, _ramcode@h
|
||||
e_or2i r6, _ramcode@l
|
||||
e_lis r7, 0x40010000@h
|
||||
mtctr r7
|
||||
se_lwz r3, 0(r6)
|
||||
se_stw r3, 0(r7)
|
||||
se_lwz r3, 4(r6)
|
||||
se_stw r3, 4(r7)
|
||||
se_lwz r3, 8(r6)
|
||||
se_stw r3, 8(r7)
|
||||
se_bctrl
|
||||
mtlr r4
|
||||
|
||||
/*
|
||||
* Branch prediction enabled.
|
||||
*/
|
||||
e_li r3, BOOT_BUCSR_DEFAULT
|
||||
mtspr 1013, r3 /* BUCSR */
|
||||
|
||||
/*
|
||||
* Cache invalidated and then enabled.
|
||||
*/
|
||||
se_li r3, LICSR1_ICINV
|
||||
mtspr 1011, r3 /* LICSR1 */
|
||||
.inv: mfspr r3, 1011 /* LICSR1 */
|
||||
e_andi. r3, r3, LICSR1_ICINV
|
||||
se_bne .inv
|
||||
e_lis r3, BOOT_LICSR1_DEFAULT@h
|
||||
e_or2i r3, BOOT_LICSR1_DEFAULT@l
|
||||
mtspr 1011, r3 /* LICSR1 */
|
||||
|
||||
se_blr
|
||||
#endif /* BOOT_PERFORM_CORE_INIT */
|
||||
|
||||
/*
|
||||
* Exception vectors initialization.
|
||||
*/
|
||||
.align 4
|
||||
_ivinit:
|
||||
/* MSR initialization.*/
|
||||
e_lis r3, BOOT_MSR_DEFAULT@h
|
||||
e_ori r3, r3, BOOT_MSR_DEFAULT@l
|
||||
mtMSR r3
|
||||
|
||||
/* IVPR initialization.*/
|
||||
e_lis r3, __ivpr_base__@h
|
||||
e_or2i r3, __ivpr_base__@l
|
||||
mtIVPR r3
|
||||
|
||||
/* IVORs initialization.*/
|
||||
e_lis r3, _unhandled_exception@h
|
||||
e_or2i r3, _unhandled_exception@l
|
||||
|
||||
mtspr 400, r3 /* IVOR0-15 */
|
||||
mtspr 401, r3
|
||||
mtspr 402, r3
|
||||
mtspr 403, r3
|
||||
mtspr 404, r3
|
||||
mtspr 405, r3
|
||||
mtspr 406, r3
|
||||
mtspr 407, r3
|
||||
mtspr 408, r3
|
||||
mtspr 409, r3
|
||||
mtspr 410, r3
|
||||
mtspr 411, r3
|
||||
mtspr 412, r3
|
||||
mtspr 413, r3
|
||||
mtspr 414, r3
|
||||
mtspr 415, r3
|
||||
mtspr 528, r3 /* IVOR32-34 */
|
||||
mtspr 529, r3
|
||||
mtspr 530, r3
|
||||
|
||||
se_blr
|
||||
|
||||
#endif /* !defined(__DOXYGEN__) */
|
||||
|
||||
/** @} */
|
||||
|
|
@ -1,95 +0,0 @@
|
|||
/*
|
||||
ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
|
||||
|
||||
Licensed under the Apache License, Version 2.0 (the "License");
|
||||
you may not use this file except in compliance with the License.
|
||||
You may obtain a copy of the License at
|
||||
|
||||
http://www.apache.org/licenses/LICENSE-2.0
|
||||
|
||||
Unless required by applicable law or agreed to in writing, software
|
||||
distributed under the License is distributed on an "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
See the License for the specific language governing permissions and
|
||||
limitations under the License.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file SPC56ECxx/intc.h
|
||||
* @brief SPC56ECxx INTC module header.
|
||||
*
|
||||
* @addtogroup INTC
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifndef _INTC_H_
|
||||
#define _INTC_H_
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Module constants. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @name INTC addresses
|
||||
* @{
|
||||
*/
|
||||
#define INTC_BASE 0xFFF48000
|
||||
#define INTC_IACKR_ADDR (INTC_BASE + 0x10)
|
||||
#define INTC_EOIR_ADDR (INTC_BASE + 0x18)
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @brief INTC priority levels.
|
||||
*/
|
||||
#define INTC_PRIORITY_LEVELS 16U
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Module pre-compile time settings. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Derived constants and error checks. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Module data structures and types. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Module macros. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @name INTC-related macros
|
||||
* @{
|
||||
*/
|
||||
#define INTC_BCR (*((volatile uint32_t *)(INTC_BASE + 0)))
|
||||
#define INTC_CPR(n) (*((volatile uint32_t *)(INTC_BASE + 8 + ((n) * sizeof (uint32_t)))))
|
||||
#define INTC_IACKR(n) (*((volatile uint32_t *)(INTC_BASE + 0x10 + ((n) * sizeof (uint32_t)))))
|
||||
#define INTC_EOIR(n) (*((volatile uint32_t *)(INTC_BASE + 0x18 + ((n) * sizeof (uint32_t)))))
|
||||
#define INTC_PSR(n) (*((volatile uint8_t *)(INTC_BASE + 0x40 + ((n) * sizeof (uint8_t)))))
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @brief Core selection macros for PSR register.
|
||||
*/
|
||||
#define INTC_PSR_CORE0 0x00
|
||||
#define INTC_PSR_CORE1 0xC0
|
||||
#define INTC_PSR_CORES01 0x40
|
||||
|
||||
/**
|
||||
* @brief PSR register content helper
|
||||
*/
|
||||
#define INTC_PSR_ENABLE(cores, prio) ((uint32_t)(cores) | (uint32_t)(prio))
|
||||
|
||||
/*===========================================================================*/
|
||||
/* External declarations. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Module inline functions. */
|
||||
/*===========================================================================*/
|
||||
|
||||
#endif /* _INTC_H_ */
|
||||
|
||||
/** @} */
|
||||
|
|
@ -1,83 +0,0 @@
|
|||
/*
|
||||
ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
|
||||
|
||||
Licensed under the Apache License, Version 2.0 (the "License");
|
||||
you may not use this file except in compliance with the License.
|
||||
You may obtain a copy of the License at
|
||||
|
||||
http://www.apache.org/licenses/LICENSE-2.0
|
||||
|
||||
Unless required by applicable law or agreed to in writing, software
|
||||
distributed under the License is distributed on an "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
See the License for the specific language governing permissions and
|
||||
limitations under the License.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file SPC56ECxx/ppcparams.h
|
||||
* @brief PowerPC parameters for the SPC56ECxx.
|
||||
*
|
||||
* @defgroup PPC_SPC56ECxx SPC56ECxx Specific Parameters
|
||||
* @ingroup PPC_SPECIFIC
|
||||
* @details This file contains the PowerPC specific parameters for the
|
||||
* SPC56ECxx platform.
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifndef _PPCPARAMS_H_
|
||||
#define _PPCPARAMS_H_
|
||||
|
||||
/**
|
||||
* @brief Family identification macro.
|
||||
*/
|
||||
#define PPC_SPC56ECxx
|
||||
|
||||
/**
|
||||
* @brief PPC core model.
|
||||
*/
|
||||
#define PPC_VARIANT PPC_VARIANT_e200z4
|
||||
|
||||
/**
|
||||
* @brief Number of cores.
|
||||
*/
|
||||
#define PPC_CORE_NUMBER 1
|
||||
|
||||
/**
|
||||
* @brief Number of writable bits in IVPR register.
|
||||
*/
|
||||
#define PPC_IVPR_BITS 16
|
||||
|
||||
/**
|
||||
* @brief IVORx registers support.
|
||||
*/
|
||||
#define PPC_SUPPORTS_IVORS TRUE
|
||||
|
||||
/**
|
||||
* @brief Book E instruction set support.
|
||||
*/
|
||||
#define PPC_SUPPORTS_BOOKE TRUE
|
||||
|
||||
/**
|
||||
* @brief VLE instruction set support.
|
||||
*/
|
||||
#define PPC_SUPPORTS_VLE TRUE
|
||||
|
||||
/**
|
||||
* @brief Supports VLS Load/Store Multiple Volatile instructions.
|
||||
*/
|
||||
#define PPC_SUPPORTS_VLE_MULTI TRUE
|
||||
|
||||
/**
|
||||
* @brief Supports the decrementer timer.
|
||||
*/
|
||||
#define PPC_SUPPORTS_DECREMENTER TRUE
|
||||
|
||||
/**
|
||||
* @brief Number of interrupt sources.
|
||||
*/
|
||||
#define PPC_NUM_VECTORS 279
|
||||
|
||||
#endif /* _PPCPARAMS_H_ */
|
||||
|
||||
/** @} */
|
||||
|
|
@ -1,248 +0,0 @@
|
|||
/*
|
||||
ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
|
||||
|
||||
Licensed under the Apache License, Version 2.0 (the "License");
|
||||
you may not use this file except in compliance with the License.
|
||||
You may obtain a copy of the License at
|
||||
|
||||
http://www.apache.org/licenses/LICENSE-2.0
|
||||
|
||||
Unless required by applicable law or agreed to in writing, software
|
||||
distributed under the License is distributed on an "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
See the License for the specific language governing permissions and
|
||||
limitations under the License.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file boot.h
|
||||
* @brief Boot parameters for the SPC56ELxx.
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifndef _BOOT_H_
|
||||
#define _BOOT_H_
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Module constants. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @name MASx registers definitions
|
||||
* @{
|
||||
*/
|
||||
#define MAS0_TBLMAS_TBL 0x10000000
|
||||
#define MAS0_ESEL_MASK 0x000F0000
|
||||
#define MAS0_ESEL(n) ((n) << 16)
|
||||
|
||||
#define MAS1_VALID 0x80000000
|
||||
#define MAS1_IPROT 0x40000000
|
||||
#define MAS1_TID_MASK 0x00FF0000
|
||||
#define MAS1_TS 0x00001000
|
||||
#define MAS1_TSISE_MASK 0x00000F80
|
||||
#define MAS1_TSISE_1K 0x00000000
|
||||
#define MAS1_TSISE_2K 0x00000080
|
||||
#define MAS1_TSISE_4K 0x00000100
|
||||
#define MAS1_TSISE_8K 0x00000180
|
||||
#define MAS1_TSISE_16K 0x00000200
|
||||
#define MAS1_TSISE_32K 0x00000280
|
||||
#define MAS1_TSISE_64K 0x00000300
|
||||
#define MAS1_TSISE_128K 0x00000380
|
||||
#define MAS1_TSISE_256K 0x00000400
|
||||
#define MAS1_TSISE_512K 0x00000480
|
||||
#define MAS1_TSISE_1M 0x00000500
|
||||
#define MAS1_TSISE_2M 0x00000580
|
||||
#define MAS1_TSISE_4M 0x00000600
|
||||
#define MAS1_TSISE_8M 0x00000680
|
||||
#define MAS1_TSISE_16M 0x00000700
|
||||
#define MAS1_TSISE_32M 0x00000780
|
||||
#define MAS1_TSISE_64M 0x00000800
|
||||
#define MAS1_TSISE_128M 0x00000880
|
||||
#define MAS1_TSISE_256M 0x00000900
|
||||
#define MAS1_TSISE_512M 0x00000980
|
||||
#define MAS1_TSISE_1G 0x00000A00
|
||||
#define MAS1_TSISE_2G 0x00000A80
|
||||
#define MAS1_TSISE_4G 0x00000B00
|
||||
|
||||
#define MAS2_EPN_MASK 0xFFFFFC00
|
||||
#define MAS2_EPN(n) ((n) & MAS2_EPN_MASK)
|
||||
#define MAS2_EBOOK 0x00000000
|
||||
#define MAS2_VLE 0x00000020
|
||||
#define MAS2_W 0x00000010
|
||||
#define MAS2_I 0x00000008
|
||||
#define MAS2_M 0x00000004
|
||||
#define MAS2_G 0x00000002
|
||||
#define MAS2_E 0x00000001
|
||||
|
||||
#define MAS3_RPN_MASK 0xFFFFFC00
|
||||
#define MAS3_RPN(n) ((n) & MAS3_RPN_MASK)
|
||||
#define MAS3_U0 0x00000200
|
||||
#define MAS3_U1 0x00000100
|
||||
#define MAS3_U2 0x00000080
|
||||
#define MAS3_U3 0x00000040
|
||||
#define MAS3_UX 0x00000020
|
||||
#define MAS3_SX 0x00000010
|
||||
#define MAS3_UW 0x00000008
|
||||
#define MAS3_SW 0x00000004
|
||||
#define MAS3_UR 0x00000002
|
||||
#define MAS3_SR 0x00000001
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @name BUCSR registers definitions
|
||||
* @{
|
||||
*/
|
||||
#define BUCSR_BPEN 0x00000001
|
||||
#define BUCSR_BPRED_MASK 0x00000006
|
||||
#define BUCSR_BPRED_0 0x00000000
|
||||
#define BUCSR_BPRED_1 0x00000002
|
||||
#define BUCSR_BPRED_2 0x00000004
|
||||
#define BUCSR_BPRED_3 0x00000006
|
||||
#define BUCSR_BALLOC_MASK 0x00000030
|
||||
#define BUCSR_BALLOC_0 0x00000000
|
||||
#define BUCSR_BALLOC_1 0x00000010
|
||||
#define BUCSR_BALLOC_2 0x00000020
|
||||
#define BUCSR_BALLOC_3 0x00000030
|
||||
#define BUCSR_BALLOC_BFI 0x00000200
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @name LICSR1 registers definitions
|
||||
* @{
|
||||
*/
|
||||
#define LICSR1_ICE 0x00000001
|
||||
#define LICSR1_ICINV 0x00000002
|
||||
#define LICSR1_ICORG 0x00000010
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @name MSR register definitions
|
||||
* @{
|
||||
*/
|
||||
#define MSR_UCLE 0x04000000
|
||||
#define MSR_SPE 0x02000000
|
||||
#define MSR_WE 0x00040000
|
||||
#define MSR_CE 0x00020000
|
||||
#define MSR_EE 0x00008000
|
||||
#define MSR_PR 0x00004000
|
||||
#define MSR_FP 0x00002000
|
||||
#define MSR_ME 0x00001000
|
||||
#define MSR_FE0 0x00000800
|
||||
#define MSR_DE 0x00000200
|
||||
#define MSR_FE1 0x00000100
|
||||
#define MSR_IS 0x00000020
|
||||
#define MSR_DS 0x00000010
|
||||
#define MSR_RI 0x00000002
|
||||
/** @} */
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Module pre-compile time settings. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*
|
||||
* TLB default settings.
|
||||
*/
|
||||
#define TLB0_MAS0 (MAS0_TBLMAS_TBL | MAS0_ESEL(0))
|
||||
#define TLB0_MAS1 (MAS1_VALID | MAS1_IPROT | MAS1_TSISE_2M)
|
||||
#define TLB0_MAS2 (MAS2_EPN(0x00000000) | MAS2_VLE)
|
||||
#define TLB0_MAS3 (MAS3_RPN(0x00000000) | \
|
||||
MAS3_UX | MAS3_SX | MAS3_UW | MAS3_SW | \
|
||||
MAS3_UR | MAS3_SR)
|
||||
|
||||
#define TLB1_MAS0 (MAS0_TBLMAS_TBL | MAS0_ESEL(1))
|
||||
#define TLB1_MAS1 (MAS1_VALID | MAS1_IPROT | MAS1_TSISE_256K)
|
||||
#define TLB1_MAS2 (MAS2_EPN(0x40000000) | MAS2_VLE)
|
||||
#define TLB1_MAS3 (MAS3_RPN(0x40000000) | \
|
||||
MAS3_UX | MAS3_SX | MAS3_UW | MAS3_SW | \
|
||||
MAS3_UR | MAS3_SR)
|
||||
|
||||
#define TLB2_MAS0 (MAS0_TBLMAS_TBL | MAS0_ESEL(2))
|
||||
#define TLB2_MAS1 (MAS1_VALID | MAS1_IPROT | MAS1_TSISE_1M)
|
||||
#define TLB2_MAS2 (MAS2_EPN(0xC3F00000) | MAS2_I)
|
||||
#define TLB2_MAS3 (MAS3_RPN(0xC3F00000) | \
|
||||
MAS3_UW | MAS3_SW | MAS3_UR | MAS3_SR)
|
||||
|
||||
#define TLB3_MAS0 (MAS0_TBLMAS_TBL | MAS0_ESEL(3))
|
||||
#define TLB3_MAS1 (MAS1_VALID | MAS1_IPROT | MAS1_TSISE_1M)
|
||||
#define TLB3_MAS2 (MAS2_EPN(0xFFE00000) | MAS2_I)
|
||||
#define TLB3_MAS3 (MAS3_RPN(0xFFE00000) | \
|
||||
MAS3_UW | MAS3_SW | MAS3_UR | MAS3_SR)
|
||||
|
||||
#define TLB4_MAS0 (MAS0_TBLMAS_TBL | MAS0_ESEL(4))
|
||||
#define TLB4_MAS1 (MAS1_VALID | MAS1_IPROT | MAS1_TSISE_1M)
|
||||
#define TLB4_MAS2 (MAS2_EPN(0x8FF00000) | MAS2_I)
|
||||
#define TLB4_MAS3 (MAS3_RPN(0x8FF00000) | \
|
||||
MAS3_UW | MAS3_SW | MAS3_UR | MAS3_SR)
|
||||
|
||||
#define TLB5_MAS0 (MAS0_TBLMAS_TBL | MAS0_ESEL(5))
|
||||
#define TLB5_MAS1 (MAS1_VALID | MAS1_IPROT | MAS1_TSISE_1M)
|
||||
#define TLB5_MAS2 (MAS2_EPN(0xFFF00000) | MAS2_I)
|
||||
#define TLB5_MAS3 (MAS3_RPN(0xFFF00000) | \
|
||||
MAS3_UW | MAS3_SW | MAS3_UR | MAS3_SR)
|
||||
|
||||
/*
|
||||
* BUCSR default settings.
|
||||
*/
|
||||
#if !defined(BOOT_BUCSR_DEFAULT) || defined(__DOXYGEN__)
|
||||
#define BOOT_BUCSR_DEFAULT (BUCSR_BPEN | BUCSR_BPRED_0 | \
|
||||
BUCSR_BALLOC_0 | BUCSR_BALLOC_BFI)
|
||||
#endif
|
||||
|
||||
/*
|
||||
* LICSR1 default settings.
|
||||
*/
|
||||
#if !defined(BOOT_LICSR1_DEFAULT) || defined(__DOXYGEN__)
|
||||
#define BOOT_LICSR1_DEFAULT (LICSR1_ICE | LICSR1_ICORG)
|
||||
#endif
|
||||
|
||||
/*
|
||||
* MSR default settings.
|
||||
*/
|
||||
#if !defined(BOOT_MSR_DEFAULT) || defined(__DOXYGEN__)
|
||||
#define BOOT_MSR_DEFAULT (MSR_SPE | MSR_WE | MSR_CE | MSR_ME)
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Boot default settings.
|
||||
*/
|
||||
#if !defined(BOOT_PERFORM_CORE_INIT) || defined(__DOXYGEN__)
|
||||
#define BOOT_PERFORM_CORE_INIT 1
|
||||
#endif
|
||||
|
||||
/*
|
||||
* VLE mode default settings.
|
||||
*/
|
||||
#if !defined(BOOT_USE_VLE) || defined(__DOXYGEN__)
|
||||
#define BOOT_USE_VLE 1
|
||||
#endif
|
||||
|
||||
/*
|
||||
* RAM relocation flag.
|
||||
*/
|
||||
#if !defined(BOOT_RELOCATE_IN_RAM) || defined(__DOXYGEN__)
|
||||
#define BOOT_RELOCATE_IN_RAM 0
|
||||
#endif
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Derived constants and error checks. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Module data structures and types. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Module macros. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* External declarations. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Module inline functions. */
|
||||
/*===========================================================================*/
|
||||
|
||||
#endif /* _BOOT_H_ */
|
||||
|
||||
/** @} */
|
||||
|
|
@ -1,405 +0,0 @@
|
|||
/*
|
||||
ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
|
||||
|
||||
Licensed under the Apache License, Version 2.0 (the "License");
|
||||
you may not use this file except in compliance with the License.
|
||||
You may obtain a copy of the License at
|
||||
|
||||
http://www.apache.org/licenses/LICENSE-2.0
|
||||
|
||||
Unless required by applicable law or agreed to in writing, software
|
||||
distributed under the License is distributed on an "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
See the License for the specific language governing permissions and
|
||||
limitations under the License.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file SPC56ELxx/boot.s
|
||||
* @brief SPC56ELxx boot-related code.
|
||||
*
|
||||
* @addtogroup PPC_BOOT
|
||||
* @{
|
||||
*/
|
||||
|
||||
#include "boot.h"
|
||||
|
||||
#if !defined(__DOXYGEN__)
|
||||
|
||||
/* BAM record.*/
|
||||
.section .boot, "ax"
|
||||
|
||||
#if BOOT_USE_VLE
|
||||
.long 0x015A0000
|
||||
#else
|
||||
.long 0x005A0000
|
||||
#endif
|
||||
.long _reset_address
|
||||
|
||||
.align 2
|
||||
.globl _reset_address
|
||||
.type _reset_address, @function
|
||||
_reset_address:
|
||||
bl _coreinit
|
||||
bl _ivinit
|
||||
|
||||
#if BOOT_RELOCATE_IN_RAM
|
||||
/*
|
||||
* Image relocation in RAM.
|
||||
*/
|
||||
lis %r4, __ram_reloc_start__@h
|
||||
ori %r4, %r4, __ram_reloc_start__@l
|
||||
lis %r5, __ram_reloc_dest__@h
|
||||
ori %r5, %r5, __ram_reloc_dest__@l
|
||||
lis %r6, __ram_reloc_end__@h
|
||||
ori %r6, %r6, __ram_reloc_end__@l
|
||||
.relloop:
|
||||
cmpl cr0, %r4, %r6
|
||||
bge cr0, .relend
|
||||
lwz %r7, 0(%r4)
|
||||
addi %r4, %r4, 4
|
||||
stw %r7, 0(%r5)
|
||||
addi %r5, %r5, 4
|
||||
b .relloop
|
||||
.relend:
|
||||
lis %r3, _boot_address@h
|
||||
ori %r3, %r3, _boot_address@l
|
||||
mtctr %r3
|
||||
bctrl
|
||||
#else
|
||||
b _boot_address
|
||||
#endif
|
||||
|
||||
#if BOOT_PERFORM_CORE_INIT
|
||||
.align 2
|
||||
_ramcode:
|
||||
tlbwe
|
||||
isync
|
||||
blr
|
||||
#endif /* BOOT_PERFORM_CORE_INIT */
|
||||
|
||||
.align 2
|
||||
_coreinit:
|
||||
#if BOOT_PERFORM_CORE_INIT
|
||||
/*
|
||||
* Invalidating all TLBs except TLB0.
|
||||
*/
|
||||
lis %r3, 0
|
||||
mtspr 625, %r3 /* MAS1 */
|
||||
mtspr 626, %r3 /* MAS2 */
|
||||
mtspr 627, %r3 /* MAS3 */
|
||||
lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(1))@h
|
||||
mtspr 624, %r3 /* MAS0 */
|
||||
tlbwe
|
||||
lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(2))@h
|
||||
mtspr 624, %r3 /* MAS0 */
|
||||
tlbwe
|
||||
lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(3))@h
|
||||
mtspr 624, %r3 /* MAS0 */
|
||||
tlbwe
|
||||
lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(4))@h
|
||||
mtspr 624, %r3 /* MAS0 */
|
||||
tlbwe
|
||||
lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(5))@h
|
||||
mtspr 624, %r3 /* MAS0 */
|
||||
tlbwe
|
||||
lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(6))@h
|
||||
mtspr 624, %r3 /* MAS0 */
|
||||
tlbwe
|
||||
lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(7))@h
|
||||
mtspr 624, %r3 /* MAS0 */
|
||||
tlbwe
|
||||
lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(8))@h
|
||||
mtspr 624, %r3 /* MAS0 */
|
||||
tlbwe
|
||||
lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(9))@h
|
||||
mtspr 624, %r3 /* MAS0 */
|
||||
tlbwe
|
||||
lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(10))@h
|
||||
mtspr 624, %r3 /* MAS0 */
|
||||
tlbwe
|
||||
lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(11))@h
|
||||
mtspr 624, %r3 /* MAS0 */
|
||||
tlbwe
|
||||
lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(12))@h
|
||||
mtspr 624, %r3 /* MAS0 */
|
||||
tlbwe
|
||||
lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(13))@h
|
||||
mtspr 624, %r3 /* MAS0 */
|
||||
tlbwe
|
||||
lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(14))@h
|
||||
mtspr 624, %r3 /* MAS0 */
|
||||
tlbwe
|
||||
lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(15))@h
|
||||
mtspr 624, %r3 /* MAS0 */
|
||||
tlbwe
|
||||
|
||||
/*
|
||||
* TLB1 allocated to internal RAM.
|
||||
*/
|
||||
lis %r3, TLB1_MAS0@h
|
||||
mtspr 624, %r3 /* MAS0 */
|
||||
lis %r3, TLB1_MAS1@h
|
||||
ori %r3, %r3, TLB1_MAS1@l
|
||||
mtspr 625, %r3 /* MAS1 */
|
||||
lis %r3, TLB1_MAS2@h
|
||||
ori %r3, %r3, TLB1_MAS2@l
|
||||
mtspr 626, %r3 /* MAS2 */
|
||||
lis %r3, TLB1_MAS3@h
|
||||
ori %r3, %r3, TLB1_MAS3@l
|
||||
mtspr 627, %r3 /* MAS3 */
|
||||
tlbwe
|
||||
|
||||
/*
|
||||
* TLB2 allocated to internal Peripherals Bridge A.
|
||||
*/
|
||||
lis %r3, TLB2_MAS0@h
|
||||
mtspr 624, %r3 /* MAS0 */
|
||||
lis %r3, TLB2_MAS1@h
|
||||
ori %r3, %r3, TLB2_MAS1@l
|
||||
mtspr 625, %r3 /* MAS1 */
|
||||
lis %r3, TLB2_MAS2@h
|
||||
ori %r3, %r3, TLB2_MAS2@l
|
||||
mtspr 626, %r3 /* MAS2 */
|
||||
lis %r3, TLB2_MAS3@h
|
||||
ori %r3, %r3, TLB2_MAS3@l
|
||||
mtspr 627, %r3 /* MAS3 */
|
||||
tlbwe
|
||||
|
||||
/*
|
||||
* TLB3 allocated to internal Peripherals Bridge B.
|
||||
*/
|
||||
lis %r3, TLB3_MAS0@h
|
||||
mtspr 624, %r3 /* MAS0 */
|
||||
lis %r3, TLB3_MAS1@h
|
||||
ori %r3, %r3, TLB3_MAS1@l
|
||||
mtspr 625, %r3 /* MAS1 */
|
||||
lis %r3, TLB3_MAS2@h
|
||||
ori %r3, %r3, TLB3_MAS2@l
|
||||
mtspr 626, %r3 /* MAS2 */
|
||||
lis %r3, TLB3_MAS3@h
|
||||
ori %r3, %r3, TLB3_MAS3@l
|
||||
mtspr 627, %r3 /* MAS3 */
|
||||
tlbwe
|
||||
|
||||
/*
|
||||
* TLB4 allocated to on-platform peripherals.
|
||||
*/
|
||||
lis %r3, TLB4_MAS0@h
|
||||
mtspr 624, %r3 /* MAS0 */
|
||||
lis %r3, TLB4_MAS1@h
|
||||
ori %r3, %r3, TLB4_MAS1@l
|
||||
mtspr 625, %r3 /* MAS1 */
|
||||
lis %r3, TLB4_MAS2@h
|
||||
ori %r3, %r3, TLB4_MAS2@l
|
||||
mtspr 626, %r3 /* MAS2 */
|
||||
lis %r3, TLB4_MAS3@h
|
||||
ori %r3, %r3, TLB4_MAS3@l
|
||||
mtspr 627, %r3 /* MAS3 */
|
||||
tlbwe
|
||||
|
||||
/*
|
||||
* TLB5 allocated to on-platform peripherals.
|
||||
*/
|
||||
lis %r3, TLB5_MAS0@h
|
||||
mtspr 624, %r3 /* MAS0 */
|
||||
lis %r3, TLB5_MAS1@h
|
||||
ori %r3, %r3, TLB5_MAS1@l
|
||||
mtspr 625, %r3 /* MAS1 */
|
||||
lis %r3, TLB5_MAS2@h
|
||||
ori %r3, %r3, TLB5_MAS2@l
|
||||
mtspr 626, %r3 /* MAS2 */
|
||||
lis %r3, TLB5_MAS3@h
|
||||
ori %r3, %r3, TLB5_MAS3@l
|
||||
mtspr 627, %r3 /* MAS3 */
|
||||
tlbwe
|
||||
|
||||
/*
|
||||
* RAM clearing, this device requires a write to all RAM location in
|
||||
* order to initialize the ECC detection hardware, this is going to
|
||||
* slow down the startup but there is no way around.
|
||||
*/
|
||||
xor %r0, %r0, %r0
|
||||
xor %r1, %r1, %r1
|
||||
xor %r2, %r2, %r2
|
||||
xor %r3, %r3, %r3
|
||||
xor %r4, %r4, %r4
|
||||
xor %r5, %r5, %r5
|
||||
xor %r6, %r6, %r6
|
||||
xor %r7, %r7, %r7
|
||||
xor %r8, %r8, %r8
|
||||
xor %r9, %r9, %r9
|
||||
xor %r10, %r10, %r10
|
||||
xor %r11, %r11, %r11
|
||||
xor %r12, %r12, %r12
|
||||
xor %r13, %r13, %r13
|
||||
xor %r14, %r14, %r14
|
||||
xor %r15, %r15, %r15
|
||||
xor %r16, %r16, %r16
|
||||
xor %r17, %r17, %r17
|
||||
xor %r18, %r18, %r18
|
||||
xor %r19, %r19, %r19
|
||||
xor %r20, %r20, %r20
|
||||
xor %r21, %r21, %r21
|
||||
xor %r22, %r22, %r22
|
||||
xor %r23, %r23, %r23
|
||||
xor %r24, %r24, %r24
|
||||
xor %r25, %r25, %r25
|
||||
xor %r26, %r26, %r26
|
||||
xor %r27, %r27, %r27
|
||||
xor %r28, %r28, %r28
|
||||
xor %r29, %r29, %r29
|
||||
xor %r30, %r30, %r30
|
||||
xor %r31, %r31, %r31
|
||||
lis %r4, __ram_start__@h
|
||||
ori %r4, %r4, __ram_start__@l
|
||||
lis %r5, __ram_end__@h
|
||||
ori %r5, %r5, __ram_end__@l
|
||||
.cleareccloop:
|
||||
cmpl %cr0, %r4, %r5
|
||||
bge %cr0, .cleareccend
|
||||
stmw %r16, 0(%r4)
|
||||
addi %r4, %r4, 64
|
||||
b .cleareccloop
|
||||
.cleareccend:
|
||||
#endif /* BOOT_PERFORM_CORE_INIT */
|
||||
|
||||
/*
|
||||
* Special function registers clearing, required in order to avoid
|
||||
* possible problems with lockstep mode.
|
||||
*/
|
||||
mtcrf 0xFF, %r31
|
||||
mtspr 9, %r31 /* CTR */
|
||||
mtspr 22, %r31 /* DEC */
|
||||
mtspr 26, %r31 /* SRR0-1 */
|
||||
mtspr 27, %r31
|
||||
mtspr 54, %r31 /* DECAR */
|
||||
mtspr 58, %r31 /* CSRR0-1 */
|
||||
mtspr 59, %r31
|
||||
mtspr 61, %r31 /* DEAR */
|
||||
mtspr 256, %r31 /* USPRG0 */
|
||||
mtspr 272, %r31 /* SPRG1-7 */
|
||||
mtspr 273, %r31
|
||||
mtspr 274, %r31
|
||||
mtspr 275, %r31
|
||||
mtspr 276, %r31
|
||||
mtspr 277, %r31
|
||||
mtspr 278, %r31
|
||||
mtspr 279, %r31
|
||||
mtspr 285, %r31 /* TBU */
|
||||
mtspr 284, %r31 /* TBL */
|
||||
#if 0
|
||||
mtspr 318, %r31 /* DVC1-2 */
|
||||
mtspr 319, %r31
|
||||
#endif
|
||||
mtspr 562, %r31 /* DBCNT */
|
||||
mtspr 570, %r31 /* MCSRR0 */
|
||||
mtspr 571, %r31 /* MCSRR1 */
|
||||
mtspr 604, %r31 /* SPRG8-9 */
|
||||
mtspr 605, %r31
|
||||
|
||||
#if BOOT_PERFORM_CORE_INIT
|
||||
/*
|
||||
* *Finally* the TLB0 is re-allocated to flash, note, the final phase
|
||||
* is executed from RAM.
|
||||
*/
|
||||
lis %r3, TLB0_MAS0@h
|
||||
mtspr 624, %r3 /* MAS0 */
|
||||
lis %r3, TLB0_MAS1@h
|
||||
ori %r3, %r3, TLB0_MAS1@l
|
||||
mtspr 625, %r3 /* MAS1 */
|
||||
lis %r3, TLB0_MAS2@h
|
||||
ori %r3, %r3, TLB0_MAS2@l
|
||||
mtspr 626, %r3 /* MAS2 */
|
||||
lis %r3, TLB0_MAS3@h
|
||||
ori %r3, %r3, TLB0_MAS3@l
|
||||
mtspr 627, %r3 /* MAS3 */
|
||||
mflr %r4
|
||||
lis %r6, _ramcode@h
|
||||
ori %r6, %r6, _ramcode@l
|
||||
lis %r7, 0x40010000@h
|
||||
mtctr %r7
|
||||
lwz %r3, 0(%r6)
|
||||
stw %r3, 0(%r7)
|
||||
lwz %r3, 4(%r6)
|
||||
stw %r3, 4(%r7)
|
||||
lwz %r3, 8(%r6)
|
||||
stw %r3, 8(%r7)
|
||||
bctrl
|
||||
mtlr %r4
|
||||
#endif /* BOOT_PERFORM_CORE_INIT */
|
||||
|
||||
/*
|
||||
* Branch prediction enabled.
|
||||
*/
|
||||
li %r3, BOOT_BUCSR_DEFAULT
|
||||
mtspr 1013, %r3 /* BUCSR */
|
||||
|
||||
/*
|
||||
* Cache invalidated and then enabled.
|
||||
*/
|
||||
li %r3, LICSR1_ICINV
|
||||
mtspr 1011, %r3 /* LICSR1 */
|
||||
.inv: mfspr %r3, 1011 /* LICSR1 */
|
||||
andi. %r3, %r3, LICSR1_ICINV
|
||||
bne .inv
|
||||
lis %r3, BOOT_LICSR1_DEFAULT@h
|
||||
ori %r3, %r3, BOOT_LICSR1_DEFAULT@l
|
||||
mtspr 1011, %r3 /* LICSR1 */
|
||||
|
||||
blr
|
||||
|
||||
/*
|
||||
* Exception vectors initialization.
|
||||
*/
|
||||
.align 2
|
||||
_ivinit:
|
||||
/* MSR initialization.*/
|
||||
lis %r3, BOOT_MSR_DEFAULT@h
|
||||
ori %r3, %r3, BOOT_MSR_DEFAULT@l
|
||||
mtMSR %r3
|
||||
|
||||
/* IVPR initialization.*/
|
||||
lis %r3, __ivpr_base__@h
|
||||
ori %r3, %r3, __ivpr_base__@l
|
||||
mtIVPR %r3
|
||||
|
||||
/* IVORs initialization.*/
|
||||
lis %r3, _unhandled_exception@h
|
||||
ori %r3, %r3, _unhandled_exception@l
|
||||
|
||||
mtspr 400, %r3 /* IVOR0-15 */
|
||||
mtspr 401, %r3
|
||||
mtspr 402, %r3
|
||||
mtspr 403, %r3
|
||||
mtspr 404, %r3
|
||||
mtspr 405, %r3
|
||||
mtspr 406, %r3
|
||||
mtspr 407, %r3
|
||||
mtspr 408, %r3
|
||||
mtspr 409, %r3
|
||||
mtspr 410, %r3
|
||||
mtspr 411, %r3
|
||||
mtspr 412, %r3
|
||||
mtspr 413, %r3
|
||||
mtspr 414, %r3
|
||||
mtspr 415, %r3
|
||||
mtspr 528, %r3 /* IVOR32-34 */
|
||||
mtspr 529, %r3
|
||||
mtspr 530, %r3
|
||||
|
||||
blr
|
||||
|
||||
.section .handlers, "ax"
|
||||
|
||||
/*
|
||||
* Unhandled exceptions handler.
|
||||
*/
|
||||
.weak _unhandled_exception
|
||||
.type _unhandled_exception, @function
|
||||
_unhandled_exception:
|
||||
b _unhandled_exception
|
||||
|
||||
#endif /* !defined(__DOXYGEN__) */
|
||||
|
||||
/** @} */
|
||||
|
|
@ -1,93 +0,0 @@
|
|||
/*
|
||||
ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
|
||||
|
||||
Licensed under the Apache License, Version 2.0 (the "License");
|
||||
you may not use this file except in compliance with the License.
|
||||
You may obtain a copy of the License at
|
||||
|
||||
http://www.apache.org/licenses/LICENSE-2.0
|
||||
|
||||
Unless required by applicable law or agreed to in writing, software
|
||||
distributed under the License is distributed on an "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
See the License for the specific language governing permissions and
|
||||
limitations under the License.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file SPC56ELxx/intc.h
|
||||
* @brief SPC56ELxx INTC module header.
|
||||
*
|
||||
* @addtogroup INTC
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifndef _INTC_H_
|
||||
#define _INTC_H_
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Module constants. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @name INTC addresses
|
||||
* @{
|
||||
*/
|
||||
#define INTC_BASE 0xFFF48000
|
||||
#define INTC_IACKR_ADDR (INTC_BASE + 0x10)
|
||||
#define INTC_EOIR_ADDR (INTC_BASE + 0x18)
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @brief INTC priority levels.
|
||||
*/
|
||||
#define INTC_PRIORITY_LEVELS 16U
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Module pre-compile time settings. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Derived constants and error checks. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Module data structures and types. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Module macros. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @name INTC-related macros
|
||||
* @{
|
||||
*/
|
||||
#define INTC_BCR (*((volatile uint32_t *)(INTC_BASE + 0)))
|
||||
#define INTC_CPR(n) (*((volatile uint32_t *)(INTC_BASE + 8 + ((n) * sizeof (uint32_t)))))
|
||||
#define INTC_IACKR(n) (*((volatile uint32_t *)(INTC_BASE + 0x10 + ((n) * sizeof (uint32_t)))))
|
||||
#define INTC_EOIR(n) (*((volatile uint32_t *)(INTC_BASE + 0x18 + ((n) * sizeof (uint32_t)))))
|
||||
#define INTC_PSR(n) (*((volatile uint8_t *)(INTC_BASE + 0x40 + ((n) * sizeof (uint8_t)))))
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @brief Core selection macros for PSR register.
|
||||
*/
|
||||
#define INTC_PSR_CORE0 0x00
|
||||
|
||||
/**
|
||||
* @brief PSR register content helper
|
||||
*/
|
||||
#define INTC_PSR_ENABLE(cores, prio) ((uint32_t)(cores) | (uint32_t)(prio))
|
||||
|
||||
/*===========================================================================*/
|
||||
/* External declarations. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Module inline functions. */
|
||||
/*===========================================================================*/
|
||||
|
||||
#endif /* _INTC_H_ */
|
||||
|
||||
/** @} */
|
||||
|
|
@ -1,83 +0,0 @@
|
|||
/*
|
||||
ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
|
||||
|
||||
Licensed under the Apache License, Version 2.0 (the "License");
|
||||
you may not use this file except in compliance with the License.
|
||||
You may obtain a copy of the License at
|
||||
|
||||
http://www.apache.org/licenses/LICENSE-2.0
|
||||
|
||||
Unless required by applicable law or agreed to in writing, software
|
||||
distributed under the License is distributed on an "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
See the License for the specific language governing permissions and
|
||||
limitations under the License.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file SPC56ELxx/ppcparams.h
|
||||
* @brief PowerPC parameters for the SPC56ELxx.
|
||||
*
|
||||
* @defgroup PPC_SPC56ELxx SPC56ELxx Specific Parameters
|
||||
* @ingroup PPC_SPECIFIC
|
||||
* @details This file contains the PowerPC specific parameters for the
|
||||
* SPC56ELxx platform.
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifndef _PPCPARAMS_H_
|
||||
#define _PPCPARAMS_H_
|
||||
|
||||
/**
|
||||
* @brief Family identification macro.
|
||||
*/
|
||||
#define PPC_SPC56ELxx
|
||||
|
||||
/**
|
||||
* @brief PPC core model.
|
||||
*/
|
||||
#define PPC_VARIANT PPC_VARIANT_e200z4
|
||||
|
||||
/**
|
||||
* @brief Number of cores.
|
||||
*/
|
||||
#define PPC_CORE_NUMBER 1
|
||||
|
||||
/**
|
||||
* @brief Number of writable bits in IVPR register.
|
||||
*/
|
||||
#define PPC_IVPR_BITS 16
|
||||
|
||||
/**
|
||||
* @brief IVORx registers support.
|
||||
*/
|
||||
#define PPC_SUPPORTS_IVORS TRUE
|
||||
|
||||
/**
|
||||
* @brief Book E instruction set support.
|
||||
*/
|
||||
#define PPC_SUPPORTS_BOOKE TRUE
|
||||
|
||||
/**
|
||||
* @brief VLE instruction set support.
|
||||
*/
|
||||
#define PPC_SUPPORTS_VLE TRUE
|
||||
|
||||
/**
|
||||
* @brief Supports VLS Load/Store Multiple Volatile instructions.
|
||||
*/
|
||||
#define PPC_SUPPORTS_VLE_MULTI TRUE
|
||||
|
||||
/**
|
||||
* @brief Supports the decrementer timer.
|
||||
*/
|
||||
#define PPC_SUPPORTS_DECREMENTER TRUE
|
||||
|
||||
/**
|
||||
* @brief Number of interrupt sources.
|
||||
*/
|
||||
#define PPC_NUM_VECTORS 256
|
||||
|
||||
#endif /* _PPCPARAMS_H_ */
|
||||
|
||||
/** @} */
|
||||
|
|
@ -1,93 +0,0 @@
|
|||
/*
|
||||
ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
|
||||
|
||||
Licensed under the Apache License, Version 2.0 (the "License");
|
||||
you may not use this file except in compliance with the License.
|
||||
You may obtain a copy of the License at
|
||||
|
||||
http://www.apache.org/licenses/LICENSE-2.0
|
||||
|
||||
Unless required by applicable law or agreed to in writing, software
|
||||
distributed under the License is distributed on an "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
See the License for the specific language governing permissions and
|
||||
limitations under the License.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file boot.h
|
||||
* @brief Boot parameters for the SPC57EMxx_HSM.
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifndef _BOOT_H_
|
||||
#define _BOOT_H_
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Module constants. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @name BUCSR registers definitions
|
||||
* @{
|
||||
*/
|
||||
#define BUCSR_BPEN 0x00000001
|
||||
#define BUCSR_BALLOC_BFI 0x00000200
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @name MSR register definitions
|
||||
* @{
|
||||
*/
|
||||
#define MSR_WE 0x00040000
|
||||
#define MSR_CE 0x00020000
|
||||
#define MSR_EE 0x00008000
|
||||
#define MSR_PR 0x00004000
|
||||
#define MSR_ME 0x00001000
|
||||
#define MSR_DE 0x00000200
|
||||
#define MSR_IS 0x00000020
|
||||
#define MSR_DS 0x00000010
|
||||
#define MSR_RI 0x00000002
|
||||
/** @} */
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Module pre-compile time settings. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*
|
||||
* BUCSR default settings.
|
||||
*/
|
||||
#if !defined(BOOT_BUCSR_DEFAULT) || defined(__DOXYGEN__)
|
||||
#define BOOT_BUCSR_DEFAULT (BUCSR_BPEN | BUCSR_BALLOC_BFI)
|
||||
#endif
|
||||
|
||||
/*
|
||||
* MSR default settings.
|
||||
*/
|
||||
#if !defined(BOOT_MSR_DEFAULT) || defined(__DOXYGEN__)
|
||||
#define BOOT_MSR_DEFAULT (MSR_WE | MSR_CE | MSR_ME)
|
||||
#endif
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Derived constants and error checks. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Module data structures and types. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Module macros. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* External declarations. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Module inline functions. */
|
||||
/*===========================================================================*/
|
||||
|
||||
#endif /* _BOOT_H_ */
|
||||
|
||||
/** @} */
|
||||
|
|
@ -1,208 +0,0 @@
|
|||
/*
|
||||
ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
|
||||
|
||||
Licensed under the Apache License, Version 2.0 (the "License");
|
||||
you may not use this file except in compliance with the License.
|
||||
You may obtain a copy of the License at
|
||||
|
||||
http://www.apache.org/licenses/LICENSE-2.0
|
||||
|
||||
Unless required by applicable law or agreed to in writing, software
|
||||
distributed under the License is distributed on an "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
See the License for the specific language governing permissions and
|
||||
limitations under the License.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file SPC57EMxx_HSM/boot.s
|
||||
* @brief SPC57EMxx_HSM boot-related code.
|
||||
*
|
||||
* @addtogroup PPC_BOOT
|
||||
* @{
|
||||
*/
|
||||
|
||||
#include "boot.h"
|
||||
|
||||
#define HSBI_CCR 0xA3F14004
|
||||
#define HSBI_CCR_CE 0x00000001
|
||||
#define HSBI_CCR_INV 0x00000002
|
||||
|
||||
#if !defined(__DOXYGEN__)
|
||||
|
||||
/* Boot record.*/
|
||||
.section .boot, "ax"
|
||||
|
||||
.long 0xFFFF0000
|
||||
.long 0xFFFF0000
|
||||
.long 0xFFFFFFFF
|
||||
.long _reset_address
|
||||
.long 0xFFFFFFFF
|
||||
.long 0xFFFFFFFF
|
||||
.long 0xFFFFFFFF
|
||||
.long 0xFFFFFFFF
|
||||
|
||||
.align 2
|
||||
.globl _reset_address
|
||||
.type _reset_address, @function
|
||||
_reset_address:
|
||||
bl _coreinit
|
||||
bl _ivinit
|
||||
b _boot_address
|
||||
|
||||
.align 2
|
||||
_coreinit:
|
||||
#if 0
|
||||
/*
|
||||
* Cache invalidate and enable.
|
||||
*/
|
||||
lis %r7, HSBI_CCR@h
|
||||
ori %r7, %r7, HSBI_CCR@l
|
||||
li %r0, HSBI_CCR_INV | HSBI_CCR_CE
|
||||
stw %r0, 0(%r7)
|
||||
.inv:
|
||||
lwz %r0, 0(%r7)
|
||||
andi. %r0, %r0, HSBI_CCR_INV
|
||||
bne+ %cr0, .inv
|
||||
#endif
|
||||
|
||||
/*
|
||||
* RAM clearing, this device requires a write to all RAM location in
|
||||
* order to initialize the ECC detection hardware, this is going to
|
||||
* slow down the startup but there is no way around.
|
||||
*/
|
||||
xor %r0, %r0, %r0
|
||||
xor %r1, %r1, %r1
|
||||
xor %r2, %r2, %r2
|
||||
xor %r3, %r3, %r3
|
||||
xor %r4, %r4, %r4
|
||||
xor %r5, %r5, %r5
|
||||
xor %r6, %r6, %r6
|
||||
xor %r7, %r7, %r7
|
||||
xor %r8, %r8, %r8
|
||||
xor %r9, %r9, %r9
|
||||
xor %r10, %r10, %r10
|
||||
xor %r11, %r11, %r11
|
||||
xor %r12, %r12, %r12
|
||||
xor %r13, %r13, %r13
|
||||
xor %r14, %r14, %r14
|
||||
xor %r15, %r15, %r15
|
||||
xor %r16, %r16, %r16
|
||||
xor %r17, %r17, %r17
|
||||
xor %r18, %r18, %r18
|
||||
xor %r19, %r19, %r19
|
||||
xor %r20, %r20, %r20
|
||||
xor %r21, %r21, %r21
|
||||
xor %r22, %r22, %r22
|
||||
xor %r23, %r23, %r23
|
||||
xor %r24, %r24, %r24
|
||||
xor %r25, %r25, %r25
|
||||
xor %r26, %r26, %r26
|
||||
xor %r27, %r27, %r27
|
||||
xor %r28, %r28, %r28
|
||||
xor %r29, %r29, %r29
|
||||
xor %r30, %r30, %r30
|
||||
xor %r31, %r31, %r31
|
||||
lis %r4, __ram_start__@h
|
||||
ori %r4, %r4, __ram_start__@l
|
||||
lis %r5, __ram_end__@h
|
||||
ori %r5, %r5, __ram_end__@l
|
||||
.cleareccloop:
|
||||
cmpl %cr0, %r4, %r5
|
||||
bge %cr0, .cleareccend
|
||||
stmw %r16, 0(%r4)
|
||||
addi %r4, %r4, 64
|
||||
b .cleareccloop
|
||||
.cleareccend:
|
||||
|
||||
/*
|
||||
* Branch prediction enabled.
|
||||
*/
|
||||
li %r3, BUCSR_DEFAULT
|
||||
mtspr 1013, %r3 /* BUCSR */
|
||||
|
||||
blr
|
||||
|
||||
/*
|
||||
* Exception vectors initialization.
|
||||
*/
|
||||
.align 2
|
||||
_ivinit:
|
||||
/* MSR initialization.*/
|
||||
lis %r3, MSR_DEFAULT@h
|
||||
ori %r3, %r3, MSR_DEFAULT@l
|
||||
mtMSR %r3
|
||||
|
||||
/* IVPR initialization.*/
|
||||
lis %r3, __ivpr_base__@h
|
||||
ori %r3, %r3, __ivpr_base__@l
|
||||
mtIVPR %r3
|
||||
|
||||
blr
|
||||
|
||||
.section .ivors, "ax"
|
||||
|
||||
.globl IVORS
|
||||
IVORS:
|
||||
IVOR0: b _IVOR0
|
||||
.align 4
|
||||
IVOR1: b _IVOR1
|
||||
.align 4
|
||||
IVOR2: b _IVOR2
|
||||
.align 4
|
||||
IVOR3: b _IVOR3
|
||||
.align 4
|
||||
IVOR4: b _IVOR4
|
||||
.align 4
|
||||
IVOR5: b _IVOR5
|
||||
.align 4
|
||||
IVOR6: b _IVOR6
|
||||
.align 4
|
||||
IVOR7: b _IVOR7
|
||||
.align 4
|
||||
IVOR8: b _IVOR8
|
||||
.align 4
|
||||
IVOR9: b _IVOR9
|
||||
.align 4
|
||||
IVOR10: b _IVOR10
|
||||
.align 4
|
||||
IVOR11: b _IVOR11
|
||||
.align 4
|
||||
IVOR12: b _IVOR12
|
||||
.align 4
|
||||
IVOR13: b _IVOR13
|
||||
.align 4
|
||||
IVOR14: b _IVOR14
|
||||
.align 4
|
||||
IVOR15: b _IVOR15
|
||||
|
||||
.section .handlers, "ax"
|
||||
|
||||
/*
|
||||
* Default IVOR handlers.
|
||||
*/
|
||||
.align 2
|
||||
.weak _IVOR0, _IVOR1, _IVOR2, _IVOR3, _IVOR4, _IVOR5
|
||||
.weak _IVOR6, _IVOR7, _IVOR8, _IVOR9, _IVOR10, _IVOR11
|
||||
.weak _IVOR12, _IVOR13, _IVOR14, _IVOR15
|
||||
_IVOR0:
|
||||
_IVOR1:
|
||||
_IVOR2:
|
||||
_IVOR3:
|
||||
_IVOR5:
|
||||
_IVOR6:
|
||||
_IVOR7:
|
||||
_IVOR8:
|
||||
_IVOR9:
|
||||
_IVOR11:
|
||||
_IVOR12:
|
||||
_IVOR13:
|
||||
_IVOR14:
|
||||
_IVOR15:
|
||||
.global _unhandled_exception
|
||||
_unhandled_exception:
|
||||
b _unhandled_exception
|
||||
|
||||
#endif /* !defined(__DOXYGEN__) */
|
||||
|
||||
/** @} */
|
||||
|
|
@ -1,94 +0,0 @@
|
|||
/*
|
||||
ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
|
||||
|
||||
Licensed under the Apache License, Version 2.0 (the "License");
|
||||
you may not use this file except in compliance with the License.
|
||||
You may obtain a copy of the License at
|
||||
|
||||
http://www.apache.org/licenses/LICENSE-2.0
|
||||
|
||||
Unless required by applicable law or agreed to in writing, software
|
||||
distributed under the License is distributed on an "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
See the License for the specific language governing permissions and
|
||||
limitations under the License.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file SPC57EMxx_HSM/intc.h
|
||||
* @brief SPC57EMxx_HSM INTC module header.
|
||||
*
|
||||
* @addtogroup INTC
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifndef _INTC_H_
|
||||
#define _INTC_H_
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Module constants. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @name INTC addresses
|
||||
* @{
|
||||
*/
|
||||
#define INTC_BASE 0xA3F48000
|
||||
#define INTC_IACKR_ADDR (INTC_BASE + 0x20)
|
||||
#define INTC_EOIR_ADDR (INTC_BASE + 0x30)
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @brief INTC priority levels.
|
||||
*/
|
||||
#define INTC_PRIORITY_LEVELS 16U
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Module pre-compile time settings. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Derived constants and error checks. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Module data structures and types. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Module macros. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @name INTC-related macros
|
||||
* @{
|
||||
*/
|
||||
#define INTC_BCR (*((volatile uint32_t *)(INTC_BASE + 0)))
|
||||
#define INTC_MPROT (*((volatile uint32_t *)(INTC_BASE + 4)))
|
||||
#define INTC_CPR(n) (*((volatile uint32_t *)(INTC_BASE + 0x10 + ((n) * sizeof (uint32_t)))))
|
||||
#define INTC_IACKR(n) (*((volatile uint32_t *)(INTC_BASE + 0x20 + ((n) * sizeof (uint32_t)))))
|
||||
#define INTC_EOIR(n) (*((volatile uint32_t *)(INTC_BASE + 0x30 + ((n) * sizeof (uint32_t)))))
|
||||
#define INTC_PSR(n) (*((volatile uint16_t *)(INTC_BASE + 0x60 + ((n) * sizeof (uint16_t)))))
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @brief Core selection macros for PSR register.
|
||||
*/
|
||||
#define INTC_PSR_CORE4 0x8000
|
||||
|
||||
/**
|
||||
* @brief PSR register content helper
|
||||
*/
|
||||
#define INTC_PSR_ENABLE(cores, prio) ((uint32_t)(cores) | (uint32_t)(prio))
|
||||
|
||||
/*===========================================================================*/
|
||||
/* External declarations. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Module inline functions. */
|
||||
/*===========================================================================*/
|
||||
|
||||
#endif /* _INTC_H_ */
|
||||
|
||||
/** @} */
|
||||
|
|
@ -1,88 +0,0 @@
|
|||
/*
|
||||
ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
|
||||
|
||||
Licensed under the Apache License, Version 2.0 (the "License");
|
||||
you may not use this file except in compliance with the License.
|
||||
You may obtain a copy of the License at
|
||||
|
||||
http://www.apache.org/licenses/LICENSE-2.0
|
||||
|
||||
Unless required by applicable law or agreed to in writing, software
|
||||
distributed under the License is distributed on an "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
See the License for the specific language governing permissions and
|
||||
limitations under the License.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file SPC57EMxx_HSM/ppcparams.h
|
||||
* @brief PowerPC parameters for the SPC57EMxx_HSM.
|
||||
*
|
||||
* @defgroup PPC_SPC57EMxx_HSM SPC57EMxx_HSM Specific Parameters
|
||||
* @ingroup PPC_SPECIFIC
|
||||
* @details This file contains the PowerPC specific parameters for the
|
||||
* SPC57EMxx_HSM platform.
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifndef _PPCPARAMS_H_
|
||||
#define _PPCPARAMS_H_
|
||||
|
||||
/**
|
||||
* @brief Family identification macro.
|
||||
*/
|
||||
#define PPC_SPC560Dxx
|
||||
|
||||
/**
|
||||
* @brief Alternate identification macro.
|
||||
*/
|
||||
#define PPC_SPC57EMxx_HSM
|
||||
|
||||
/**
|
||||
* @brief PPC core model.
|
||||
*/
|
||||
#define PPC_VARIANT PPC_VARIANT_e200z0
|
||||
|
||||
/**
|
||||
* @brief Number of cores.
|
||||
*/
|
||||
#define PPC_CORE_NUMBER 1
|
||||
|
||||
/**
|
||||
* @brief Number of writable bits in IVPR register.
|
||||
*/
|
||||
#define PPC_IVPR_BITS 20
|
||||
|
||||
/**
|
||||
* @brief IVORx registers support.
|
||||
*/
|
||||
#define PPC_SUPPORTS_IVORS FALSE
|
||||
|
||||
/**
|
||||
* @brief Book E instruction set support.
|
||||
*/
|
||||
#define PPC_SUPPORTS_BOOKE FALSE
|
||||
|
||||
/**
|
||||
* @brief VLE instruction set support.
|
||||
*/
|
||||
#define PPC_SUPPORTS_VLE TRUE
|
||||
|
||||
/**
|
||||
* @brief Supports VLS Load/Store Multiple Volatile instructions.
|
||||
*/
|
||||
#define PPC_SUPPORTS_VLE_MULTI TRUE
|
||||
|
||||
/**
|
||||
* @brief Supports the decrementer timer.
|
||||
*/
|
||||
#define PPC_SUPPORTS_DECREMENTER FALSE
|
||||
|
||||
/**
|
||||
* @brief Number of interrupt sources.
|
||||
*/
|
||||
#define PPC_NUM_VECTORS 64
|
||||
|
||||
#endif /* _PPCPARAMS_H_ */
|
||||
|
||||
/** @} */
|
||||
|
|
@ -1,243 +1,179 @@
|
|||
# e200z common makefile scripts and rules.
|
||||
|
||||
##############################################################################
|
||||
# Processing options coming from the upper Makefile.
|
||||
#
|
||||
|
||||
# Compiler options
|
||||
OPT = $(USE_OPT)
|
||||
COPT = $(USE_COPT)
|
||||
CPPOPT = $(USE_CPPOPT)
|
||||
|
||||
# Garbage collection
|
||||
ifeq ($(USE_LINK_GC),yes)
|
||||
OPT += -ffunction-sections -fdata-sections -fno-common
|
||||
LDOPT := --gc-sections
|
||||
else
|
||||
LDOPT := --no-gc-sections
|
||||
endif
|
||||
|
||||
# Linker extra options
|
||||
ifneq ($(USE_LDOPT),)
|
||||
LDOPT := $(LDOPT),$(USE_LDOPT)
|
||||
endif
|
||||
|
||||
# Link time optimizations
|
||||
ifeq ($(USE_LTO),yes)
|
||||
OPT += -flto
|
||||
endif
|
||||
|
||||
# VLE option handling.
|
||||
ifeq ($(USE_VLE),yes)
|
||||
DDEFS += -DPPC_USE_VLE=1
|
||||
DADEFS += -DPPC_USE_VLE=1
|
||||
MCU += -mvle
|
||||
else
|
||||
DDEFS += -DPPC_USE_VLE=0
|
||||
DADEFS += -DPPC_USE_VLE=0
|
||||
endif
|
||||
|
||||
# Process stack size
|
||||
ifeq ($(USE_PROCESS_STACKSIZE),)
|
||||
LDOPT := $(LDOPT),--defsym=__process_stack_size__=0x400
|
||||
else
|
||||
LDOPT := $(LDOPT),--defsym=__process_stack_size__=$(USE_PROCESS_STACKSIZE)
|
||||
endif
|
||||
|
||||
# Exceptions stack size
|
||||
ifeq ($(USE_EXCEPTIONS_STACKSIZE),)
|
||||
LDOPT := $(LDOPT),--defsym=__irq_stack_size__=0x400
|
||||
else
|
||||
LDOPT := $(LDOPT),--defsym=__irq_stack_size__=$(USE_EXCEPTIONS_STACKSIZE)
|
||||
endif
|
||||
|
||||
# Output directory and files
|
||||
ifeq ($(BUILDDIR),)
|
||||
BUILDDIR = build
|
||||
endif
|
||||
ifeq ($(BUILDDIR),.)
|
||||
BUILDDIR = build
|
||||
endif
|
||||
OUTFILES = $(BUILDDIR)/$(PROJECT).elf $(BUILDDIR)/$(PROJECT).hex \
|
||||
$(BUILDDIR)/$(PROJECT).mot $(BUILDDIR)/$(PROJECT).bin \
|
||||
$(BUILDDIR)/$(PROJECT).dmp $(BUILDDIR)/$(PROJECT).list
|
||||
|
||||
|
||||
# Source files groups and paths
|
||||
SRC = $(CSRC)$(CPPSRC)
|
||||
SRCPATHS = $(sort $(dir $(ASMXSRC)) $(dir $(ASMSRC)) $(dir $(SRC)))
|
||||
|
||||
# Various directories
|
||||
OBJDIR = $(BUILDDIR)/obj
|
||||
LSTDIR = $(BUILDDIR)/lst
|
||||
|
||||
# Object files groups
|
||||
COBJS = $(addprefix $(OBJDIR)/, $(notdir $(CSRC:.c=.o)))
|
||||
CPPOBJS = $(addprefix $(OBJDIR)/, $(notdir $(CPPSRC:.cpp=.o)))
|
||||
ASMOBJS = $(addprefix $(OBJDIR)/, $(notdir $(ASMSRC:.s=.o)))
|
||||
ASMXOBJS = $(addprefix $(OBJDIR)/, $(notdir $(ASMXSRC:.S=.o)))
|
||||
OBJS = $(ASMXOBJS) $(ASMOBJS) $(COBJS) $(CPPOBJS)
|
||||
|
||||
# Paths
|
||||
IINCDIR = $(patsubst %,-I%,$(INCDIR) $(DINCDIR) $(UINCDIR))
|
||||
LLIBDIR = $(patsubst %,-L%,$(DLIBDIR) $(ULIBDIR))
|
||||
|
||||
# Macros
|
||||
DEFS = $(DDEFS) $(UDEFS)
|
||||
ADEFS = $(DADEFS) $(UADEFS)
|
||||
|
||||
# Libs
|
||||
LIBS = $(DLIBS) $(ULIBS)
|
||||
|
||||
# Various settings
|
||||
MCFLAGS = -mcpu=$(MCU)
|
||||
ODFLAGS = -x --syms
|
||||
ASFLAGS = $(MCFLAGS) -Wa,-amhls=$(LSTDIR)/$(notdir $(<:.s=.lst)) $(ADEFS)
|
||||
ASXFLAGS = $(MCFLAGS) -Wa,-amhls=$(LSTDIR)/$(notdir $(<:.S=.lst)) $(ADEFS)
|
||||
CFLAGS = $(MCFLAGS) $(OPT) $(COPT) $(CWARN) -Wa,-alms=$(LSTDIR)/$(notdir $(<:.c=.lst)) $(DEFS)
|
||||
CPPFLAGS = $(MCFLAGS) $(OPT) $(CPPOPT) $(CPPWARN) -Wa,-alms=$(LSTDIR)/$(notdir $(<:.cpp=.lst)) $(DEFS)
|
||||
LDFLAGS = $(MCFLAGS) $(OPT) -nostartfiles $(LLIBDIR) -Wl,-Map=$(BUILDDIR)/$(PROJECT).map,--cref,--no-warn-mismatch,--library-path=$(RULESPATH),$(LDOPT),--script=$(LDSCRIPT)
|
||||
|
||||
# Generate dependency information
|
||||
ASFLAGS += -MD -MP -MF .dep/$(@F).d
|
||||
ASXFLAGS += -MD -MP -MF .dep/$(@F).d
|
||||
CFLAGS += -MD -MP -MF .dep/$(@F).d
|
||||
CPPFLAGS += -MD -MP -MF .dep/$(@F).d
|
||||
|
||||
# Paths where to search for sources
|
||||
VPATH = $(SRCPATHS)
|
||||
|
||||
#
|
||||
# Makefile rules
|
||||
#
|
||||
|
||||
all: PRE_MAKE_ALL_RULE_HOOK $(OBJS) $(OUTFILES) POST_MAKE_ALL_RULE_HOOK
|
||||
|
||||
PRE_MAKE_ALL_RULE_HOOK:
|
||||
|
||||
POST_MAKE_ALL_RULE_HOOK:
|
||||
|
||||
$(OBJS): | $(BUILDDIR) $(OBJDIR) $(LSTDIR)
|
||||
|
||||
$(BUILDDIR):
|
||||
ifneq ($(USE_VERBOSE_COMPILE),yes)
|
||||
@echo Compiler Options
|
||||
@echo $(CC) -c $(CFLAGS) -I. $(IINCDIR) main.c -o main.o
|
||||
@echo
|
||||
endif
|
||||
@mkdir -p $(BUILDDIR)
|
||||
|
||||
$(OBJDIR):
|
||||
@mkdir -p $(OBJDIR)
|
||||
|
||||
$(LSTDIR):
|
||||
@mkdir -p $(LSTDIR)
|
||||
|
||||
$(CPPOBJS) : $(OBJDIR)/%.o : %.cpp Makefile
|
||||
ifeq ($(USE_VERBOSE_COMPILE),yes)
|
||||
@echo
|
||||
$(CPPC) -c $(CPPFLAGS) -I. $(IINCDIR) $< -o $@
|
||||
else
|
||||
@echo Compiling $(<F)
|
||||
@$(CPPC) -c $(CPPFLAGS) -I. $(IINCDIR) $< -o $@
|
||||
endif
|
||||
|
||||
$(COBJS) : $(OBJDIR)/%.o : %.c Makefile
|
||||
ifeq ($(USE_VERBOSE_COMPILE),yes)
|
||||
@echo
|
||||
$(CC) -c $(CFLAGS) -I. $(IINCDIR) $< -o $@
|
||||
else
|
||||
@echo Compiling $(<F)
|
||||
@$(CC) -c $(CFLAGS) -I. $(IINCDIR) $< -o $@
|
||||
endif
|
||||
|
||||
$(ASMOBJS) : $(OBJDIR)/%.o : %.s Makefile
|
||||
ifeq ($(USE_VERBOSE_COMPILE),yes)
|
||||
@echo
|
||||
$(AS) -c $(ASFLAGS) -I. $(IINCDIR) $< -o $@
|
||||
else
|
||||
@echo Compiling $(<F)
|
||||
@$(AS) -c $(ASFLAGS) -I. $(IINCDIR) $< -o $@
|
||||
endif
|
||||
|
||||
$(ASMXOBJS) : $(OBJDIR)/%.o : %.S Makefile
|
||||
ifeq ($(USE_VERBOSE_COMPILE),yes)
|
||||
@echo
|
||||
$(CC) -c $(ASXFLAGS) -I. $(IINCDIR) $< -o $@
|
||||
else
|
||||
@echo Compiling $(<F)
|
||||
@$(CC) -c $(ASXFLAGS) -I. $(IINCDIR) $< -o $@
|
||||
endif
|
||||
|
||||
%.elf: $(OBJS) $(LDSCRIPT)
|
||||
ifeq ($(USE_VERBOSE_COMPILE),yes)
|
||||
@echo
|
||||
$(LD) $(OBJS) $(LDFLAGS) $(LIBS) -o $@
|
||||
else
|
||||
@echo Linking $@
|
||||
@$(LD) $(OBJS) $(LDFLAGS) $(LIBS) -o $@
|
||||
endif
|
||||
|
||||
%.hex: %.elf $(LDSCRIPT)
|
||||
ifeq ($(USE_VERBOSE_COMPILE),yes)
|
||||
$(HEX) $< $@
|
||||
else
|
||||
@echo Creating $@
|
||||
@$(HEX) $< $@
|
||||
endif
|
||||
|
||||
%.mot: %.elf $(LDSCRIPT)
|
||||
ifeq ($(USE_VERBOSE_COMPILE),yes)
|
||||
$(MOT) $< $@
|
||||
else
|
||||
@echo Creating $@
|
||||
@$(MOT) $< $@
|
||||
endif
|
||||
|
||||
%.bin: %.elf $(LDSCRIPT)
|
||||
ifeq ($(USE_VERBOSE_COMPILE),yes)
|
||||
$(BIN) $< $@
|
||||
else
|
||||
@echo Creating $@
|
||||
@$(BIN) $< $@
|
||||
endif
|
||||
|
||||
%.dmp: %.elf $(LDSCRIPT)
|
||||
ifeq ($(USE_VERBOSE_COMPILE),yes)
|
||||
$(OD) $(ODFLAGS) $< > $@
|
||||
$(SZ) $<
|
||||
else
|
||||
@echo Creating $@
|
||||
@$(OD) $(ODFLAGS) $< > $@
|
||||
@echo
|
||||
@$(SZ) $<
|
||||
endif
|
||||
|
||||
%.list: %.elf $(LDSCRIPT)
|
||||
ifeq ($(USE_VERBOSE_COMPILE),yes)
|
||||
$(OD) -S $< > $@
|
||||
else
|
||||
@echo Creating $@
|
||||
@$(OD) -S $< > $@
|
||||
@echo Done
|
||||
endif
|
||||
|
||||
lib: $(OBJS) $(BUILDDIR)/lib$(PROJECT).a
|
||||
|
||||
$(BUILDDIR)/lib$(PROJECT).a: $(OBJS)
|
||||
@$(AR) -r $@ $^
|
||||
@echo
|
||||
@echo Done
|
||||
|
||||
clean:
|
||||
@echo Cleaning
|
||||
-rm -fR .dep $(BUILDDIR)
|
||||
@echo
|
||||
@echo Done
|
||||
|
||||
#
|
||||
# Include the dependency files, should be the last of the makefile
|
||||
#
|
||||
-include $(shell mkdir .dep 2>/dev/null) $(wildcard .dep/*)
|
||||
|
||||
# *** EOF ***
|
||||
# e200z common makefile scripts and rules.
|
||||
|
||||
##############################################################################
|
||||
# Processing options coming from the upper Makefile.
|
||||
#
|
||||
|
||||
# Compiler options
|
||||
OPT = $(USE_OPT)
|
||||
COPT = $(USE_COPT)
|
||||
CPPOPT = $(USE_CPPOPT)
|
||||
|
||||
# Garbage collection
|
||||
ifeq ($(USE_LINK_GC),yes)
|
||||
OPT += -ffunction-sections -fdata-sections -fno-common
|
||||
LDOPT := --gc-sections
|
||||
else
|
||||
LDOPT := --no-gc-sections
|
||||
endif
|
||||
|
||||
# Linker extra options
|
||||
ifneq ($(USE_LDOPT),)
|
||||
LDOPT := $(LDOPT),$(USE_LDOPT)
|
||||
endif
|
||||
|
||||
# Link time optimizations
|
||||
ifeq ($(USE_LTO),yes)
|
||||
OPT += -flto
|
||||
endif
|
||||
|
||||
# Output directory and files
|
||||
ifeq ($(BUILDDIR),)
|
||||
BUILDDIR = build
|
||||
endif
|
||||
ifeq ($(BUILDDIR),.)
|
||||
BUILDDIR = build
|
||||
endif
|
||||
OUTFILES = $(BUILDDIR)/$(PROJECT)
|
||||
|
||||
|
||||
# Source files groups and paths
|
||||
SRC = $(CSRC)$(CPPSRC)
|
||||
SRCPATHS = $(sort $(dir $(ASMXSRC)) $(dir $(ASMSRC)) $(dir $(SRC)))
|
||||
|
||||
# Various directories
|
||||
OBJDIR = $(BUILDDIR)/obj
|
||||
LSTDIR = $(BUILDDIR)/lst
|
||||
|
||||
# Object files groups
|
||||
COBJS = $(addprefix $(OBJDIR)/, $(notdir $(CSRC:.c=.o)))
|
||||
CPPOBJS = $(addprefix $(OBJDIR)/, $(notdir $(CPPSRC:.cpp=.o)))
|
||||
ASMOBJS = $(addprefix $(OBJDIR)/, $(notdir $(ASMSRC:.s=.o)))
|
||||
ASMXOBJS = $(addprefix $(OBJDIR)/, $(notdir $(ASMXSRC:.S=.o)))
|
||||
OBJS = $(ASMXOBJS) $(ASMOBJS) $(COBJS) $(CPPOBJS)
|
||||
|
||||
# Paths
|
||||
IINCDIR = $(patsubst %,-I%,$(INCDIR) $(DINCDIR) $(UINCDIR))
|
||||
LLIBDIR = $(patsubst %,-L%,$(DLIBDIR) $(ULIBDIR))
|
||||
|
||||
# Macros
|
||||
DEFS = $(DDEFS) $(UDEFS)
|
||||
ADEFS = $(DADEFS) $(UADEFS)
|
||||
|
||||
# Libs
|
||||
LIBS = $(DLIBS) $(ULIBS)
|
||||
|
||||
# Various settings
|
||||
MCFLAGS =
|
||||
ODFLAGS = -x --syms
|
||||
ASFLAGS = $(MCFLAGS) -Wa,-amhls=$(LSTDIR)/$(notdir $(<:.s=.lst)) $(ADEFS)
|
||||
ASXFLAGS = $(MCFLAGS) -Wa,-amhls=$(LSTDIR)/$(notdir $(<:.S=.lst)) $(ADEFS)
|
||||
CFLAGS = $(MCFLAGS) $(OPT) $(COPT) $(CWARN) -Wa,-alms=$(LSTDIR)/$(notdir $(<:.c=.lst)) $(DEFS)
|
||||
CPPFLAGS = $(MCFLAGS) $(OPT) $(CPPOPT) $(CPPWARN) -Wa,-alms=$(LSTDIR)/$(notdir $(<:.cpp=.lst)) $(DEFS)
|
||||
LDFLAGS = $(MCFLAGS) $(OPT) $(LLIBDIR) -Wl,-Map=$(BUILDDIR)/$(PROJECT).map,--cref,--no-warn-mismatch,$(LDOPT)
|
||||
|
||||
# Generate dependency information
|
||||
ASFLAGS += -MD -MP -MF .dep/$(@F).d
|
||||
ASXFLAGS += -MD -MP -MF .dep/$(@F).d
|
||||
CFLAGS += -MD -MP -MF .dep/$(@F).d
|
||||
CPPFLAGS += -MD -MP -MF .dep/$(@F).d
|
||||
|
||||
# Paths where to search for sources
|
||||
VPATH = $(SRCPATHS)
|
||||
|
||||
#
|
||||
# Makefile rules
|
||||
#
|
||||
|
||||
all: PRE_MAKE_ALL_RULE_HOOK $(OBJS) $(OUTFILES) POST_MAKE_ALL_RULE_HOOK
|
||||
|
||||
PRE_MAKE_ALL_RULE_HOOK:
|
||||
|
||||
POST_MAKE_ALL_RULE_HOOK:
|
||||
|
||||
$(OBJS): | $(BUILDDIR) $(OBJDIR) $(LSTDIR)
|
||||
|
||||
$(BUILDDIR):
|
||||
ifneq ($(USE_VERBOSE_COMPILE),yes)
|
||||
@echo Compiler Options
|
||||
@echo $(CC) -c $(CFLAGS) -I. $(IINCDIR) main.c -o main.o
|
||||
@echo
|
||||
endif
|
||||
@mkdir -p $(BUILDDIR)
|
||||
|
||||
$(OBJDIR):
|
||||
@mkdir -p $(OBJDIR)
|
||||
|
||||
$(LSTDIR):
|
||||
@mkdir -p $(LSTDIR)
|
||||
|
||||
$(CPPOBJS) : $(OBJDIR)/%.o : %.cpp Makefile
|
||||
ifeq ($(USE_VERBOSE_COMPILE),yes)
|
||||
@echo
|
||||
$(CPPC) -c $(CPPFLAGS) -I. $(IINCDIR) $< -o $@
|
||||
else
|
||||
@echo Compiling $(<F)
|
||||
@$(CPPC) -c $(CPPFLAGS) -I. $(IINCDIR) $< -o $@
|
||||
endif
|
||||
|
||||
$(COBJS) : $(OBJDIR)/%.o : %.c Makefile
|
||||
ifeq ($(USE_VERBOSE_COMPILE),yes)
|
||||
@echo
|
||||
$(CC) -c $(CFLAGS) -I. $(IINCDIR) $< -o $@
|
||||
else
|
||||
@echo Compiling $(<F)
|
||||
@$(CC) -c $(CFLAGS) -I. $(IINCDIR) $< -o $@
|
||||
endif
|
||||
|
||||
$(ASMOBJS) : $(OBJDIR)/%.o : %.s Makefile
|
||||
ifeq ($(USE_VERBOSE_COMPILE),yes)
|
||||
@echo
|
||||
$(AS) -c $(ASFLAGS) -I. $(IINCDIR) $< -o $@
|
||||
else
|
||||
@echo Compiling $(<F)
|
||||
@$(AS) -c $(ASFLAGS) -I. $(IINCDIR) $< -o $@
|
||||
endif
|
||||
|
||||
$(ASMXOBJS) : $(OBJDIR)/%.o : %.S Makefile
|
||||
ifeq ($(USE_VERBOSE_COMPILE),yes)
|
||||
@echo
|
||||
$(CC) -c $(ASXFLAGS) -I. $(IINCDIR) $< -o $@
|
||||
else
|
||||
@echo Compiling $(<F)
|
||||
@$(CC) -c $(ASXFLAGS) -I. $(IINCDIR) $< -o $@
|
||||
endif
|
||||
|
||||
$(BUILDDIR)/$(PROJECT): $(OBJS)
|
||||
ifeq ($(USE_VERBOSE_COMPILE),yes)
|
||||
@echo
|
||||
$(LD) $(OBJS) $(LDFLAGS) $(LIBS) -o $@
|
||||
else
|
||||
@echo Linking $@
|
||||
@$(LD) $(OBJS) $(LDFLAGS) $(LIBS) -o $@
|
||||
endif
|
||||
|
||||
lib: $(OBJS) $(BUILDDIR)/lib$(PROJECT).a
|
||||
|
||||
$(BUILDDIR)/lib$(PROJECT).a: $(OBJS)
|
||||
@$(AR) -r $@ $^
|
||||
@echo
|
||||
@echo Done
|
||||
|
||||
clean: CLEAN_RULE_HOOK
|
||||
@echo Cleaning
|
||||
-rm -fR .dep $(BUILDDIR)
|
||||
@echo
|
||||
@echo Done
|
||||
|
||||
CLEAN_RULE_HOOK:
|
||||
|
||||
.PHONY: gcov
|
||||
gcov:
|
||||
$(COV) -u -b -o $(BUILDDIR)/obj $(GCOVSRC)
|
||||
|
||||
#
|
||||
# Include the dependency files, should be the last of the makefile
|
||||
#
|
||||
-include $(shell mkdir .dep 2>/dev/null) $(wildcard .dep/*)
|
||||
|
||||
# *** EOF ***
|
||||
Loading…
Reference in New Issue