From c450b544c1a35478fd07c093e82ba5cc000f078e Mon Sep 17 00:00:00 2001
From: gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4>
Date: Fri, 29 Mar 2013 10:18:38 +0000
Subject: [PATCH] git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@5514
 35acf78f-673a-0410-8e92-d51de3d6d3f4

---
 os/hal/platforms/SPC5xx/DSPI_v1/spi_lld.c | 19 ++++---------------
 testhal/SPC563Mxx/SPI/main.c              |  4 ++--
 2 files changed, 6 insertions(+), 17 deletions(-)

diff --git a/os/hal/platforms/SPC5xx/DSPI_v1/spi_lld.c b/os/hal/platforms/SPC5xx/DSPI_v1/spi_lld.c
index b7e7a07fa..a8d5773e2 100644
--- a/os/hal/platforms/SPC5xx/DSPI_v1/spi_lld.c
+++ b/os/hal/platforms/SPC5xx/DSPI_v1/spi_lld.c
@@ -248,10 +248,12 @@ static void spi_start_dma_tx8(SPIDriver *spip,
                               size_t n,
                               const uint8_t *txbuf) {
   uint32_t cmd = spip->config->pushr & ~DSPI_PUSHR_EXCLUDED_BITS;
+  uint8_t *cp = (uint8_t *)DSPI_PUSHR8_ADDRESS(spip);
 
   /* The first frame is pushed by the CPU, then the DMA is activated to
      send the following frames.*/
   spip->dspi->PUSHR.R = cmd | (uint32_t)*txbuf++;
+  *cp = 0x55;
 
   /* Setting up TX DMA TCD parameters for 8 bits transfers.*/
   edmaChannelSetup(spip->tx_channel,            /* channel.                 */
@@ -397,20 +399,6 @@ static void spi_serve_dma_error_irq(edma_channel_t channel,
  */
 void spi_lld_init(void) {
 
-  /* Enforcing low power mode for all DSPIs even if not used.*/
-#if SPC5_HAS_DSPI0
-  SPC5_DSPI0.MCR.R = SPC5_MCR_MSTR | SPC5_MCR_MDIS | SPC5_MCR_HALT;
-#endif
-#if SPC5_HAS_DSPI1
-  SPC5_DSPI1.MCR.R = SPC5_MCR_MSTR | SPC5_MCR_MDIS | SPC5_MCR_HALT;
-#endif
-#if SPC5_HAS_DSPI2
-  SPC5_DSPI2.MCR.R = SPC5_MCR_MSTR | SPC5_MCR_MDIS | SPC5_MCR_HALT;
-#endif
-#if SPC5_HAS_DSPI3
-  SPC5_DSPI3.MCR.R = SPC5_MCR_MSTR | SPC5_MCR_MDIS | SPC5_MCR_HALT;
-#endif
-
 #if SPC5_SPI_USE_DSPI0
   /* Driver initialization.*/
   spiObjectInit(&SPID1);
@@ -496,7 +484,8 @@ void spi_lld_start(SPIDriver *spip) {
   /* Configures the peripheral.*/
   spip->dspi->MCR.R     = SPC5_MCR_MSTR | SPC5_MCR_HALT | spip->config->mcr;
   spip->dspi->CTAR[0].R = spip->config->ctar0;
-  spip->dspi->RSER.R    = SPC5_RSER_TFFF_DIRS | SPC5_RSER_RFDF_DIRS;
+  spip->dspi->RSER.R    = SPC5_RSER_TFFF_RE | SPC5_RSER_TFFF_DIRS |
+                          SPC5_RSER_RFDF_RE | SPC5_RSER_RFDF_DIRS;
   spip->dspi->SR.R      = spip->dspi->SR.R;
 }
 
diff --git a/testhal/SPC563Mxx/SPI/main.c b/testhal/SPC563Mxx/SPI/main.c
index 25c9a2ede..b22eaba64 100644
--- a/testhal/SPC563Mxx/SPI/main.c
+++ b/testhal/SPC563Mxx/SPI/main.c
@@ -30,7 +30,7 @@ static const SPIConfig hs_spicfg = {
   0,
   0,                                                            /* MCR.     */
   SPC5_CTAR_FMSZ(8) | SPC5_CTAR_PBR_PRE2 | SPC5_CTAR_BR_DIV2,   /* CTAR0.   */
-  0                                                             /* PUSHR.   */
+  SPC5_PUSHR_CONT | SPC5_PUSHR_PCS(0)                           /* PUSHR.   */
 };
 
 /*
@@ -42,7 +42,7 @@ static const SPIConfig ls_spicfg = {
   0,
   0,                                                            /* MCR.     */
   SPC5_CTAR_FMSZ(8) | SPC5_CTAR_PBR_PRE2 | SPC5_CTAR_BR_DIV256, /* CTAR0.   */
-  0                                                             /* PUSHR.   */
+  SPC5_PUSHR_CONT | SPC5_PUSHR_PCS(0)                           /* PUSHR.   */
 };
 
 /*