andreika-git
/
ChibiOS
mirror of https://github.com/andreika-git/ChibiOS.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@8279 35acf78f-673a-0410-8e92-d51de3d6d3f4

This commit is contained in:
gdisirio 2015-09-04 12:29:23 +00:00
parent 6274f1e25f
commit c497eb864e
1 changed files with 9 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

11
testhal/STM32/STM32F7xx/GPT-ADC/main.c
View File

@ -17,6 +17,10 @@
#include "ch.h" #include "ch.h"
#include "hal.h" #include "hal.h"
/* TRUE means that DMA-accessible buffers are placed in a non-cached RAM
area and that no cache management is required.*/
#define DMA_BUFFERS_COHERENCE TRUE
/*===========================================================================*/ /*===========================================================================*/
/* GPT driver related. */ /* GPT driver related. */
/*===========================================================================*/ /*===========================================================================*/
@ -38,12 +42,15 @@ static const GPTConfig gpt4cfg1 = {
#define ADC_GRP1_NUM_CHANNELS 2 #define ADC_GRP1_NUM_CHANNELS 2
#define ADC_GRP1_BUF_DEPTH 64 #define ADC_GRP1_BUF_DEPTH 64
#if !DMA_BUFFERS_COHERENCE
/* Note, the buffer is aligned to a 32 bytes boundary because limitations /* Note, the buffer is aligned to a 32 bytes boundary because limitations
imposed by the data cache. Note, this is GNU specific, it must be imposed by the data cache. Note, this is GNU specific, it must be
handled differently for other compilers.*/ handled differently for other compilers.
Only required if the ADC buffer is placed in a cache-able area.*/
#if defined(__GNUC__) #if defined(__GNUC__)
__attribute__((aligned (32))) __attribute__((aligned (32)))
#endif #endif
#endif
static adcsample_t samples1[ADC_GRP1_NUM_CHANNELS * ADC_GRP1_BUF_DEPTH]; static adcsample_t samples1[ADC_GRP1_NUM_CHANNELS * ADC_GRP1_BUF_DEPTH];
/* /*
@ -52,7 +59,7 @@ static adcsample_t samples1[ADC_GRP1_NUM_CHANNELS * ADC_GRP1_BUF_DEPTH];
size_t nx = 0, ny = 0; size_t nx = 0, ny = 0;
static void adccallback(ADCDriver *adcp, adcsample_t *buffer, size_t n) { static void adccallback(ADCDriver *adcp, adcsample_t *buffer, size_t n) {
#if 0 #if !DMA_BUFFERS_COHERENCE
/* DMA buffer invalidation because data cache, only invalidating the /* DMA buffer invalidation because data cache, only invalidating the
half buffer just filled. half buffer just filled.
Only required if the ADC buffer is placed in a cache-able area.*/ Only required if the ADC buffer is placed in a cache-able area.*/