Removed instances of //
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3746 35acf78f-673a-0410-8e92-d51de3d6d3f4
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@ -275,7 +275,7 @@ int main(void) {
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chEvtRegister(&evt.et_es, &el0, 0); /* Registers on the timer event source. */
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chEvtRegister(&MMCD1.inserted_event, &el1, 1);
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chEvtRegister(&MMCD1.removed_event, &el2, 2);
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while (TRUE)// chThdSleepMilliseconds(50);
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while (TRUE)
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chEvtDispatch(evhndl, chEvtWaitOne(ALL_EVENTS));
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return 0;
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}
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@ -81,14 +81,14 @@ void miiReset(MACDriver *macp) {
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/*
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* PHY power control.
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*/
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AT91C_BASE_PIOB->PIO_OER = PIOB_PHY_PD_MASK; // Becomes an output.
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AT91C_BASE_PIOB->PIO_PPUDR = PIOB_PHY_PD_MASK; // Default pullup disabled.
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AT91C_BASE_PIOB->PIO_OER = PIOB_PHY_PD_MASK; /* Becomes an output. */
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AT91C_BASE_PIOB->PIO_PPUDR = PIOB_PHY_PD_MASK;/* Default pullup disabled. */
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#if (PHY_HARDWARE == PHY_DAVICOM_9161)
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AT91C_BASE_PIOB->PIO_CODR = PIOB_PHY_PD_MASK; // Output to low level.
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AT91C_BASE_PIOB->PIO_CODR = PIOB_PHY_PD_MASK; /* Output to low level. */
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#else
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AT91C_BASE_PIOB->PIO_SODR = PIOB_PHY_PD_MASK; // Output to high level.
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AT91C_BASE_PIOB->PIO_SODR = PIOB_PHY_PD_MASK; /* Output to high level. */
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#endif
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#endif
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#endif // PIOB_PHY_PD_MASK
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/*
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* PHY reset by pulsing the NRST pin.
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@ -277,7 +277,7 @@ typedef struct {
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IOREG32 UART_FCR;
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};
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IOREG32 UART_LCR;
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IOREG32 UART_MCR; // UART1 only
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IOREG32 UART_MCR;
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IOREG32 UART_LSR;
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IOREG32 unused18;
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IOREG32 UART_SCR;
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@ -89,7 +89,7 @@ void ChkIntSources(void) {
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}
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#endif
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// Interrupt Timer simulation (10ms interval).
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/* Interrupt Timer simulation (10ms interval).*/
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QueryPerformanceCounter(&n);
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if (n.QuadPart > nextcnt.QuadPart) {
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nextcnt.QuadPart += slice.QuadPart;
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@ -100,7 +100,7 @@ static msg_t thread1(void *p) {
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static void mtx1_execute(void) {
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tprio_t prio = chThdGetPriority(); // Because priority inheritance.
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tprio_t prio = chThdGetPriority(); /* Because priority inheritance.*/
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chMtxLock(&m1);
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threads[0] = chThdCreateStatic(wa[0], WA_SIZE, prio+1, thread1, "E");
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threads[1] = chThdCreateStatic(wa[1], WA_SIZE, prio+2, thread1, "D");
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@ -244,8 +244,8 @@ ROMCONST struct testcase testmtx2 = {
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static void mtx3_setup(void) {
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chMtxInit(&m1); // Mutex B
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chMtxInit(&m2); // Mutex A
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chMtxInit(&m1); /* Mutex B.*/
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chMtxInit(&m2); /* Mutex A.*/
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}
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/* Lowest priority thread */
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@ -539,7 +539,6 @@ static void mtx7_setup(void) {
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static void mtx7_execute(void) {
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// Bacause priority inheritance.
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tprio_t prio = chThdGetPriority();
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threads[0] = chThdCreateStatic(wa[0], WA_SIZE, prio+1, thread10, "E");
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threads[1] = chThdCreateStatic(wa[1], WA_SIZE, prio+2, thread10, "D");
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@ -93,7 +93,7 @@ static void cmd_reboot(BaseChannel *chp, int argc, char *argv[]){
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return;
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}
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chprintf(chp, "rebooting...\r\n");
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chThdSleepMilliseconds(100); // time to print out message in terminal
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chThdSleepMilliseconds(100);
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NVIC_SystemReset();
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}
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@ -105,11 +105,11 @@ static void cmd_sleep(BaseChannel *chp, int argc, char *argv[]){
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}
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chprintf(chp, "Going to sleep. Type any character to wake up.\r\n");
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chThdSleepMilliseconds(200); // time to print out message in terminal
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chThdSleepMilliseconds(200);
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extChannelEnable(&EXTD1, 10);
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PWR->CR |= (PWR_CR_LPDS | PWR_CR_CSBF | PWR_CR_CWUF);
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PWR->CR &= ~PWR_CR_PDDS; // explicit clear PDDS, just to be safe
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PWR->CR &= ~PWR_CR_PDDS;
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SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
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__WFI();
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}
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@ -146,20 +146,20 @@ int main(void) {
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*/
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extStart(&EXTD1, &extcfg);
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/* Activates the serial driver using the driver default configuration. */
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/* Activates the serial driver using the driver default configuration.*/
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sdStart(&SD1, NULL);
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/* Setting up ports. */
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/* Setting up ports.*/
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palSetPadMode(IOPORT1, 9, PAL_MODE_STM32_ALTERNATE_PUSHPULL);
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palSetPadMode(IOPORT1, 10, PAL_MODE_INPUT);
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/* Shell manager initialization. */
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/* Shell manager initialization.*/
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shellInit();
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static WORKING_AREA(waShell, 512);
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shellCreateStatic(&shell_cfg1, waShell, sizeof(waShell), NORMALPRIO);
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/* Start blink indicating. */
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chThdSleepMilliseconds(2000); // timeuot to differ reboot and wake up from sleep
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/* Start blink indicating.*/
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chThdSleepMilliseconds(2000);
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while (TRUE) {
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chThdSleepMilliseconds(100);
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palTogglePad(IOPORT3, GPIOC_LED);
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@ -99,12 +99,12 @@
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#define STM32_EXT_EXTI5_9_IRQ_PRIORITY 6
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#define STM32_EXT_EXTI10_15_IRQ_PRIORITY 6
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#define STM32_EXT_EXTI16_IRQ_PRIORITY 6
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#define STM32_EXT_EXTI17_IRQ_PRIORITY 15 // RTC alarm
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#define STM32_EXT_EXTI17_IRQ_PRIORITY 15
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#define STM32_EXT_EXTI18_IRQ_PRIORITY 6
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#define STM32_EXT_EXTI19_IRQ_PRIORITY 6
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#define STM32_EXT_EXTI20_IRQ_PRIORITY 6
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#define STM32_EXT_EXTI21_IRQ_PRIORITY 15 // RTC tamper-timestamp
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#define STM32_EXT_EXTI22_IRQ_PRIORITY 15 // RTC wakeup
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#define STM32_EXT_EXTI21_IRQ_PRIORITY 15
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#define STM32_EXT_EXTI22_IRQ_PRIORITY 15
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/*
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* GPT driver system settings.
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