andreika-git
/
ChibiOS
mirror of https://github.com/andreika-git/ChibiOS.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@4829 35acf78f-673a-0410-8e92-d51de3d6d3f4

This commit is contained in:
gdisirio 2012-11-19 11:50:14 +00:00
parent 7fa885a201
commit c57e384229
13 changed files with 175 additions and 207 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
boards/GENERIC_SPC560B/board.c
View File

@ -62,7 +62,7 @@ const PALConfig pal_default_config =
*/ */
void __early_init(void) { void __early_init(void) {
spc560bc_clock_init(); spc_clock_init();
} }
/* /*

2
boards/GENERIC_SPC560B/board.h
View File

@ -35,7 +35,7 @@
* Board frequencies. * Board frequencies.
*/ */
#if !defined(SPC5_XOSC_CLK) #if !defined(SPC5_XOSC_CLK)
#define SPC5_XOSC_CLK 40000000 #define SPC5_XOSC_CLK 8000000
#endif #endif
/* /*

2
boards/GENERIC_SPC560P/board.c
View File

@ -62,7 +62,7 @@ const PALConfig pal_default_config =
*/ */
void __early_init(void) { void __early_init(void) {
spc560p_clock_init(); spc_clock_init();
} }
/* /*

2
demos/PPC-SPC560B-GCC/.project
View File

@ -27,7 +27,7 @@
<link> <link>
<name>board</name> <name>board</name>
<type>2</type> <type>2</type>
<locationURI>CHIBIOS/boards/GENERIC_SPC560P</locationURI> <locationURI>CHIBIOS/boards/GENERIC_SPC560B</locationURI>
</link> </link>
<link> <link>
<name>os</name> <name>os</name>

8
demos/PPC-SPC560B-GCC/Makefile
View File

@ -46,15 +46,15 @@ PROJECT = ch
# Imported source files # Imported source files
CHIBIOS = ../.. CHIBIOS = ../..
include $(CHIBIOS)/boards/GENERIC_SPC560P/board.mk include $(CHIBIOS)/boards/GENERIC_SPC560B/board.mk
include $(CHIBIOS)/os/hal/platforms/SPC560Pxx/platform.mk include $(CHIBIOS)/os/hal/platforms/SPC560BCxx/platform.mk
include $(CHIBIOS)/os/hal/hal.mk include $(CHIBIOS)/os/hal/hal.mk
include $(CHIBIOS)/os/ports/GCC/PPC/SPC560Pxx/port.mk include $(CHIBIOS)/os/ports/GCC/PPC/SPC560BCxx/port.mk
include $(CHIBIOS)/os/kernel/kernel.mk include $(CHIBIOS)/os/kernel/kernel.mk
include $(CHIBIOS)/test/test.mk include $(CHIBIOS)/test/test.mk
# Define linker script file here # Define linker script file here
LDSCRIPT= $(PORTLD)/SPC560P44.ld LDSCRIPT= $(PORTLD)/SPC560B50.ld
# C sources here. # C sources here.
CSRC = $(PORTSRC) \ CSRC = $(PORTSRC) \

39
demos/PPC-SPC560B-GCC/mcuconf.h
View File

@ -36,22 +36,21 @@
*/ */
#define SPC5_NO_INIT FALSE #define SPC5_NO_INIT FALSE
#define SPC5_ALLOW_OVERCLOCK FALSE #define SPC5_ALLOW_OVERCLOCK FALSE
#define SPC5_FMPLL0_IDF_VALUE 5 #define SPC5_XOSCDIV_VALUE 1
#define SPC5_IRCDIV_VALUE 1
#define SPC5_FMPLL0_IDF_VALUE 1
#define SPC5_FMPLL0_NDIV_VALUE 32 #define SPC5_FMPLL0_NDIV_VALUE 32
#define SPC5_FMPLL0_ODF SPC5_FMPLL_ODF_DIV4 #define SPC5_FMPLL0_ODF SPC5_FMPLL_ODF_DIV4
#define SPC5_FMPLL1_IDF_VALUE 5
#define SPC5_FMPLL1_NDIV_VALUE 60
#define SPC5_FMPLL1_ODF SPC5_FMPLL_ODF_DIV4
#define SPC5_ME_ME_BITS (SPC5_ME_ME_RUN1 | \ #define SPC5_ME_ME_BITS (SPC5_ME_ME_RUN1 | \
SPC5_ME_ME_RUN2 | \ SPC5_ME_ME_RUN2 | \
SPC5_ME_ME_RUN3 | \ SPC5_ME_ME_RUN3 | \
SPC5_ME_ME_HALT0 | \ SPC5_ME_ME_HALT0 | \
SPC5_ME_ME_STOP0) SPC5_ME_ME_STOP0 | \
SPC5_ME_ME_STANDBY0)
#define SPC5_ME_TEST_MC_BITS (SPC5_ME_MC_SYSCLK_IRC | \ #define SPC5_ME_TEST_MC_BITS (SPC5_ME_MC_SYSCLK_IRC | \
SPC5_ME_MC_IRCON | \ SPC5_ME_MC_IRCON | \
SPC5_ME_MC_XOSC0ON | \ SPC5_ME_MC_XOSC0ON | \
SPC5_ME_MC_PLL0ON | \ SPC5_ME_MC_PLL0ON | \
SPC5_ME_MC_PLL1ON | \
SPC5_ME_MC_CFLAON_NORMAL | \ SPC5_ME_MC_CFLAON_NORMAL | \
SPC5_ME_MC_DFLAON_NORMAL | \ SPC5_ME_MC_DFLAON_NORMAL | \
SPC5_ME_MC_MVRON) SPC5_ME_MC_MVRON)
@ -60,7 +59,6 @@
SPC5_ME_MC_IRCON | \ SPC5_ME_MC_IRCON | \
SPC5_ME_MC_XOSC0ON | \ SPC5_ME_MC_XOSC0ON | \
SPC5_ME_MC_PLL0ON | \ SPC5_ME_MC_PLL0ON | \
SPC5_ME_MC_PLL1ON | \
SPC5_ME_MC_CFLAON_NORMAL | \ SPC5_ME_MC_CFLAON_NORMAL | \
SPC5_ME_MC_DFLAON_NORMAL | \ SPC5_ME_MC_DFLAON_NORMAL | \
SPC5_ME_MC_MVRON) SPC5_ME_MC_MVRON)
@ -68,7 +66,6 @@
SPC5_ME_MC_IRCON | \ SPC5_ME_MC_IRCON | \
SPC5_ME_MC_XOSC0ON | \ SPC5_ME_MC_XOSC0ON | \
SPC5_ME_MC_PLL0ON | \ SPC5_ME_MC_PLL0ON | \
SPC5_ME_MC_PLL1ON | \
SPC5_ME_MC_CFLAON_NORMAL | \ SPC5_ME_MC_CFLAON_NORMAL | \
SPC5_ME_MC_DFLAON_NORMAL | \ SPC5_ME_MC_DFLAON_NORMAL | \
SPC5_ME_MC_MVRON) SPC5_ME_MC_MVRON)
@ -76,7 +73,6 @@
SPC5_ME_MC_IRCON | \ SPC5_ME_MC_IRCON | \
SPC5_ME_MC_XOSC0ON | \ SPC5_ME_MC_XOSC0ON | \
SPC5_ME_MC_PLL0ON | \ SPC5_ME_MC_PLL0ON | \
SPC5_ME_MC_PLL1ON | \
SPC5_ME_MC_CFLAON_NORMAL | \ SPC5_ME_MC_CFLAON_NORMAL | \
SPC5_ME_MC_DFLAON_NORMAL | \ SPC5_ME_MC_DFLAON_NORMAL | \
SPC5_ME_MC_MVRON) SPC5_ME_MC_MVRON)
@ -84,7 +80,6 @@
SPC5_ME_MC_IRCON | \ SPC5_ME_MC_IRCON | \
SPC5_ME_MC_XOSC0ON | \ SPC5_ME_MC_XOSC0ON | \
SPC5_ME_MC_PLL0ON | \ SPC5_ME_MC_PLL0ON | \
SPC5_ME_MC_PLL1ON | \
SPC5_ME_MC_CFLAON_NORMAL | \ SPC5_ME_MC_CFLAON_NORMAL | \
SPC5_ME_MC_DFLAON_NORMAL | \ SPC5_ME_MC_DFLAON_NORMAL | \
SPC5_ME_MC_MVRON) SPC5_ME_MC_MVRON)
@ -92,7 +87,6 @@
SPC5_ME_MC_IRCON | \ SPC5_ME_MC_IRCON | \
SPC5_ME_MC_XOSC0ON | \ SPC5_ME_MC_XOSC0ON | \
SPC5_ME_MC_PLL0ON | \ SPC5_ME_MC_PLL0ON | \
SPC5_ME_MC_PLL1ON | \
SPC5_ME_MC_CFLAON_NORMAL | \ SPC5_ME_MC_CFLAON_NORMAL | \
SPC5_ME_MC_DFLAON_NORMAL | \ SPC5_ME_MC_DFLAON_NORMAL | \
SPC5_ME_MC_MVRON) SPC5_ME_MC_MVRON)
@ -100,7 +94,6 @@
SPC5_ME_MC_IRCON | \ SPC5_ME_MC_IRCON | \
SPC5_ME_MC_XOSC0ON | \ SPC5_ME_MC_XOSC0ON | \
SPC5_ME_MC_PLL0ON | \ SPC5_ME_MC_PLL0ON | \
SPC5_ME_MC_PLL1ON | \
SPC5_ME_MC_CFLAON_NORMAL | \ SPC5_ME_MC_CFLAON_NORMAL | \
SPC5_ME_MC_DFLAON_NORMAL | \ SPC5_ME_MC_DFLAON_NORMAL | \
SPC5_ME_MC_MVRON) SPC5_ME_MC_MVRON)
@ -108,10 +101,22 @@
SPC5_ME_MC_IRCON | \ SPC5_ME_MC_IRCON | \
SPC5_ME_MC_XOSC0ON | \ SPC5_ME_MC_XOSC0ON | \
SPC5_ME_MC_PLL0ON | \ SPC5_ME_MC_PLL0ON | \
SPC5_ME_MC_PLL1ON | \
SPC5_ME_MC_CFLAON_NORMAL | \ SPC5_ME_MC_CFLAON_NORMAL | \
SPC5_ME_MC_DFLAON_NORMAL | \ SPC5_ME_MC_DFLAON_NORMAL | \
SPC5_ME_MC_MVRON) SPC5_ME_MC_MVRON)
#define SPC5_ME_RUN_PC0_BITS 0
#define SPC5_ME_RUN_PC1_BITS (SPC5_ME_RUN_PC_TEST | \
SPC5_ME_RUN_PC_SAFE | \
SPC5_ME_RUN_PC_DRUN | \
SPC5_ME_RUN_PC_RUN0 | \
SPC5_ME_RUN_PC_RUN1 | \
SPC5_ME_RUN_PC_RUN2 | \
SPC5_ME_RUN_PC_RUN3)
#define SPC5_ME_RUN_PC2_BITS (SPC5_ME_RUN_PC_DRUN | \
SPC5_ME_RUN_PC_RUN0 | \
SPC5_ME_RUN_PC_RUN1 | \
SPC5_ME_RUN_PC_RUN2 | \
SPC5_ME_RUN_PC_RUN3)
#define SPC5_ME_RUN_PC3_BITS (SPC5_ME_RUN_PC_RUN0 | \ #define SPC5_ME_RUN_PC3_BITS (SPC5_ME_RUN_PC_RUN0 | \
SPC5_ME_RUN_PC_RUN1 | \ SPC5_ME_RUN_PC_RUN1 | \
SPC5_ME_RUN_PC_RUN2 | \ SPC5_ME_RUN_PC_RUN2 | \
@ -132,6 +137,12 @@
SPC5_ME_RUN_PC_RUN1 | \ SPC5_ME_RUN_PC_RUN1 | \
SPC5_ME_RUN_PC_RUN2 | \ SPC5_ME_RUN_PC_RUN2 | \
SPC5_ME_RUN_PC_RUN3) SPC5_ME_RUN_PC_RUN3)
#define SPC5_ME_LP_PC0_BITS 0
#define SPC5_ME_LP_PC1_BITS (SPC5_ME_LP_PC_HALT0 | \
SPC5_ME_LP_PC_STOP0 | \
SPC5_ME_LP_PC_STANDBY0)
#define SPC5_ME_LP_PC2_BITS (SPC5_ME_LP_PC_HALT0)
#define SPC5_ME_LP_PC3_BITS (SPC5_ME_LP_PC_STOP0)
#define SPC5_ME_LP_PC4_BITS (SPC5_ME_LP_PC_HALT0 | \ #define SPC5_ME_LP_PC4_BITS (SPC5_ME_LP_PC_HALT0 | \
SPC5_ME_LP_PC_STOP0) SPC5_ME_LP_PC_STOP0)
#define SPC5_ME_LP_PC5_BITS (SPC5_ME_LP_PC_HALT0 | \ #define SPC5_ME_LP_PC5_BITS (SPC5_ME_LP_PC_HALT0 | \
@ -140,7 +151,7 @@
SPC5_ME_LP_PC_STOP0) SPC5_ME_LP_PC_STOP0)
#define SPC5_ME_LP_PC7_BITS (SPC5_ME_LP_PC_HALT0 | \ #define SPC5_ME_LP_PC7_BITS (SPC5_ME_LP_PC_HALT0 | \
SPC5_ME_LP_PC_STOP0) SPC5_ME_LP_PC_STOP0)
#define SPC5_PIT3_IRQ_PRIORITY 4 #define SPC5_PIT0_IRQ_PRIORITY 4
/* /*
* SERIAL driver system settings. * SERIAL driver system settings.

9
demos/PPC-SPC560P-GCC/.cproject
View File

@ -23,20 +23,23 @@
<builder autoBuildTarget="all" cleanBuildTarget="clean" enableAutoBuild="false" enableCleanBuild="true" enabledIncrementalBuild="true" id="org.eclipse.cdt.build.core.settings.default.builder.1464300191" incrementalBuildTarget="all" keepEnvironmentInBuildfile="false" managedBuildOn="false" name="Gnu Make Builder" parallelBuildOn="true" parallelizationNumber="optimal" superClass="org.eclipse.cdt.build.core.settings.default.builder"/> <builder autoBuildTarget="all" cleanBuildTarget="clean" enableAutoBuild="false" enableCleanBuild="true" enabledIncrementalBuild="true" id="org.eclipse.cdt.build.core.settings.default.builder.1464300191" incrementalBuildTarget="all" keepEnvironmentInBuildfile="false" managedBuildOn="false" name="Gnu Make Builder" parallelBuildOn="true" parallelizationNumber="optimal" superClass="org.eclipse.cdt.build.core.settings.default.builder"/>
<tool id="org.eclipse.cdt.build.core.settings.holder.libs.2072938444" name="holder for library settings" superClass="org.eclipse.cdt.build.core.settings.holder.libs"/> <tool id="org.eclipse.cdt.build.core.settings.holder.libs.2072938444" name="holder for library settings" superClass="org.eclipse.cdt.build.core.settings.holder.libs"/>
<tool id="org.eclipse.cdt.build.core.settings.holder.891594876" name="Assembly" superClass="org.eclipse.cdt.build.core.settings.holder"> <tool id="org.eclipse.cdt.build.core.settings.holder.891594876" name="Assembly" superClass="org.eclipse.cdt.build.core.settings.holder">
<option id="org.eclipse.cdt.build.core.settings.holder.undef.incpaths.1086284041" superClass="org.eclipse.cdt.build.core.settings.holder.undef.incpaths" valueType="undefIncludePath"> <option id="org.eclipse.cdt.build.core.settings.holder.undef.incpaths.1086284041" name="Undefined Include Paths" superClass="org.eclipse.cdt.build.core.settings.holder.undef.incpaths" valueType="undefIncludePath">
<listOptionValue builtIn="false" value="C:/MinGW/lib/gcc/mingw32/3.4.5/include"/> <listOptionValue builtIn="false" value="C:/MinGW/lib/gcc/mingw32/3.4.5/include"/>
<listOptionValue builtIn="false" value="C:/MinGW/include"/>
</option> </option>
<inputType id="org.eclipse.cdt.build.core.settings.holder.inType.1668196245" languageId="org.eclipse.cdt.core.assembly" languageName="Assembly" sourceContentType="org.eclipse.cdt.core.asmSource" superClass="org.eclipse.cdt.build.core.settings.holder.inType"/> <inputType id="org.eclipse.cdt.build.core.settings.holder.inType.1668196245" languageId="org.eclipse.cdt.core.assembly" languageName="Assembly" sourceContentType="org.eclipse.cdt.core.asmSource" superClass="org.eclipse.cdt.build.core.settings.holder.inType"/>
</tool> </tool>
<tool id="org.eclipse.cdt.build.core.settings.holder.508413348" name="GNU C++" superClass="org.eclipse.cdt.build.core.settings.holder"> <tool id="org.eclipse.cdt.build.core.settings.holder.508413348" name="GNU C++" superClass="org.eclipse.cdt.build.core.settings.holder">
<option id="org.eclipse.cdt.build.core.settings.holder.undef.incpaths.1266436465" superClass="org.eclipse.cdt.build.core.settings.holder.undef.incpaths" valueType="undefIncludePath"> <option id="org.eclipse.cdt.build.core.settings.holder.undef.incpaths.1266436465" name="Undefined Include Paths" superClass="org.eclipse.cdt.build.core.settings.holder.undef.incpaths" valueType="undefIncludePath">
<listOptionValue builtIn="false" value="C:/MinGW/lib/gcc/mingw32/3.4.5/include"/> <listOptionValue builtIn="false" value="C:/MinGW/lib/gcc/mingw32/3.4.5/include"/>
<listOptionValue builtIn="false" value="C:/MinGW/include"/>
</option> </option>
<inputType id="org.eclipse.cdt.build.core.settings.holder.inType.729232331" languageId="org.eclipse.cdt.core.g++" languageName="GNU C++" sourceContentType="org.eclipse.cdt.core.cxxSource,org.eclipse.cdt.core.cxxHeader" superClass="org.eclipse.cdt.build.core.settings.holder.inType"/> <inputType id="org.eclipse.cdt.build.core.settings.holder.inType.729232331" languageId="org.eclipse.cdt.core.g++" languageName="GNU C++" sourceContentType="org.eclipse.cdt.core.cxxSource,org.eclipse.cdt.core.cxxHeader" superClass="org.eclipse.cdt.build.core.settings.holder.inType"/>
</tool> </tool>
<tool id="org.eclipse.cdt.build.core.settings.holder.1152877925" name="GNU C" superClass="org.eclipse.cdt.build.core.settings.holder"> <tool id="org.eclipse.cdt.build.core.settings.holder.1152877925" name="GNU C" superClass="org.eclipse.cdt.build.core.settings.holder">
<option id="org.eclipse.cdt.build.core.settings.holder.undef.incpaths.112826565" superClass="org.eclipse.cdt.build.core.settings.holder.undef.incpaths" valueType="undefIncludePath"> <option id="org.eclipse.cdt.build.core.settings.holder.undef.incpaths.112826565" name="Undefined Include Paths" superClass="org.eclipse.cdt.build.core.settings.holder.undef.incpaths" valueType="undefIncludePath">
<listOptionValue builtIn="false" value="C:/MinGW/lib/gcc/mingw32/3.4.5/include"/> <listOptionValue builtIn="false" value="C:/MinGW/lib/gcc/mingw32/3.4.5/include"/>
<listOptionValue builtIn="false" value="C:/MinGW/include"/>
</option> </option>
<inputType id="org.eclipse.cdt.build.core.settings.holder.inType.88733268" languageId="org.eclipse.cdt.core.gcc" languageName="GNU C" sourceContentType="org.eclipse.cdt.core.cSource,org.eclipse.cdt.core.cHeader" superClass="org.eclipse.cdt.build.core.settings.holder.inType"/> <inputType id="org.eclipse.cdt.build.core.settings.holder.inType.88733268" languageId="org.eclipse.cdt.core.gcc" languageName="GNU C" sourceContentType="org.eclipse.cdt.core.cSource,org.eclipse.cdt.core.cHeader" superClass="org.eclipse.cdt.build.core.settings.holder.inType"/>
</tool> </tool>

34
os/hal/platforms/SPC560BCxx/hal_lld.c
View File

@ -79,7 +79,7 @@ void hal_lld_init(void) {
/* The system is switched to the RUN0 mode, the default for normal /* The system is switched to the RUN0 mode, the default for normal
operations.*/ operations.*/
if (halSPC560PSetRunMode(SPC5_RUNMODE_RUN0) == CH_FAILED) if (halSPCSetRunMode(SPC5_RUNMODE_RUN0) == CH_FAILED)
chSysHalt(); chSysHalt();
/* INTC initialization, software vector mode, 4 bytes vectors, starting /* INTC initialization, software vector mode, 4 bytes vectors, starting
@ -91,10 +91,10 @@ void hal_lld_init(void) {
/* PIT channel 3 initialization for Kernel ticks, the PIT is configured /* PIT channel 3 initialization for Kernel ticks, the PIT is configured
to run in DRUN,RUN0...RUN3 and HALT0 modes, the clock is gated in other to run in DRUN,RUN0...RUN3 and HALT0 modes, the clock is gated in other
modes.*/ modes.*/
INTC.PSR[127].R = SPC5_PIT3_IRQ_PRIORITY; INTC.PSR[127].R = SPC5_PIT0_IRQ_PRIORITY;
halSPC560PSetPeripheralClockMode(92, halSPCSetPeripheralClockMode(92,
SPC5_ME_PCTL_RUN(2) | SPC5_ME_PCTL_LP(2)); SPC5_ME_PCTL_RUN(2) | SPC5_ME_PCTL_LP(2));
reg = halSPC560PGetSystemClock() / CH_FREQUENCY - 1; reg = halSPCGetSystemClock() / CH_FREQUENCY - 1;
PIT.PITMCR.R = 1; /* PIT clock enabled, stop while debugging. */ PIT.PITMCR.R = 1; /* PIT clock enabled, stop while debugging. */
PIT.CH[3].LDVAL.R = reg; PIT.CH[3].LDVAL.R = reg;
PIT.CH[3].CVAL.R = reg; PIT.CH[3].CVAL.R = reg;
@ -110,10 +110,10 @@ void hal_lld_init(void) {
* *
* @special * @special
*/ */
void spc560p_clock_init(void) { void spc_clock_init(void) {
/* Waiting for IRC stabilization before attempting anything else.*/ /* Waiting for IRC stabilization before attempting anything else.*/
while (!ME.GS.B.S_RC) while (!ME.GS.B.S_FIRC)
; ;
#if !SPC5_NO_INIT #if !SPC5_NO_INIT
@ -125,14 +125,10 @@ void spc560p_clock_init(void) {
#endif /* SPC5_ENABLE_XOSC */ #endif /* SPC5_ENABLE_XOSC */
/* Initialization of the FMPLLs settings.*/ /* Initialization of the FMPLLs settings.*/
CGM.FMPLL[0].CR.R = SPC5_FMPLL0_ODF | CGM.FMPLL_CR.R = SPC5_FMPLL0_ODF |
((SPC5_FMPLL0_IDF_VALUE - 1) << 26) | ((SPC5_FMPLL0_IDF_VALUE - 1) << 26) |
(SPC5_FMPLL0_NDIV_VALUE << 16); (SPC5_FMPLL0_NDIV_VALUE << 16);
CGM.FMPLL[0].MR.R = 0; /* TODO: Add a setting. */ CGM.FMPLL_MR.R = 0; /* TODO: Add a setting. */
CGM.FMPLL[1].CR.R = SPC5_FMPLL1_ODF |
(SPC5_FMPLL1_IDF_VALUE << 26) |
(SPC5_FMPLL1_NDIV_VALUE << 16);
CGM.FMPLL[1].MR.R = 0; /* TODO: Add a setting. */
/* Run modes initialization.*/ /* Run modes initialization.*/
ME.MER.R = SPC5_ME_ME_BITS; /* Enabled run modes. */ ME.MER.R = SPC5_ME_ME_BITS; /* Enabled run modes. */
@ -166,7 +162,7 @@ void spc560p_clock_init(void) {
/* Switches again to DRUN mode (current mode) in order to update the /* Switches again to DRUN mode (current mode) in order to update the
settings.*/ settings.*/
if (halSPC560PSetRunMode(SPC5_RUNMODE_DRUN) == CH_FAILED) if (halSPCSetRunMode(SPC5_RUNMODE_DRUN) == CH_FAILED)
chSysHalt(); chSysHalt();
/* CFLASH settings calculated for a maximum clock of 64MHz.*/ /* CFLASH settings calculated for a maximum clock of 64MHz.*/
@ -187,7 +183,7 @@ void spc560p_clock_init(void) {
* @retval CH_SUCCESS if the switch operation has been completed. * @retval CH_SUCCESS if the switch operation has been completed.
* @retval CH_FAILED if the switch operation failed. * @retval CH_FAILED if the switch operation failed.
*/ */
bool_t halSPC560PSetRunMode(spc560prunmode_t mode) { bool_t halSPCSetRunMode(spc560prunmode_t mode) {
/* Starts a transition process.*/ /* Starts a transition process.*/
ME.MCTL.R = SPC5_ME_MCTL_MODE(mode) | SPC5_ME_MCTL_KEY; ME.MCTL.R = SPC5_ME_MCTL_MODE(mode) | SPC5_ME_MCTL_KEY;
@ -216,7 +212,7 @@ bool_t halSPC560PSetRunMode(spc560prunmode_t mode) {
* *
* @notapi * @notapi
*/ */
void halSPC560PSetPeripheralClockMode(uint32_t n, uint32_t pctl) { void halSPCSetPeripheralClockMode(uint32_t n, uint32_t pctl) {
uint32_t mode; uint32_t mode;
ME.PCTL[n].R = pctl; ME.PCTL[n].R = pctl;
@ -231,19 +227,21 @@ void halSPC560PSetPeripheralClockMode(uint32_t n, uint32_t pctl) {
* *
* @return The system clock in Hertz. * @return The system clock in Hertz.
*/ */
uint32_t halSPC560PGetSystemClock(void) { uint32_t halSPCGetSystemClock(void) {
uint32_t sysclk; uint32_t sysclk;
sysclk = ME.GS.B.S_SYSCLK; sysclk = ME.GS.B.S_SYSCLK;
switch (sysclk) { switch (sysclk) {
case SPC5_ME_GS_SYSCLK_IRC: case SPC5_ME_GS_SYSCLK_IRC:
return SPC5_IRC_CLK; return SPC5_IRC_CLK;
case SPC5_ME_GS_SYSCLK_DIVIRC:
return SPC5_IRC_CLK / SPC5_IRCDIV_VALUE;
case SPC5_ME_GS_SYSCLK_XOSC: case SPC5_ME_GS_SYSCLK_XOSC:
return SPC5_XOSC_CLK / SPC5_XOSCDIV_VALUE;
case SPC5_ME_GS_SYSCLK_DIVXOSC:
return SPC5_XOSC_CLK; return SPC5_XOSC_CLK;
case SPC5_ME_GS_SYSCLK_FMPLL0: case SPC5_ME_GS_SYSCLK_FMPLL0:
return SPC5_FMPLL0_CLK; return SPC5_FMPLL0_CLK;
case SPC5_ME_GS_SYSCLK_FMPLL1:
return SPC5_FMPLL1_CLK;
default: default:
return 0; return 0;
} }

210
os/hal/platforms/SPC560BCxx/hal_lld.h
View File

@ -34,8 +34,8 @@
#ifndef _HAL_LLD_H_ #ifndef _HAL_LLD_H_
#define _HAL_LLD_H_ #define _HAL_LLD_H_
#include "xpc560p.h" #include "xpc560bc.h"
#include "spc560p_registry.h" #include "spc560bc_registry.h"
/*===========================================================================*/ /*===========================================================================*/
/* Driver constants. */ /* Driver constants. */
@ -50,7 +50,7 @@
* @name Platform identification * @name Platform identification
* @{ * @{
*/ */
#define PLATFORM_NAME "SPC560Pxx Chassis and Safety" #define PLATFORM_NAME "SPC560B/Cxx Car Body and Convenience"
/** @} */ /** @} */
/** /**
@ -60,13 +60,23 @@
/** /**
* @brief Maximum XOSC clock frequency. * @brief Maximum XOSC clock frequency.
*/ */
#define SPC5_XOSC_CLK_MAX 40000000 #define SPC5_XOSC_CLK_MAX 16000000
/** /**
* @brief Minimum XOSC clock frequency. * @brief Minimum XOSC clock frequency.
*/ */
#define SPC5_XOSC_CLK_MIN 4000000 #define SPC5_XOSC_CLK_MIN 4000000
/**
* @brief Maximum SXOSC clock frequency.
*/
#define SPC5_SXOSC_CLK_MAX 40000
/**
* @brief Minimum SXOSC clock frequency.
*/
#define SPC5_SXOSC_CLK_MIN 32000
/** /**
* @brief Maximum FMPLLs input clock frequency. * @brief Maximum FMPLLs input clock frequency.
*/ */
@ -75,7 +85,7 @@
/** /**
* @brief Maximum FMPLLs input clock frequency. * @brief Maximum FMPLLs input clock frequency.
*/ */
#define SPC5_FMPLLIN_MAX 16000000 #define SPC5_FMPLLIN_MAX 64000000
/** /**
* @brief Maximum FMPLLs VCO clock frequency. * @brief Maximum FMPLLs VCO clock frequency.
@ -91,23 +101,16 @@
* @brief Maximum FMPLL0 output clock frequency. * @brief Maximum FMPLL0 output clock frequency.
*/ */
#define SPC5_FMPLL0_CLK_MAX 64000000 #define SPC5_FMPLL0_CLK_MAX 64000000
/**
* @brief Maximum FMPLL1 output clock frequency.
*/
#define SPC5_FMPLL1_CLK_MAX 120000000
/**
* @brief Maximum FMPLL1 1D1 output clock frequency.
*/
#define SPC5_FMPLL1_1D1_CLK_MAX 80000000
/** @} */ /** @} */
/** /**
* @name Internal clock sources * @name Internal clock sources
* @{ * @{
*/ */
#define SPC5_IRC_CLK 16000000 /**< Internal RC oscillator.*/ #define SPC5_IRC_CLK 16000000 /**< Internal fast RC
oscillator. */
#define SPC5_SIRC_CLK 128000 /**< Internal RC slow
oscillator. */
/** @} */ /** @} */
/** /**
@ -126,9 +129,10 @@
*/ */
#define SPC5_ME_GS_SYSCLK_MASK (15U << 0) #define SPC5_ME_GS_SYSCLK_MASK (15U << 0)
#define SPC5_ME_GS_SYSCLK_IRC (0U << 0) #define SPC5_ME_GS_SYSCLK_IRC (0U << 0)
#define SPC5_ME_GS_SYSCLK_DIVIRC (1U << 0)
#define SPC5_ME_GS_SYSCLK_XOSC (2U << 0) #define SPC5_ME_GS_SYSCLK_XOSC (2U << 0)
#define SPC5_ME_GS_SYSCLK_DIVXOSC (3U << 0)
#define SPC5_ME_GS_SYSCLK_FMPLL0 (4U << 0) #define SPC5_ME_GS_SYSCLK_FMPLL0 (4U << 0)
#define SPC5_ME_GS_SYSCLK_FMPLL1 (5U << 0)
/** @} */ /** @} */
/** /**
@ -136,15 +140,16 @@
* @{ * @{
*/ */
#define SPC5_ME_ME_RESET (1U << 0) #define SPC5_ME_ME_RESET (1U << 0)
#define SPC5_ME_ME_TEST (2U << 0) #define SPC5_ME_ME_TEST (1U << 1)
#define SPC5_ME_ME_SAFE (4U << 0) #define SPC5_ME_ME_SAFE (1U << 2)
#define SPC5_ME_ME_DRUN (8U << 0) #define SPC5_ME_ME_DRUN (1U << 3)
#define SPC5_ME_ME_RUN0 (16U << 0) #define SPC5_ME_ME_RUN0 (1U << 4)
#define SPC5_ME_ME_RUN1 (32U << 0) #define SPC5_ME_ME_RUN1 (1U << 5)
#define SPC5_ME_ME_RUN2 (64U << 0) #define SPC5_ME_ME_RUN2 (1U << 6)
#define SPC5_ME_ME_RUN3 (128U << 0) #define SPC5_ME_ME_RUN3 (1U << 7)
#define SPC5_ME_ME_HALT0 (256U << 0) #define SPC5_ME_ME_HALT0 (1U << 8)
#define SPC5_ME_ME_STOP0 (1024U << 0) #define SPC5_ME_ME_STOP0 (1U << 10)
#define SPC5_ME_ME_STANDBY0 (1U << 13)
/** @} */ /** @} */
/** /**
@ -153,15 +158,15 @@
*/ */
#define SPC5_ME_MC_SYSCLK_MASK (15U << 0) #define SPC5_ME_MC_SYSCLK_MASK (15U << 0)
#define SPC5_ME_MC_SYSCLK(n) ((n) << 0) #define SPC5_ME_MC_SYSCLK(n) ((n) << 0)
#define SPC5_ME_MC_SYSCLK_IRC SPC5_ME_MC_SYSCLK(0) #define SPC5_ME_MC_SYSCLK_IRC SPC5_ME_MC_SYSCLK(0)
#define SPC5_ME_MC_SYSCLK_XOSC SPC5_ME_MC_SYSCLK(2) #define SPC5_ME_MC_SYSCLK_DIVIRC SPC5_ME_MC_SYSCLK(1)
#define SPC5_ME_MC_SYSCLK_FMPLL0 SPC5_ME_MC_SYSCLK(4) #define SPC5_ME_MC_SYSCLK_XOSC SPC5_ME_MC_SYSCLK(2)
#define SPC5_ME_MC_SYSCLK_FMPLL1 SPC5_ME_MC_SYSCLK(5) #define SPC5_ME_MC_SYSCLK_DIVXOSC SPC5_ME_MC_SYSCLK(3)
#define SPC5_ME_MC_SYSCLK_DISABLED SPC5_ME_MC_SYSCLK(15) #define SPC5_ME_MC_SYSCLK_FMPLL0 SPC5_ME_MC_SYSCLK(4)
#define SPC5_ME_MC_SYSCLK_DISABLED SPC5_ME_MC_SYSCLK(15)
#define SPC5_ME_MC_IRCON (1U << 4) #define SPC5_ME_MC_IRCON (1U << 4)
#define SPC5_ME_MC_XOSC0ON (1U << 5) #define SPC5_ME_MC_XOSC0ON (1U << 5)
#define SPC5_ME_MC_PLL0ON (1U << 6) #define SPC5_ME_MC_PLL0ON (1U << 6)
#define SPC5_ME_MC_PLL1ON (1U << 7)
#define SPC5_ME_MC_CFLAON_MASK (3U << 16) #define SPC5_ME_MC_CFLAON_MASK (3U << 16)
#define SPC5_ME_MC_CFLAON(n) ((n) << 16) #define SPC5_ME_MC_CFLAON(n) ((n) << 16)
#define SPC5_ME_MC_CFLAON_PD (1U << 16) #define SPC5_ME_MC_CFLAON_PD (1U << 16)
@ -205,6 +210,7 @@
*/ */
#define SPC5_ME_LP_PC_HALT0 (1U << 8) #define SPC5_ME_LP_PC_HALT0 (1U << 8)
#define SPC5_ME_LP_PC_STOP0 (1U << 10) #define SPC5_ME_LP_PC_STOP0 (1U << 10)
#define SPC5_ME_LP_PC_STANDBY0 (1U << 10)
/** @} */ /** @} */
/** /**
@ -226,62 +232,54 @@
* @brief Disables the clocks initialization in the HAL. * @brief Disables the clocks initialization in the HAL.
*/ */
#if !defined(SPC5_NO_INIT) || defined(__DOXYGEN__) #if !defined(SPC5_NO_INIT) || defined(__DOXYGEN__)
#define SPC5_NO_INIT FALSE #define SPC5_NO_INIT FALSE
#endif #endif
/** /**
* @brief Disables the overclock checks. * @brief Disables the overclock checks.
*/ */
#if !defined(SPC5_ALLOW_OVERCLOCK) || defined(__DOXYGEN__) #if !defined(SPC5_ALLOW_OVERCLOCK) || defined(__DOXYGEN__)
#define SPC5_ALLOW_OVERCLOCK FALSE #define SPC5_ALLOW_OVERCLOCK FALSE
#endif
/**
* @brief XOSC divider value.
* @note The allowed range is 1...32.
*/
#if !defined(SPC5_XOSCDIV_VALUE) || defined(__DOXYGEN__)
#define SPC5_XOSCDIV_VALUE 1
#endif
/**
* @brief Fast IRC divider value.
* @note The allowed range is 1...32.
*/
#if !defined(SPC5_IRCDIV_VALUE) || defined(__DOXYGEN__)
#define SPC5_IRCDIV_VALUE 1
#endif #endif
/** /**
* @brief FMPLL0 IDF divider value. * @brief FMPLL0 IDF divider value.
* @note The default value is calculated for XOSC=40MHz and PHI=64MHz. * @note The default value is calculated for XOSC=8MHz and PHI=64MHz.
*/ */
#if !defined(SPC5_FMPLL0_IDF_VALUE) || defined(__DOXYGEN__) #if !defined(SPC5_FMPLL0_IDF_VALUE) || defined(__DOXYGEN__)
#define SPC5_FMPLL0_IDF_VALUE 5 #define SPC5_FMPLL0_IDF_VALUE 1
#endif #endif
/** /**
* @brief FMPLL0 NDIV divider value. * @brief FMPLL0 NDIV divider value.
* @note The default value is calculated for XOSC=40MHz and PHI=64MHz. * @note The default value is calculated for XOSC=8MHz and PHI=64MHz.
*/ */
#if !defined(SPC5_FMPLL0_NDIV_VALUE) || defined(__DOXYGEN__) #if !defined(SPC5_FMPLL0_NDIV_VALUE) || defined(__DOXYGEN__)
#define SPC5_FMPLL0_NDIV_VALUE 32 #define SPC5_FMPLL0_NDIV_VALUE 32
#endif #endif
/** /**
* @brief FMPLL0 ODF divider value. * @brief FMPLL0 ODF divider value.
* @note The default value is calculated for XOSC=40MHz and PHI=64MHz. * @note The default value is calculated for XOSC=8MHz and PHI=64MHz.
*/ */
#if !defined(SPC5_FMPLL0_ODF) || defined(__DOXYGEN__) #if !defined(SPC5_FMPLL0_ODF) || defined(__DOXYGEN__)
#define SPC5_FMPLL0_ODF SPC5_FMPLL_ODF_DIV4 #define SPC5_FMPLL0_ODF SPC5_FMPLL_ODF_DIV4
#endif
/**
* @brief FMPLL1 IDF divider value.
* @note The default value is calculated for XOSC=40MHz and PHI=64MHz.
*/
#if !defined(SPC5_FMPLL1_IDF_VALUE) || defined(__DOXYGEN__)
#define SPC5_FMPLL1_IDF_VALUE 5
#endif
/**
* @brief FMPLL1 NDIV divider value.
* @note The default value is calculated for XOSC=40MHz and PHI=64MHz.
*/
#if !defined(SPC5_FMPLL1_NDIV_VALUE) || defined(__DOXYGEN__)
#define SPC5_FMPLL1_NDIV_VALUE 60
#endif
/**
* @brief FMPLL1 ODF divider value.
* @note The default value is calculated for XOSC=40MHz and PHI=64MHz.
*/
#if !defined(SPC5_FMPLL1_ODF) || defined(__DOXYGEN__)
#define SPC5_FMPLL1_ODF SPC5_FMPLL_ODF_DIV4
#endif #endif
/** /**
@ -294,7 +292,8 @@
SPC5_ME_ME_RUN2 | \ SPC5_ME_ME_RUN2 | \
SPC5_ME_ME_RUN3 | \ SPC5_ME_ME_RUN3 | \
SPC5_ME_ME_HALT0 | \ SPC5_ME_ME_HALT0 | \
SPC5_ME_ME_STOP0) SPC5_ME_ME_STOP0 | \
SPC5_ME_ME_STANDBY0)
#endif #endif
/** /**
@ -305,7 +304,6 @@
SPC5_ME_MC_IRCON | \ SPC5_ME_MC_IRCON | \
SPC5_ME_MC_XOSC0ON | \ SPC5_ME_MC_XOSC0ON | \
SPC5_ME_MC_PLL0ON | \ SPC5_ME_MC_PLL0ON | \
SPC5_ME_MC_PLL1ON | \
SPC5_ME_MC_CFLAON_NORMAL | \ SPC5_ME_MC_CFLAON_NORMAL | \
SPC5_ME_MC_DFLAON_NORMAL | \ SPC5_ME_MC_DFLAON_NORMAL | \
SPC5_ME_MC_MVRON) SPC5_ME_MC_MVRON)
@ -326,7 +324,6 @@
SPC5_ME_MC_IRCON | \ SPC5_ME_MC_IRCON | \
SPC5_ME_MC_XOSC0ON | \ SPC5_ME_MC_XOSC0ON | \
SPC5_ME_MC_PLL0ON | \ SPC5_ME_MC_PLL0ON | \
SPC5_ME_MC_PLL1ON | \
SPC5_ME_MC_CFLAON_NORMAL | \ SPC5_ME_MC_CFLAON_NORMAL | \
SPC5_ME_MC_DFLAON_NORMAL | \ SPC5_ME_MC_DFLAON_NORMAL | \
SPC5_ME_MC_MVRON) SPC5_ME_MC_MVRON)
@ -340,7 +337,6 @@
SPC5_ME_MC_IRCON | \ SPC5_ME_MC_IRCON | \
SPC5_ME_MC_XOSC0ON | \ SPC5_ME_MC_XOSC0ON | \
SPC5_ME_MC_PLL0ON | \ SPC5_ME_MC_PLL0ON | \
SPC5_ME_MC_PLL1ON | \
SPC5_ME_MC_CFLAON_NORMAL | \ SPC5_ME_MC_CFLAON_NORMAL | \
SPC5_ME_MC_DFLAON_NORMAL | \ SPC5_ME_MC_DFLAON_NORMAL | \
SPC5_ME_MC_MVRON) SPC5_ME_MC_MVRON)
@ -354,7 +350,6 @@
SPC5_ME_MC_IRCON | \ SPC5_ME_MC_IRCON | \
SPC5_ME_MC_XOSC0ON | \ SPC5_ME_MC_XOSC0ON | \
SPC5_ME_MC_PLL0ON | \ SPC5_ME_MC_PLL0ON | \
SPC5_ME_MC_PLL1ON | \
SPC5_ME_MC_CFLAON_NORMAL | \ SPC5_ME_MC_CFLAON_NORMAL | \
SPC5_ME_MC_DFLAON_NORMAL | \ SPC5_ME_MC_DFLAON_NORMAL | \
SPC5_ME_MC_MVRON) SPC5_ME_MC_MVRON)
@ -368,7 +363,6 @@
SPC5_ME_MC_IRCON | \ SPC5_ME_MC_IRCON | \
SPC5_ME_MC_XOSC0ON | \ SPC5_ME_MC_XOSC0ON | \
SPC5_ME_MC_PLL0ON | \ SPC5_ME_MC_PLL0ON | \
SPC5_ME_MC_PLL1ON | \
SPC5_ME_MC_CFLAON_NORMAL | \ SPC5_ME_MC_CFLAON_NORMAL | \
SPC5_ME_MC_DFLAON_NORMAL | \ SPC5_ME_MC_DFLAON_NORMAL | \
SPC5_ME_MC_MVRON) SPC5_ME_MC_MVRON)
@ -382,7 +376,6 @@
SPC5_ME_MC_IRCON | \ SPC5_ME_MC_IRCON | \
SPC5_ME_MC_XOSC0ON | \ SPC5_ME_MC_XOSC0ON | \
SPC5_ME_MC_PLL0ON | \ SPC5_ME_MC_PLL0ON | \
SPC5_ME_MC_PLL1ON | \
SPC5_ME_MC_CFLAON_NORMAL | \ SPC5_ME_MC_CFLAON_NORMAL | \
SPC5_ME_MC_DFLAON_NORMAL | \ SPC5_ME_MC_DFLAON_NORMAL | \
SPC5_ME_MC_MVRON) SPC5_ME_MC_MVRON)
@ -396,7 +389,6 @@
SPC5_ME_MC_IRCON | \ SPC5_ME_MC_IRCON | \
SPC5_ME_MC_XOSC0ON | \ SPC5_ME_MC_XOSC0ON | \
SPC5_ME_MC_PLL0ON | \ SPC5_ME_MC_PLL0ON | \
SPC5_ME_MC_PLL1ON | \
SPC5_ME_MC_CFLAON_NORMAL | \ SPC5_ME_MC_CFLAON_NORMAL | \
SPC5_ME_MC_DFLAON_NORMAL | \ SPC5_ME_MC_DFLAON_NORMAL | \
SPC5_ME_MC_MVRON) SPC5_ME_MC_MVRON)
@ -410,7 +402,6 @@
SPC5_ME_MC_IRCON | \ SPC5_ME_MC_IRCON | \
SPC5_ME_MC_XOSC0ON | \ SPC5_ME_MC_XOSC0ON | \
SPC5_ME_MC_PLL0ON | \ SPC5_ME_MC_PLL0ON | \
SPC5_ME_MC_PLL1ON | \
SPC5_ME_MC_CFLAON_NORMAL | \ SPC5_ME_MC_CFLAON_NORMAL | \
SPC5_ME_MC_DFLAON_NORMAL | \ SPC5_ME_MC_DFLAON_NORMAL | \
SPC5_ME_MC_MVRON) SPC5_ME_MC_MVRON)
@ -524,7 +515,8 @@
*/ */
#if !defined(SPC5_ME_LP_PC1_BITS) || defined(__DOXYGEN__) #if !defined(SPC5_ME_LP_PC1_BITS) || defined(__DOXYGEN__)
#define SPC5_ME_LP_PC1_BITS (SPC5_ME_LP_PC_HALT0 | \ #define SPC5_ME_LP_PC1_BITS (SPC5_ME_LP_PC_HALT0 | \
SPC5_ME_LP_PC_STOP0) SPC5_ME_LP_PC_STOP0 | \
SPC5_ME_LP_PC_STANDBY0)
#endif #endif
/** /**
@ -582,12 +574,12 @@
#endif #endif
/** /**
* @brief PIT channel 3 IRQ priority. * @brief PIT channel 0 IRQ priority.
* @note This PIT channel is allocated permanently for system tick * @note This PIT channel is allocated permanently for system tick
* generation. * generation.
*/ */
#if !defined(SPC5_PIT3_IRQ_PRIORITY) || defined(__DOXYGEN__) #if !defined(SPC5_PIT0_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define SPC5_PIT3_IRQ_PRIORITY 4 #define SPC5_PIT0_IRQ_PRIORITY 4
#endif #endif
/*===========================================================================*/ /*===========================================================================*/
@ -600,6 +592,16 @@
#error "invalid SPC5_XOSC_CLK value specified" #error "invalid SPC5_XOSC_CLK value specified"
#endif #endif
/* Check on the XOSC divider.*/
#if (SPC5_XOSCDIV_VALUE < 1) || (SPC5_XOSCDIV_VALUE > 32)
#error "invalid SPC5_XOSCDIV_VALUE value specified"
#endif
/* Check on the IRC divider.*/
#if (SPC5_IRCDIV_VALUE < 1) || (SPC5_IRCDIV_VALUE > 32)
#error "invalid SPC5_IRCDIV_VALUE value specified"
#endif
/* Check on SPC5_FMPLL0_IDF_VALUE.*/ /* Check on SPC5_FMPLL0_IDF_VALUE.*/
#if (SPC5_FMPLL0_IDF_VALUE < 1) || (SPC5_FMPLL0_IDF_VALUE > 15) #if (SPC5_FMPLL0_IDF_VALUE < 1) || (SPC5_FMPLL0_IDF_VALUE > 15)
#error "invalid SPC5_FMPLL0_IDF_VALUE value specified" #error "invalid SPC5_FMPLL0_IDF_VALUE value specified"
@ -646,52 +648,6 @@
#error "SPC5_FMPLL0_CLK outside acceptable range (0...SPC5_FMPLL0_CLK_MAX)" #error "SPC5_FMPLL0_CLK outside acceptable range (0...SPC5_FMPLL0_CLK_MAX)"
#endif #endif
/* Check on SPC5_FMPLL1_IDF_VALUE.*/
#if (SPC5_FMPLL1_IDF_VALUE < 1) || (SPC5_FMPLL1_IDF_VALUE > 15)
#error "invalid SPC5_FMPLL1_IDF_VALUE value specified"
#endif
/* Check on SPC5_FMPLL1_NDIV_VALUE.*/
#if (SPC5_FMPLL1_NDIV_VALUE < 32) || (SPC5_FMPLL1_NDIV_VALUE > 96)
#error "invalid SPC5_FMPLL1_NDIV_VALUE value specified"
#endif
/* Check on SPC5_FMPLL1_ODF.*/
#if (SPC5_FMPLL1_ODF == SPC5_FMPLL_ODF_DIV2)
#define SPC5_FMPLL1_ODF_VALUE 2
#elif (SPC5_FMPLL1_ODF == SPC5_FMPLL_ODF_DIV4)
#define SPC5_FMPLL1_ODF_VALUE 4
#elif (SPC5_FMPLL1_ODF == SPC5_FMPLL_ODF_DIV8)
#define SPC5_FMPLL1_ODF_VALUE 8
#elif (SPC5_FMPLL1_ODF == SPC5_FMPLL_ODF_DIV16)
#define SPC5_FMPLL1_ODF_VALUE 16
#else
#error "invalid SPC5_FMPLL1_ODF value specified"
#endif
/**
* @brief SPC5_FMPLL1_VCO_CLK clock point.
*/
#define SPC5_FMPLL1_VCO_CLK \
((SPC5_XOSC_CLK / SPC5_FMPLL1_IDF_VALUE) * SPC5_FMPLL1_NDIV_VALUE)
/* Check on FMPLL1 VCO output.*/
#if (SPC5_FMPLL1_VCO_CLK < SPC5_FMPLLVCO_MIN) || \
(SPC5_FMPLL1_VCO_CLK > SPC5_FMPLLVCO_MAX)
#error "SPC5_FMPLL1_CLK outside acceptable range (SPC5_FMPLLVCO_MIN...SPC5_FMPLLVCO_MAX)"
#endif
/**
* @brief SPC5_FMPLL1_CLK clock point.
*/
#define SPC5_FMPLL1_CLK \
(SPC5_FMPLL1_VCO_CLK / SPC5_FMPLL1_ODF_VALUE)
/* Check on SPC5_FMPLL1_CLK.*/
#if (SPC5_FMPLL1_CLK > SPC5_FMPLL1_CLK_MAX) && !SPC5_ALLOW_OVERCLOCK
#error "SPC5_FMPLL1_CLK outside acceptable range (0...SPC5_FMPLL1_CLK_MAX)"
#endif
/*===========================================================================*/ /*===========================================================================*/
/* Driver data structures and types. */ /* Driver data structures and types. */
/*===========================================================================*/ /*===========================================================================*/
@ -720,11 +676,11 @@ typedef enum {
extern "C" { extern "C" {
#endif #endif
void hal_lld_init(void); void hal_lld_init(void);
void spc560p_clock_init(void); void spc_clock_init(void);
bool_t halSPC560PSetRunMode(spc560prunmode_t mode); bool_t halSPCSetRunMode(spc560prunmode_t mode);
void halSPC560PSetPeripheralClockMode(uint32_t n, uint32_t pctl); void halSPCSetPeripheralClockMode(uint32_t n, uint32_t pctl);
#if !SPC5_NO_INIT #if !SPC5_NO_INIT
uint32_t halSPC560PGetSystemClock(void); uint32_t halSPCGetSystemClock(void);
#endif #endif
#ifdef __cplusplus #ifdef __cplusplus
} }

16
os/hal/platforms/SPC560Pxx/hal_lld.c
View File

@ -79,7 +79,7 @@ void hal_lld_init(void) {
/* The system is switched to the RUN0 mode, the default for normal /* The system is switched to the RUN0 mode, the default for normal
operations.*/ operations.*/
if (halSPC560PSetRunMode(SPC5_RUNMODE_RUN0) == CH_FAILED) if (halSPCSetRunMode(SPC5_RUNMODE_RUN0) == CH_FAILED)
chSysHalt(); chSysHalt();
/* INTC initialization, software vector mode, 4 bytes vectors, starting /* INTC initialization, software vector mode, 4 bytes vectors, starting
@ -92,9 +92,9 @@ void hal_lld_init(void) {
to run in DRUN,RUN0...RUN3 and HALT0 modes, the clock is gated in other to run in DRUN,RUN0...RUN3 and HALT0 modes, the clock is gated in other
modes.*/ modes.*/
INTC.PSR[127].R = SPC5_PIT3_IRQ_PRIORITY; INTC.PSR[127].R = SPC5_PIT3_IRQ_PRIORITY;
halSPC560PSetPeripheralClockMode(92, halSPCSetPeripheralClockMode(92,
SPC5_ME_PCTL_RUN(2) | SPC5_ME_PCTL_LP(2)); SPC5_ME_PCTL_RUN(2) | SPC5_ME_PCTL_LP(2));
reg = halSPC560PGetSystemClock() / CH_FREQUENCY - 1; reg = halSPCGetSystemClock() / CH_FREQUENCY - 1;
PIT.PITMCR.R = 1; /* PIT clock enabled, stop while debugging. */ PIT.PITMCR.R = 1; /* PIT clock enabled, stop while debugging. */
PIT.CH[3].LDVAL.R = reg; PIT.CH[3].LDVAL.R = reg;
PIT.CH[3].CVAL.R = reg; PIT.CH[3].CVAL.R = reg;
@ -110,7 +110,7 @@ void hal_lld_init(void) {
* *
* @special * @special
*/ */
void spc560p_clock_init(void) { void spc_clock_init(void) {
/* Waiting for IRC stabilization before attempting anything else.*/ /* Waiting for IRC stabilization before attempting anything else.*/
while (!ME.GS.B.S_RC) while (!ME.GS.B.S_RC)
@ -166,7 +166,7 @@ void spc560p_clock_init(void) {
/* Switches again to DRUN mode (current mode) in order to update the /* Switches again to DRUN mode (current mode) in order to update the
settings.*/ settings.*/
if (halSPC560PSetRunMode(SPC5_RUNMODE_DRUN) == CH_FAILED) if (halSPCSetRunMode(SPC5_RUNMODE_DRUN) == CH_FAILED)
chSysHalt(); chSysHalt();
/* CFLASH settings calculated for a maximum clock of 64MHz.*/ /* CFLASH settings calculated for a maximum clock of 64MHz.*/
@ -187,7 +187,7 @@ void spc560p_clock_init(void) {
* @retval CH_SUCCESS if the switch operation has been completed. * @retval CH_SUCCESS if the switch operation has been completed.
* @retval CH_FAILED if the switch operation failed. * @retval CH_FAILED if the switch operation failed.
*/ */
bool_t halSPC560PSetRunMode(spc560prunmode_t mode) { bool_t halSPCSetRunMode(spc560prunmode_t mode) {
/* Starts a transition process.*/ /* Starts a transition process.*/
ME.MCTL.R = SPC5_ME_MCTL_MODE(mode) | SPC5_ME_MCTL_KEY; ME.MCTL.R = SPC5_ME_MCTL_MODE(mode) | SPC5_ME_MCTL_KEY;
@ -216,7 +216,7 @@ bool_t halSPC560PSetRunMode(spc560prunmode_t mode) {
* *
* @notapi * @notapi
*/ */
void halSPC560PSetPeripheralClockMode(uint32_t n, uint32_t pctl) { void halSPCSetPeripheralClockMode(uint32_t n, uint32_t pctl) {
uint32_t mode; uint32_t mode;
ME.PCTL[n].R = pctl; ME.PCTL[n].R = pctl;
@ -231,7 +231,7 @@ void halSPC560PSetPeripheralClockMode(uint32_t n, uint32_t pctl) {
* *
* @return The system clock in Hertz. * @return The system clock in Hertz.
*/ */
uint32_t halSPC560PGetSystemClock(void) { uint32_t halSPCGetSystemClock(void) {
uint32_t sysclk; uint32_t sysclk;
sysclk = ME.GS.B.S_SYSCLK; sysclk = ME.GS.B.S_SYSCLK;

36
os/hal/platforms/SPC560Pxx/hal_lld.h
View File

@ -136,15 +136,15 @@
* @{ * @{
*/ */
#define SPC5_ME_ME_RESET (1U << 0) #define SPC5_ME_ME_RESET (1U << 0)
#define SPC5_ME_ME_TEST (2U << 0) #define SPC5_ME_ME_TEST (1U << 1)
#define SPC5_ME_ME_SAFE (4U << 0) #define SPC5_ME_ME_SAFE (1U << 2)
#define SPC5_ME_ME_DRUN (8U << 0) #define SPC5_ME_ME_DRUN (1U << 3)
#define SPC5_ME_ME_RUN0 (16U << 0) #define SPC5_ME_ME_RUN0 (1U << 4)
#define SPC5_ME_ME_RUN1 (32U << 0) #define SPC5_ME_ME_RUN1 (1U << 5)
#define SPC5_ME_ME_RUN2 (64U << 0) #define SPC5_ME_ME_RUN2 (1U << 6)
#define SPC5_ME_ME_RUN3 (128U << 0) #define SPC5_ME_ME_RUN3 (1U << 7)
#define SPC5_ME_ME_HALT0 (256U << 0) #define SPC5_ME_ME_HALT0 (1U << 8)
#define SPC5_ME_ME_STOP0 (1024U << 0) #define SPC5_ME_ME_STOP0 (1U << 10)
/** @} */ /** @} */
/** /**
@ -153,11 +153,11 @@
*/ */
#define SPC5_ME_MC_SYSCLK_MASK (15U << 0) #define SPC5_ME_MC_SYSCLK_MASK (15U << 0)
#define SPC5_ME_MC_SYSCLK(n) ((n) << 0) #define SPC5_ME_MC_SYSCLK(n) ((n) << 0)
#define SPC5_ME_MC_SYSCLK_IRC SPC5_ME_MC_SYSCLK(0) #define SPC5_ME_MC_SYSCLK_IRC SPC5_ME_MC_SYSCLK(0)
#define SPC5_ME_MC_SYSCLK_XOSC SPC5_ME_MC_SYSCLK(2) #define SPC5_ME_MC_SYSCLK_XOSC SPC5_ME_MC_SYSCLK(2)
#define SPC5_ME_MC_SYSCLK_FMPLL0 SPC5_ME_MC_SYSCLK(4) #define SPC5_ME_MC_SYSCLK_FMPLL0 SPC5_ME_MC_SYSCLK(4)
#define SPC5_ME_MC_SYSCLK_FMPLL1 SPC5_ME_MC_SYSCLK(5) #define SPC5_ME_MC_SYSCLK_FMPLL1 SPC5_ME_MC_SYSCLK(5)
#define SPC5_ME_MC_SYSCLK_DISABLED SPC5_ME_MC_SYSCLK(15) #define SPC5_ME_MC_SYSCLK_DISABLED SPC5_ME_MC_SYSCLK(15)
#define SPC5_ME_MC_IRCON (1U << 4) #define SPC5_ME_MC_IRCON (1U << 4)
#define SPC5_ME_MC_XOSC0ON (1U << 5) #define SPC5_ME_MC_XOSC0ON (1U << 5)
#define SPC5_ME_MC_PLL0ON (1U << 6) #define SPC5_ME_MC_PLL0ON (1U << 6)
@ -720,11 +720,11 @@ typedef enum {
extern "C" { extern "C" {
#endif #endif
void hal_lld_init(void); void hal_lld_init(void);
void spc560p_clock_init(void); void spc_clock_init(void);
bool_t halSPC560PSetRunMode(spc560prunmode_t mode); bool_t halSPCSetRunMode(spc560prunmode_t mode);
void halSPC560PSetPeripheralClockMode(uint32_t n, uint32_t pctl); void halSPCSetPeripheralClockMode(uint32_t n, uint32_t pctl);
#if !SPC5_NO_INIT #if !SPC5_NO_INIT
uint32_t halSPC560PGetSystemClock(void); uint32_t halSPCGetSystemClock(void);
#endif #endif
#ifdef __cplusplus #ifdef __cplusplus
} }

18
os/hal/platforms/SPC5xx/LINFlex_v1/serial_lld.c
View File

@ -97,7 +97,7 @@ static void spc5_linflex_init(SerialDriver *sdp, const SerialConfig *config) {
parameters.*/ parameters.*/
linflexp->UARTCR.R = SPC5_UARTCR_UART; /* UART mode FIRST. */ linflexp->UARTCR.R = SPC5_UARTCR_UART; /* UART mode FIRST. */
linflexp->UARTCR.R = SPC5_UARTCR_UART | SPC5_UARTCR_RXEN | config->mode; linflexp->UARTCR.R = SPC5_UARTCR_UART | SPC5_UARTCR_RXEN | config->mode;
div = halSPC560PGetSystemClock() / config->speed; div = halSPCGetSystemClock() / config->speed;
linflexp->LINFBRR.R = (uint16_t)(div & 15); /* Fractional divider. */ linflexp->LINFBRR.R = (uint16_t)(div & 15); /* Fractional divider. */
linflexp->LINIBRR.R = (uint16_t)(div >> 4); /* Integer divider. */ linflexp->LINIBRR.R = (uint16_t)(div >> 4); /* Integer divider. */
linflexp->UARTSR.R = 0xFFFF; /* Clearing UARTSR register.*/ linflexp->UARTSR.R = 0xFFFF; /* Clearing UARTSR register.*/
@ -363,14 +363,14 @@ void sd_lld_start(SerialDriver *sdp, const SerialConfig *config) {
if (sdp->state == SD_STOP) { if (sdp->state == SD_STOP) {
#if SPC5_SERIAL_USE_LINFLEX0 #if SPC5_SERIAL_USE_LINFLEX0
if (&SD1 == sdp) { if (&SD1 == sdp) {
halSPC560PSetPeripheralClockMode(SPC5_LINFLEX0_PCTL, halSPCSetPeripheralClockMode(SPC5_LINFLEX0_PCTL,
SPC5_SERIAL_LINFLEX0_START_PCTL); SPC5_SERIAL_LINFLEX0_START_PCTL);
} }
#endif #endif
#if SPC5_SERIAL_USE_LINFLEX1 #if SPC5_SERIAL_USE_LINFLEX1
if (&SD2 == sdp) { if (&SD2 == sdp) {
halSPC560PSetPeripheralClockMode(SPC5_LINFLEX1_PCTL, halSPCSetPeripheralClockMode(SPC5_LINFLEX1_PCTL,
SPC5_SERIAL_LINFLEX1_START_PCTL); SPC5_SERIAL_LINFLEX1_START_PCTL);
} }
#endif #endif
} }
@ -391,15 +391,15 @@ void sd_lld_stop(SerialDriver *sdp) {
#if SPC5_SERIAL_USE_LINFLEX0 #if SPC5_SERIAL_USE_LINFLEX0
if (&SD1 == sdp) { if (&SD1 == sdp) {
halSPC560PSetPeripheralClockMode(SPC5_LINFLEX0_PCTL, halSPCSetPeripheralClockMode(SPC5_LINFLEX0_PCTL,
SPC5_SERIAL_LINFLEX0_STOP_PCTL); SPC5_SERIAL_LINFLEX0_STOP_PCTL);
return; return;
} }
#endif #endif
#if SPC5_SERIAL_USE_LINFLEX1 #if SPC5_SERIAL_USE_LINFLEX1
if (&SD2 == sdp) { if (&SD2 == sdp) {
halSPC560PSetPeripheralClockMode(SPC5_LINFLEX1_PCTL, halSPCSetPeripheralClockMode(SPC5_LINFLEX1_PCTL,
SPC5_SERIAL_LINFLEX1_STOP_PCTL); SPC5_SERIAL_LINFLEX1_STOP_PCTL);
return; return;
} }
#endif #endif

4
os/hal/platforms/SPC5xx/SIUL_v1/pal_lld.h
View File

@ -153,7 +153,7 @@ typedef struct {
uint8_t pcr_index; uint8_t pcr_index;
uint8_t gpdo_value; uint8_t gpdo_value;
iomode_t pcr_value; iomode_t pcr_value;
} spc560p_siu_init_t; } spc_siu_init_t;
/** /**
* @brief Generic I/O ports static initializer. * @brief Generic I/O ports static initializer.
@ -166,7 +166,7 @@ typedef struct {
*/ */
typedef struct { typedef struct {
iomode_t default_mode; iomode_t default_mode;
const spc560p_siu_init_t *inits; const spc_siu_init_t *inits;
const uint8_t *padsels; const uint8_t *padsels;
} PALConfig; } PALConfig;