diff --git a/os/hal/ports/STM32/LLD/ADCv5/hal_adc_lld.c b/os/hal/ports/STM32/LLD/ADCv5/hal_adc_lld.c index f8a44e355..d4d52a017 100644 --- a/os/hal/ports/STM32/LLD/ADCv5/hal_adc_lld.c +++ b/os/hal/ports/STM32/LLD/ADCv5/hal_adc_lld.c @@ -293,12 +293,17 @@ void adc_lld_start_conversion(ADCDriver *adcp) { /* ADC setup, if it is defined a callback for the analog watch dog then it is enabled.*/ - adcp->adc->ISR = adcp->adc->ISR; - adcp->adc->IER = ADC_IER_OVRIE | - ADC_IER_AWD1IE | ADC_IER_AWD2IE | ADC_IER_AWD3IE; - adcp->adc->TR1 = grpp->tr1; - adcp->adc->TR2 = grpp->tr2; - adcp->adc->TR3 = grpp->tr3; + adcp->adc->ISR = adcp->adc->ISR; + if (grpp->error_cb != NULL) { + adcp->adc->IER = ADC_IER_OVRIE | ADC_IER_AWD1IE + | ADC_IER_AWD2IE + | ADC_IER_AWD3IE; + adcp->adc->TR1 = grpp->tr1; + adcp->adc->TR2 = grpp->tr2; + adcp->adc->TR3 = grpp->tr3; + adcp->adc->AWD2CR = grpp->awd2cr; + adcp->adc->AWD3CR = grpp->awd3cr; + } adcp->adc->SMPR = grpp->smpr; adcp->adc->CHSELR = grpp->chselr; @@ -333,7 +338,7 @@ void adc_lld_stop_conversion(ADCDriver *adcp) { void adc_lld_serve_interrupt(ADCDriver *adcp) { uint32_t isr; - isr = adcp->adc->ISR & adcp->adc->IER; + isr = adcp->adc->ISR; adcp->adc->ISR = isr; /* It could be a spurious interrupt caused by overflows after DMA disabling, diff --git a/os/hal/ports/STM32/LLD/ADCv5/hal_adc_lld.h b/os/hal/ports/STM32/LLD/ADCv5/hal_adc_lld.h index 0bcebd8c4..45ea1e036 100644 --- a/os/hal/ports/STM32/LLD/ADCv5/hal_adc_lld.h +++ b/os/hal/ports/STM32/LLD/ADCv5/hal_adc_lld.h @@ -89,11 +89,43 @@ /** @} */ /** - * @name Threashold registers initializer + * @name CHSELR register initializers for CHSELRMOD=0 + * @{ + */ +#define ADC_CHSELR_CHSEL_N(n) (1U << (n)) +/** @} */ + +/** + * @name CHSELR register initializers for CHSELRMOD=1 + * @{ + */ +#define ADC_CHSELR_SQ1_N(n) ((uint32_t)(n) << 0U) +#define ADC_CHSELR_SQ2_N(n) ((uint32_t)(n) << 4U) +#define ADC_CHSELR_SQ3_N(n) ((uint32_t)(n) << 8U) +#define ADC_CHSELR_SQ4_N(n) ((uint32_t)(n) << 12U) +#define ADC_CHSELR_SQ5_N(n) ((uint32_t)(n) << 16U) +#define ADC_CHSELR_SQ6_N(n) ((uint32_t)(n) << 20U) +#define ADC_CHSELR_SQ7_N(n) ((uint32_t)(n) << 24U) +#define ADC_CHSELR_SQ8_N(n) ((uint32_t)(n) << 28U) + +#define ADC_CHSELR_SQ1_END (15U << 0U) +#define ADC_CHSELR_SQ2_END (15U << 4U) +#define ADC_CHSELR_SQ3_END (15U << 8U) +#define ADC_CHSELR_SQ4_END (15U << 12U) +#define ADC_CHSELR_SQ5_END (15U << 16U) +#define ADC_CHSELR_SQ6_END (15U << 20U) +#define ADC_CHSELR_SQ7_END (15U << 24U) +#define ADC_CHSELR_SQ8_END (15U << 28U) +/** @} */ + +/** + * @name Threshold registers initializers * @{ */ #define ADC_TR(low, high) (((uint32_t)(high) << 16U) | \ (uint32_t)(low)) +#define ADC_TR_DISABLED ADC_TR(0U, 0x0FFFU) +#define ADC_AWDCR_ENABLE(n) (1U << (n)) /** @} */ /*===========================================================================*/ @@ -313,6 +345,10 @@ typedef enum { uint32_t tr2; \ /* ADC TR3 register initialization data.*/ \ uint32_t tr3; \ + /* ADC AWD2CR register initialization data.*/ \ + uint32_t awd2cr; \ + /* ADC AWD3CR register initialization data.*/ \ + uint32_t awd3cr; \ /* ADC SMPR register initialization data.*/ \ uint32_t smpr; \ /* ADC CHSELR register initialization data. \ diff --git a/testhal/STM32/STM32F3xx/ADC_DUAL/main.c b/testhal/STM32/STM32F3xx/ADC_DUAL/main.c index 6518965c8..ded0af4e1 100644 --- a/testhal/STM32/STM32F3xx/ADC_DUAL/main.c +++ b/testhal/STM32/STM32F3xx/ADC_DUAL/main.c @@ -52,28 +52,32 @@ static void adcerrorcallback(ADCDriver *adcp, adcerror_t err) { * Channels: IN7, IN8. */ static const ADCConversionGroup adcgrpcfg1 = { - FALSE, - ADC_GRP1_NUM_CHANNELS, - NULL, - adcerrorcallback, - ADC_CFGR_CONT, /* CFGR */ - ADC_TR(0, 4095), /* TR1 */ - ADC_CCR_DUAL_FIELD(1), /* CCR */ - { /* SMPR[2] */ + .circular = false, + .num_channels = ADC_GRP1_NUM_CHANNELS, + .end_cb = NULL, + .error_cb = adcerrorcallback, + .cfgr = ADC_CFGR_CONT, + .tr1 = ADC_TR_DISABLED, + .tr2 = ADC_TR_DISABLED, + .tr3 = ADC_TR_DISABLED, + .awd2cr = 0U, + .awd3cr = 0U, + .ccr = ADC_CCR_DUAL_FIELD(1), + .smpr = { 0, 0 }, - { /* SQR[4] */ + .sqr = { ADC_SQR1_SQ1_N(ADC_CHANNEL_IN7) | ADC_SQR1_SQ2_N(ADC_CHANNEL_IN8), 0, 0, 0 }, - { /* SSMPR[2] */ + .ssmpr = { 0, 0 }, - { /* SSQR[4] */ + .ssqr = { ADC_SQR1_SQ1_N(ADC_CHANNEL_IN8) | ADC_SQR1_SQ2_N(ADC_CHANNEL_IN7), 0, 0, @@ -87,20 +91,24 @@ static const ADCConversionGroup adcgrpcfg1 = { * Channels: IN7, IN8, IN7, IN8, IN7, IN8, Sensor, VBat/2. */ static const ADCConversionGroup adcgrpcfg2 = { - TRUE, - ADC_GRP2_NUM_CHANNELS, - adccallback, - adcerrorcallback, - ADC_CFGR_CONT, /* CFGR */ - ADC_TR(0, 4095), /* TR1 */ - ADC_CCR_DUAL_FIELD(1) | ADC_CCR_TSEN | ADC_CCR_VBATEN, /* CCR */ - { /* SMPR[2] */ + .circular = true, + .num_channels = ADC_GRP2_NUM_CHANNELS, + .end_cb = adccallback, + .error_cb = adcerrorcallback, + .cfgr = ADC_CFGR_CONT, + .tr1 = ADC_TR_DISABLED, + .tr2 = ADC_TR_DISABLED, + .tr3 = ADC_TR_DISABLED, + .awd2cr = 0U, + .awd3cr = 0U, + .ccr = ADC_CCR_DUAL_FIELD(1) | ADC_CCR_TSEN | ADC_CCR_VBATEN, + .smpr = { ADC_SMPR1_SMP_AN7(ADC_SMPR_SMP_19P5) | ADC_SMPR1_SMP_AN8(ADC_SMPR_SMP_19P5), ADC_SMPR2_SMP_AN16(ADC_SMPR_SMP_61P5) | ADC_SMPR2_SMP_AN17(ADC_SMPR_SMP_61P5), }, - { /* SQR[4] */ + .sqr = { ADC_SQR1_SQ1_N(ADC_CHANNEL_IN7) | ADC_SQR1_SQ2_N(ADC_CHANNEL_IN8) | ADC_SQR1_SQ3_N(ADC_CHANNEL_IN7) | ADC_SQR1_SQ4_N(ADC_CHANNEL_IN8), ADC_SQR2_SQ5_N(ADC_CHANNEL_IN7) | ADC_SQR2_SQ6_N(ADC_CHANNEL_IN8) | @@ -108,13 +116,13 @@ static const ADCConversionGroup adcgrpcfg2 = { 0, 0 }, - { /* SSMPR[2] */ + .ssmpr = { ADC_SMPR1_SMP_AN7(ADC_SMPR_SMP_19P5) | ADC_SMPR1_SMP_AN8(ADC_SMPR_SMP_19P5), ADC_SMPR2_SMP_AN16(ADC_SMPR_SMP_61P5) | ADC_SMPR2_SMP_AN17(ADC_SMPR_SMP_61P5), }, - { /* SSQR[4] */ + .ssqr = { ADC_SQR1_SQ1_N(ADC_CHANNEL_IN8) | ADC_SQR1_SQ2_N(ADC_CHANNEL_IN7) | ADC_SQR1_SQ3_N(ADC_CHANNEL_IN8) | ADC_SQR1_SQ4_N(ADC_CHANNEL_IN7), ADC_SQR2_SQ5_N(ADC_CHANNEL_IN8) | ADC_SQR2_SQ6_N(ADC_CHANNEL_IN7) | diff --git a/testhal/STM32/multi/ADC/cfg/stm32g071rb_nucleo64/portab.c b/testhal/STM32/multi/ADC/cfg/stm32g071rb_nucleo64/portab.c index d785d5a3c..76a34150c 100644 --- a/testhal/STM32/multi/ADC/cfg/stm32g071rb_nucleo64/portab.c +++ b/testhal/STM32/multi/ADC/cfg/stm32g071rb_nucleo64/portab.c @@ -65,13 +65,15 @@ const ADCConversionGroup portab_adcgrpcfg1 = { .num_channels = ADC_GRP1_NUM_CHANNELS, .end_cb = NULL, .error_cb = adcerrorcallback, - .cfgr1 = ADC_CFGR1_CONT | ADC_CFGR1_RES_12BIT, /* CFGR1 */ - .cfgr2 = 0, /* CFGR2 */ - .tr1 = ADC_TR(0, 0), /* TR1 */ - .tr2 = ADC_TR(0, 0), /* TR2 */ - .tr3 = ADC_TR(0, 0), /* TR3 */ - .smpr = ADC_SMPR_SMP_1P5, /* SMPR */ - .chselr = ADC_CHSELR_CHSEL10 /* CHSELR */ + .cfgr1 = ADC_CFGR1_CONT | ADC_CFGR1_RES_12BIT, + .cfgr2 = 0, + .tr1 = ADC_TR_DISABLED, + .tr2 = ADC_TR_DISABLED, + .tr3 = ADC_TR_DISABLED, + .awd2cr = 0U, + .awd3cr = 0U, + .smpr = ADC_SMPR_SMP_1P5, + .chselr = ADC_CHSELR_CHSEL10 }; /* @@ -87,14 +89,16 @@ const ADCConversionGroup portab_adcgrpcfg2 = { .cfgr1 = ADC_CFGR1_CONT | ADC_CFGR1_RES_12BIT | ADC_CFGR1_EXTEN_RISING | - ADC_CFGR1_EXTSEL_SRC(0), /* CFGR1 */ - .cfgr2 = 0, /* CFGR2 */ - .tr1 = ADC_TR(0, 0), /* TR1 */ - .tr2 = ADC_TR(0, 0), /* TR2 */ - .tr3 = ADC_TR(0, 0), /* TR3 */ - .smpr = ADC_SMPR_SMP_39P5, /* SMPR */ + ADC_CFGR1_EXTSEL_SRC(0), + .cfgr2 = 0, + .tr1 = ADC_TR_DISABLED, + .tr2 = ADC_TR_DISABLED, + .tr3 = ADC_TR_DISABLED, + .awd2cr = 0U, + .awd3cr = 0U, + .smpr = ADC_SMPR_SMP_39P5, .chselr = ADC_CHSELR_CHSEL10 | ADC_CHSELR_CHSEL11 | - ADC_CHSELR_CHSEL17 | ADC_CHSELR_CHSEL18 /* CHSELR */ + ADC_CHSELR_CHSEL17 | ADC_CHSELR_CHSEL18 }; /*===========================================================================*/