From c70fa139d36fa30752033a1d761ad8385c0e8ecc Mon Sep 17 00:00:00 2001
From: Rocco Marco Guglielmi <roccomarco.guglielmi@live.com>
Date: Sat, 25 Jun 2016 16:56:59 +0000
Subject: [PATCH] Fixed Bug #761.

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/branches/stable_16.1.x@9666 35acf78f-673a-0410-8e92-d51de3d6d3f4
---
 os/hal/ports/STM32/STM32L4xx/hal_lld.c | 17 ++++++++++++++---
 readme.txt                             |  1 +
 2 files changed, 15 insertions(+), 3 deletions(-)

diff --git a/os/hal/ports/STM32/STM32L4xx/hal_lld.c b/os/hal/ports/STM32/STM32L4xx/hal_lld.c
index 98987c4ac..8277a8600 100644
--- a/os/hal/ports/STM32/STM32L4xx/hal_lld.c
+++ b/os/hal/ports/STM32/STM32L4xx/hal_lld.c
@@ -88,8 +88,7 @@ static void hal_lld_backup_domain_init(void) {
  */
 void hal_lld_init(void) {
 
-  /* Reset of all peripherals. AHB3 is not reseted because it could have
-     been initialized in the board initialization file (board.c).*/
+  /* Reset of all peripherals.*/
   rccResetAHB1(~0);
   rccResetAHB2(~0);
   rccResetAHB3(~0);
@@ -109,8 +108,20 @@ void hal_lld_init(void) {
 
   /* Programmable voltage detector enable.*/
 #if STM32_PVD_ENABLE
-  PWR->CR1 |= PWR_CR1_PVDE | (STM32_PLS & STM32_PLS_MASK);
+  PWR->CR2 = PWR_CR2_PVDE | (STM32_PLS & STM32_PLS_MASK);
+#else
+  PWR->CR2 = 0;
 #endif /* STM32_PVD_ENABLE */
+
+  /* Enabling independent VDDUSB.*/
+#if HAL_USE_USB
+  PWR->CR2 |= PWR_CR2_USV;
+#endif /* HAL_USE_USB */
+
+  /* Enabling independent VDDIO2 required by GPIOG.*/
+#if STM32_HAS_GPIOG
+  PWR->CR2 |= PWR_CR2_IOSV;
+#endif /* STM32_HAS_GPIOG */
 }
 
 /**
diff --git a/readme.txt b/readme.txt
index ec576b02d..72a6aab82 100644
--- a/readme.txt
+++ b/readme.txt
@@ -73,6 +73,7 @@
 *****************************************************************************
 
 *** 16.1.5 ***
+- HAL: Fixed wrong PWR configurations in STM32L4xx\hal_lld (bug #761).
 - HAL: Fixed wrong comment in STM32L4xx\hal_lld (bug #760).
 - HAL: Fixed wrong MSIRANGE management for STM32L4xx in function 
        stm32_clock_init() (bug #759).