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ChibiOS
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git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@16370 27425a3e-05d8-49a3-a47f-9c15f0e5edd8

This commit is contained in:
Giovanni Di Sirio 2023-08-10 16:54:18 +00:00
parent c84a7c61b7
commit c7b3abea41
3 changed files with 430 additions and 355 deletions
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46
os/hal/ports/STM32/LLD/RCCv1/stm32_pll1.inc
View File

@ -26,6 +26,15 @@
/* Driver local definitions. */
/*===========================================================================*/
/**
* @name PLL helpers
*/
#define STM32_PLL1RGE_0 (0U << RCC_PLL1CFGR_PLL1RGE_Pos)
#define STM32_PLL1RGE_1 (1U << RCC_PLL1CFGR_PLL1RGE_Pos)
#define STM32_PLL1RGE_2 (2U << RCC_PLL1CFGR_PLL1RGE_Pos)
#define STM32_PLL1RGE_3 (3U << RCC_PLL1CFGR_PLL1RGE_Pos)
/** @} */
/*===========================================================================*/
/* Derived constants and error checks. */
/*===========================================================================*/
@ -173,6 +182,10 @@
#endif
/* Input checks.*/
#if !defined(STM32_PLL1IN)
#error "STM32_PLL1IN not defined in hal_lld.h"
#endif
#if !defined(STM32_ACTIVATE_PLL1)
#error "STM32_ACTIVATE_PLL1 not defined in hal_lld.h"
#endif
@ -189,15 +202,10 @@
#error "STM32_PLL1REN not defined in hal_lld.h"
#endif
#if STM32_ACTIVATE_PLL1 && (STM32_PLL1CLKIN == 0)
#if STM32_ACTIVATE_PLL1 && (STM32_PLL1IN == 0)
#error "PLL1 activation required but no PLL1 clock selected"
#endif
#if (STM32_PLL1CLKIN != 0) && \
((STM32_PLL1CLKIN < STM32_PLLIN_MIN) || (STM32_PLL1CLKIN > STM32_PLLIN_MAX))
#error "STM32_PLL1CLKIN outside acceptable range (STM32_PLLIN_MIN...STM32_PLLIN_MAX)"
#endif
/**
* @brief STM32_PLL1M field.
*/
@ -210,6 +218,28 @@
#error "invalid STM32_PLL1M_VALUE value specified"
#endif
/**
* @brief PLL comparator input frequency.
*/
#define STM32_PLL1CLKIN (STM32_PLL1IN / STM32_PLL1M_VALUE)
/**
* @brief PLL comparator input frequency.
*/
#if STM32_PLL1CLKIN < STM32_PLLIN_MIN
#error "STM32_PLL1CLKIN below acceptable range"
#elif STM32_PLL1CLKIN > STM32_PLLIN_MAX
#error "STM32_PLL1CLKIN above acceptable range"
#elif (STM32_PLL1CLKIN < STM32_PLLIN_THRESHOLD1) || defined(__DOXYGEN__)
#define STM32_PLL1RGE STM32_PLL1RGE_0
#elif STM32_PLL1CLKIN < STM32_PLLIN_THRESHOLD2
#define STM32_PLL1RGE STM32_PLL1RGE_1
#elif STM32_PLL1CLKIN < STM32_PLLIN_THRESHOLD3
#define STM32_PLL1RGE STM32_PLL1RGE_2
#else
#define STM32_PLL1RGE STM32_PLL1RGE_3
#endif
/**
* @brief STM32_PLL1N field.
*/
@ -225,7 +255,7 @@
/**
* @brief PLL1 VCO frequency.
*/
#define STM32_PLL1VCO (STM32_PLL1CLKIN * STM32_PLL1N_VALUE)
#define STM32_PLL1VCO (STM32_PLL1IN * STM32_PLL1N_VALUE)
/*
* PLL1 VCO frequency range check.
@ -382,7 +412,7 @@ __STATIC_INLINE void pll1_init(void) {
/* PLL1 activation.*/
RCC->PLL1CFGR = STM32_PLL1REN | STM32_PLL1QEN |
STM32_PLL1PEN | STM32_PLL1M |
STM32_PLL1SRC; /* TODO PLL1VCOSEL, PLL1FRACEN, PLL1RGE */
STM32_PLL1RGE | STM32_PLL1SRC; /* TODO PLL1VCOSEL, PLL1FRACEN */
RCC->PLL1DIVR = STM32_PLL1R | STM32_PLL1Q |
STM32_PLL1P | STM32_PLL1N;
RCC->CR |= RCC_CR_PLL1ON;

361
os/hal/ports/STM32/STM32H5xx/hal_lld.h
View File

@ -1328,341 +1328,8 @@
#endif
/**
* @name System Limits for VOS range 0
* @{
*/
#define STM32_VOS0_SYSCLK_MAX 250000000
#define STM32_VOS0_HSECLK_MAX 50000000
#define STM32_VOS0_HSECLK_BYP_MAX 50000000
#define STM32_VOS0_HSECLK_MIN 4000000
#define STM32_VOS0_HSECLK_BYP_MIN 4000000
#define STM32_VOS0_LSECLK_MAX 32768
#define STM32_VOS0_LSECLK_BYP_MAX 1000000
#define STM32_VOS0_LSECLK_MIN 32768
#define STM32_VOS0_LSECLK_BYP_MIN 32768
#define STM32_VOS0_PLLIN_MAX 16000000
#define STM32_VOS0_PLLIN_MIN 2000000
#define STM32_VOS0_PLLVCO_MAX 560000000
#define STM32_VOS0_PLLVCO_MIN 128000000
#define STM32_VOS0_PLLP_MAX 250000000
#define STM32_VOS0_PLLP_MIN 1000000
#define STM32_VOS0_PLLQ_MAX 250000000
#define STM32_VOS0_PLLQ_MIN 1000000
#define STM32_VOS0_PLLR_MAX 250000000
#define STM32_VOS0_PLLR_MIN 1000000
#define STM32_VOS0_PCLK1_MAX 250000000
#define STM32_VOS0_PCLK2_MAX 250000000
#define STM32_VOS0_PCLK2_MAX 250000000
#define STM32_VOS0_ADCCLK_MAX 125000000
#define STM32_VOS0_0WS_THRESHOLD 42000000
#define STM32_VOS0_1WS_THRESHOLD 84000000
#define STM32_VOS0_2WS_THRESHOLD 126000000
#define STM32_VOS0_3WS_THRESHOLD 168000000
#define STM32_VOS0_4WS_THRESHOLD 210000000
/** @} */
/**
* @name System Limits for VOS range 1
* @{
*/
#define STM32_VOS1_SYSCLK_MAX 200000000
#define STM32_VOS1_HSECLK_MAX 50000000
#define STM32_VOS1_HSECLK_BYP_MAX 50000000
#define STM32_VOS1_HSECLK_MIN 4000000
#define STM32_VOS1_HSECLK_BYP_MIN 4000000
#define STM32_VOS1_LSECLK_MAX 32768
#define STM32_VOS1_LSECLK_BYP_MAX 1000000
#define STM32_VOS1_LSECLK_MIN 32768
#define STM32_VOS1_LSECLK_BYP_MIN 32768
#define STM32_VOS1_PLLIN_MAX 16000000
#define STM32_VOS1_PLLIN_MIN 2000000
#define STM32_VOS1_PLLVCO_MAX 560000000
#define STM32_VOS1_PLLVCO_MIN 128000000
#define STM32_VOS1_PLLP_MAX 200000000
#define STM32_VOS1_PLLP_MIN 1000000
#define STM32_VOS1_PLLQ_MAX 200000000
#define STM32_VOS1_PLLQ_MIN 1000000
#define STM32_VOS1_PLLR_MAX 200000000
#define STM32_VOS1_PLLR_MIN 1000000
#define STM32_VOS1_PCLK1_MAX 200000000
#define STM32_VOS1_PCLK2_MAX 200000000
#define STM32_VOS1_PCLK2_MAX 200000000
#define STM32_VOS1_ADCCLK_MAX 100000000
#define STM32_VOS1_0WS_THRESHOLD 34000000
#define STM32_VOS1_1WS_THRESHOLD 68000000
#define STM32_VOS1_2WS_THRESHOLD 102000000
#define STM32_VOS1_3WS_THRESHOLD 136000000
#define STM32_VOS1_4WS_THRESHOLD 170000000
/** @} */
/**
* @name System Limits for VOS range 2
* @{
*/
#define STM32_VOS2_SYSCLK_MAX 150000000
#define STM32_VOS2_HSECLK_MAX 50000000
#define STM32_VOS2_HSECLK_BYP_MAX 50000000
#define STM32_VOS2_HSECLK_MIN 4000000
#define STM32_VOS2_HSECLK_BYP_MIN 4000000
#define STM32_VOS2_LSECLK_MAX 32768
#define STM32_VOS2_LSECLK_BYP_MAX 1000000
#define STM32_VOS2_LSECLK_MIN 32768
#define STM32_VOS2_LSECLK_BYP_MIN 32768
#define STM32_VOS2_PLLIN_MAX 16000000
#define STM32_VOS2_PLLIN_MIN 2000000
#define STM32_VOS2_PLLVCO_MAX 560000000
#define STM32_VOS2_PLLVCO_MIN 128000000
#define STM32_VOS2_PLLP_MAX 150000000
#define STM32_VOS2_PLLP_MIN 1000000
#define STM32_VOS2_PLLQ_MAX 150000000
#define STM32_VOS2_PLLQ_MIN 1000000
#define STM32_VOS2_PLLR_MAX 150000000
#define STM32_VOS2_PLLR_MIN 1000000
#define STM32_VOS2_PCLK1_MAX 150000000
#define STM32_VOS2_PCLK2_MAX 150000000
#define STM32_VOS2_PCLK3_MAX 150000000
#define STM32_VOS2_ADCCLK_MAX 75000000
#define STM32_VOS2_0WS_THRESHOLD 30000000
#define STM32_VOS2_1WS_THRESHOLD 60000000
#define STM32_VOS2_2WS_THRESHOLD 90000000
#define STM32_VOS2_3WS_THRESHOLD 120000000
#define STM32_VOS2_4WS_THRESHOLD 0
/** @} */
/**
* @name System Limits for VOS range 3
* @{
*/
#define STM32_VOS3_SYSCLK_MAX 100000000
#define STM32_VOS3_HSECLK_MAX 50000000
#define STM32_VOS3_HSECLK_BYP_MAX 50000000
#define STM32_VOS3_HSECLK_MIN 4000000
#define STM32_VOS3_HSECLK_BYP_MIN 4000000
#define STM32_VOS3_LSECLK_MAX 32768
#define STM32_VOS3_LSECLK_BYP_MAX 1000000
#define STM32_VOS3_LSECLK_MIN 32768
#define STM32_VOS3_LSECLK_BYP_MIN 32768
#define STM32_VOS3_PLLIN_MAX 16000000
#define STM32_VOS3_PLLIN_MIN 2000000
#define STM32_VOS3_PLLVCO_MAX 560000000
#define STM32_VOS3_PLLVCO_MIN 128000000
#define STM32_VOS3_PLLP_MAX 100000000
#define STM32_VOS3_PLLP_MIN 1000000
#define STM32_VOS3_PLLQ_MAX 100000000
#define STM32_VOS3_PLLQ_MIN 1000000
#define STM32_VOS3_PLLR_MAX 100000000
#define STM32_VOS3_PLLR_MIN 1000000
#define STM32_VOS3_PCLK1_MAX 100000000
#define STM32_VOS3_PCLK2_MAX 100000000
#define STM32_VOS3_PCLK3_MAX 100000000
#define STM32_VOS3_ADCCLK_MAX 50000000
#define STM32_VOS3_0WS_THRESHOLD 20000000
#define STM32_VOS3_1WS_THRESHOLD 40000000
#define STM32_VOS3_2WS_THRESHOLD 60000000
#define STM32_VOS3_3WS_THRESHOLD 80000000
#define STM32_VOS3_4WS_THRESHOLD 0
/** @} */
/* Voltage related limits.*/
#if ((STM32_PWR_VOSCR & STM32_VOS_MASK) == STM32_VOS_RANGE0) || defined(__DOXYGEN__)
#define STM32_SYSCLK_MAX STM32_VOS0_SYSCLK_MAX
#define STM32_HSECLK_MAX STM32_VOS0_HSECLK_MAX
#define STM32_HSECLK_BYP_MAX STM32_VOS0_HSECLK_BYP_MAX
#define STM32_HSECLK_MIN STM32_VOS0_HSECLK_MIN
#define STM32_HSECLK_BYP_MIN STM32_VOS0_HSECLK_BYP_MIN
#define STM32_LSECLK_MAX STM32_VOS0_LSECLK_MAX
#define STM32_LSECLK_BYP_MAX STM32_VOS0_LSECLK_BYP_MAX
#define STM32_LSECLK_MIN STM32_VOS0_LSECLK_MIN
#define STM32_LSECLK_BYP_MIN STM32_VOS0_LSECLK_BYP_MIN
#define STM32_PLLIN_MAX STM32_VOS0_PLLIN_MAX
#define STM32_PLLIN_MIN STM32_VOS0_PLLIN_MIN
#define STM32_PLLVCO_MAX STM32_VOS0_PLLVCO_MAX
#define STM32_PLLVCO_MIN STM32_VOS0_PLLVCO_MIN
#define STM32_PLLP_MAX STM32_VOS0_PLLP_MAX
#define STM32_PLLP_MIN STM32_VOS0_PLLP_MIN
#define STM32_PLLP_MIN STM32_VOS0_PLLP_MIN
#define STM32_PLLQ_MAX STM32_VOS0_PLLQ_MAX
#define STM32_PLLQ_MIN STM32_VOS0_PLLQ_MIN
#define STM32_PLLR_MAX STM32_VOS0_PLLR_MAX
#define STM32_PLLR_MIN STM32_VOS0_PLLR_MIN
#define STM32_PCLK1_MAX STM32_VOS0_PCLK1_MAX
#define STM32_PCLK2_MAX STM32_VOS0_PCLK2_MAX
#define STM32_PCLK3_MAX STM32_VOS0_PCLK3_MAX
#define STM32_ADCCLK_MAX STM32_VOS0_ADCCLK_MAX
#define STM32_0WS_THRESHOLD STM32_VOS0_0WS_THRESHOLD
#define STM32_1WS_THRESHOLD STM32_VOS0_1WS_THRESHOLD
#define STM32_2WS_THRESHOLD STM32_VOS0_2WS_THRESHOLD
#define STM32_3WS_THRESHOLD STM32_VOS0_3WS_THRESHOLD
#define STM32_4WS_THRESHOLD STM32_VOS0_4WS_THRESHOLD
#define STM32_5WS_THRESHOLD STM32_VOS0_5WS_THRESHOLD
#define STM32_6WS_THRESHOLD STM32_VOS0_6WS_THRESHOLD
#define STM32_7WS_THRESHOLD STM32_VOS0_7WS_THRESHOLD
#define STM32_8WS_THRESHOLD STM32_VOS0_8WS_THRESHOLD
#elif (STM32_PWR_VOSCR & STM32_VOS_MASK) == STM32_VOS_RANGE1
#define STM32_SYSCLK_MAX STM32_VOS1_SYSCLK_MAX
#define STM32_HSECLK_MAX STM32_VOS1_HSECLK_MAX
#define STM32_HSECLK_BYP_MAX STM32_VOS1_HSECLK_BYP_MAX
#define STM32_HSECLK_MIN STM32_VOS1_HSECLK_MIN
#define STM32_HSECLK_BYP_MIN STM32_VOS1_HSECLK_BYP_MIN
#define STM32_LSECLK_MAX STM32_VOS1_LSECLK_MAX
#define STM32_LSECLK_BYP_MAX STM32_VOS1_LSECLK_BYP_MAX
#define STM32_LSECLK_MIN STM32_VOS1_LSECLK_MIN
#define STM32_LSECLK_BYP_MIN STM32_VOS1_LSECLK_BYP_MIN
#define STM32_PLLIN_MAX STM32_VOS1_PLLIN_MAX
#define STM32_PLLIN_MIN STM32_VOS1_PLLIN_MIN
#define STM32_PLLVCO_MAX STM32_VOS1_PLLVCO_MAX
#define STM32_PLLVCO_MIN STM32_VOS1_PLLVCO_MIN
#define STM32_PLLP_MAX STM32_VOS1_PLLP_MAX
#define STM32_PLLP_MIN STM32_VOS1_PLLP_MIN
#define STM32_PLLQ_MAX STM32_VOS1_PLLQ_MAX
#define STM32_PLLQ_MIN STM32_VOS1_PLLQ_MIN
#define STM32_PLLR_MAX STM32_VOS1_PLLR_MAX
#define STM32_PLLR_MIN STM32_VOS1_PLLR_MIN
#define STM32_PCLK1_MAX STM32_VOS1_PCLK1_MAX
#define STM32_PCLK2_MAX STM32_VOS1_PCLK2_MAX
#define STM32_PCLK3_MAX STM32_VOS1_PCLK3_MAX
#define STM32_ADCCLK_MAX STM32_VOS1_ADCCLK_MAX
#define STM32_0WS_THRESHOLD STM32_VOS1_0WS_THRESHOLD
#define STM32_1WS_THRESHOLD STM32_VOS1_1WS_THRESHOLD
#define STM32_2WS_THRESHOLD STM32_VOS1_2WS_THRESHOLD
#define STM32_3WS_THRESHOLD STM32_VOS1_3WS_THRESHOLD
#define STM32_4WS_THRESHOLD STM32_VOS1_4WS_THRESHOLD
#define STM32_5WS_THRESHOLD STM32_VOS1_5WS_THRESHOLD
#define STM32_6WS_THRESHOLD STM32_VOS1_6WS_THRESHOLD
#define STM32_7WS_THRESHOLD STM32_VOS1_7WS_THRESHOLD
#define STM32_8WS_THRESHOLD STM32_VOS1_8WS_THRESHOLD
#elif (STM32_PWR_VOSCR & STM32_VOS_MASK) == STM32_VOS_RANGE2
#define STM32_SYSCLK_MAX STM32_VOS2_SYSCLK_MAX
#define STM32_HSECLK_MAX STM32_VOS2_HSECLK_MAX
#define STM32_HSECLK_BYP_MAX STM32_VOS2_HSECLK_BYP_MAX
#define STM32_HSECLK_MIN STM32_VOS2_HSECLK_MIN
#define STM32_HSECLK_BYP_MIN STM32_VOS2_HSECLK_BYP_MIN
#define STM32_LSECLK_MAX STM32_VOS2_LSECLK_MAX
#define STM32_LSECLK_BYP_MAX STM32_VOS2_LSECLK_BYP_MAX
#define STM32_LSECLK_MIN STM32_VOS2_LSECLK_MIN
#define STM32_LSECLK_BYP_MIN STM32_VOS2_LSECLK_BYP_MIN
#define STM32_PLLIN_MAX STM32_VOS2_PLLIN_MAX
#define STM32_PLLIN_MIN STM32_VOS2_PLLIN_MIN
#define STM32_PLLVCO_MAX STM32_VOS2_PLLVCO_MAX
#define STM32_PLLVCO_MIN STM32_VOS2_PLLVCO_MIN
#define STM32_PLLP_MAX STM32_VOS2_PLLP_MAX
#define STM32_PLLP_MIN STM32_VOS2_PLLP_MIN
#define STM32_PLLQ_MAX STM32_VOS2_PLLQ_MAX
#define STM32_PLLQ_MIN STM32_VOS2_PLLQ_MIN
#define STM32_PLLR_MAX STM32_VOS2_PLLR_MAX
#define STM32_PLLR_MIN STM32_VOS2_PLLR_MIN
#define STM32_PCLK1_MAX STM32_VOS2_PCLK1_MAX
#define STM32_PCLK2_MAX STM32_VOS2_PCLK2_MAX
#define STM32_PCLK3_MAX STM32_VOS2_PCLK3_MAX
#define STM32_ADCCLK_MAX STM32_VOS2_ADCCLK_MAX
#define STM32_0WS_THRESHOLD STM32_VOS2_0WS_THRESHOLD
#define STM32_1WS_THRESHOLD STM32_VOS2_1WS_THRESHOLD
#define STM32_2WS_THRESHOLD STM32_VOS2_2WS_THRESHOLD
#define STM32_3WS_THRESHOLD STM32_VOS2_3WS_THRESHOLD
#define STM32_4WS_THRESHOLD STM32_VOS2_4WS_THRESHOLD
#define STM32_5WS_THRESHOLD STM32_VOS2_5WS_THRESHOLD
#define STM32_6WS_THRESHOLD STM32_VOS2_6WS_THRESHOLD
#define STM32_7WS_THRESHOLD STM32_VOS2_7WS_THRESHOLD
#define STM32_8WS_THRESHOLD STM32_VOS2_8WS_THRESHOLD
#elif (STM32_PWR_VOSCR & STM32_VOS_MASK) == STM32_VOS_RANGE3
#define STM32_SYSCLK_MAX STM32_VOS3_SYSCLK_MAX
#define STM32_HSECLK_MAX STM32_VOS3_HSECLK_MAX
#define STM32_HSECLK_BYP_MAX STM32_VOS3_HSECLK_BYP_MAX
#define STM32_HSECLK_MIN STM32_VOS3_HSECLK_MIN
#define STM32_HSECLK_BYP_MIN STM32_VOS3_HSECLK_BYP_MIN
#define STM32_LSECLK_MAX STM32_VOS3_LSECLK_MAX
#define STM32_LSECLK_BYP_MAX STM32_VOS3_LSECLK_BYP_MAX
#define STM32_LSECLK_MIN STM32_VOS3_LSECLK_MIN
#define STM32_LSECLK_BYP_MIN STM32_VOS3_LSECLK_BYP_MIN
#define STM32_PLLIN_MAX STM32_VOS3_PLLIN_MAX
#define STM32_PLLIN_MIN STM32_VOS3_PLLIN_MIN
#define STM32_PLLVCO_MAX STM32_VOS3_PLLVCO_MAX
#define STM32_PLLVCO_MIN STM32_VOS3_PLLVCO_MIN
#define STM32_PLLP_MAX STM32_VOS3_PLLP_MAX
#define STM32_PLLP_MIN STM32_VOS3_PLLP_MIN
#define STM32_PLLQ_MAX STM32_VOS3_PLLQ_MAX
#define STM32_PLLQ_MIN STM32_VOS3_PLLQ_MIN
#define STM32_PLLR_MAX STM32_VOS3_PLLR_MAX
#define STM32_PLLR_MIN STM32_VOS3_PLLR_MIN
#define STM32_PCLK1_MAX STM32_VOS3_PCLK1_MAX
#define STM32_PCLK2_MAX STM32_VOS3_PCLK2_MAX
#define STM32_PCLK3_MAX STM32_VOS3_PCLK3_MAX
#define STM32_ADCCLK_MAX STM32_VOS3_ADCCLK_MAX
#define STM32_0WS_THRESHOLD STM32_VOS3_0WS_THRESHOLD
#define STM32_1WS_THRESHOLD STM32_VOS3_1WS_THRESHOLD
#define STM32_2WS_THRESHOLD STM32_VOS3_2WS_THRESHOLD
#define STM32_3WS_THRESHOLD STM32_VOS3_3WS_THRESHOLD
#define STM32_4WS_THRESHOLD STM32_VOS3_4WS_THRESHOLD
#define STM32_5WS_THRESHOLD STM32_VOS3_5WS_THRESHOLD
#define STM32_6WS_THRESHOLD STM32_VOS3_6WS_THRESHOLD
#define STM32_7WS_THRESHOLD STM32_VOS3_7WS_THRESHOLD
#define STM32_8WS_THRESHOLD STM32_VOS3_8WS_THRESHOLD
#else
#error "invalid STM32_VOS value specified"
#endif
/**
* @name PLLs dividers ranges
* @{
*/
#define STM32_PLL1M_VALUE_MAX 63
#define STM32_PLL1M_VALUE_MIN 1
#define STM32_PLL1N_ODDVALID TRUE
#define STM32_PLL1N_VALUE_MAX 512
#define STM32_PLL1N_VALUE_MIN 4
#define STM32_PLL1P_ODDVALID FALSE
#define STM32_PLL1P_VALUE_MAX 128
#define STM32_PLL1P_VALUE_MIN 2
#define STM32_PLL1Q_ODDVALID TRUE
#define STM32_PLL1Q_VALUE_MAX 128
#define STM32_PLL1Q_VALUE_MIN 1
#define STM32_PLL1R_ODDVALID TRUE
#define STM32_PLL1R_VALUE_MAX 128
#define STM32_PLL1R_VALUE_MIN 1
#define STM32_PLL2M_VALUE_MAX 63
#define STM32_PLL2M_VALUE_MIN 1
#define STM32_PLL2N_ODDVALID TRUE
#define STM32_PLL2N_VALUE_MAX 512
#define STM32_PLL2N_VALUE_MIN 4
#define STM32_PLL2P_ODDVALID TRUE
#define STM32_PLL2P_VALUE_MAX 128
#define STM32_PLL2P_VALUE_MIN 2
#define STM32_PLL2Q_ODDVALID TRUE
#define STM32_PLL2Q_VALUE_MAX 128
#define STM32_PLL2Q_VALUE_MIN 1
#define STM32_PLL2R_ODDVALID TRUE
#define STM32_PLL2R_VALUE_MAX 128
#define STM32_PLL2R_VALUE_MIN 1
#define STM32_PLL3M_VALUE_MAX 63
#define STM32_PLL3M_VALUE_MIN 1
#define STM32_PLL3N_ODDVALID TRUE
#define STM32_PLL3N_VALUE_MAX 512
#define STM32_PLL3N_VALUE_MIN 4
#define STM32_PLL3P_ODDVALID TRUE
#define STM32_PLL3P_VALUE_MAX 128
#define STM32_PLL3P_VALUE_MIN 2
#define STM32_PLL3Q_ODDVALID TRUE
#define STM32_PLL3Q_VALUE_MAX 128
#define STM32_PLL3Q_VALUE_MIN 1
#define STM32_PLL3R_ODDVALID TRUE
#define STM32_PLL3R_VALUE_MAX 128
#define STM32_PLL3R_VALUE_MIN 1
/** @} */
/* Device limits.*/
#include "stm32_limits.h"
/* Clock handlers.*/
#include "stm32_lsi.inc"
@ -2332,16 +1999,16 @@
* @brief PLL1 input clock frequency.
*/
#if (STM32_PLL1SRC == STM32_PLL1SRC_HSE) || defined(__DOXYGEN__)
#define STM32_PLL1CLKIN (STM32_HSECLK / STM32_PLL1M_VALUE)
#define STM32_PLL1IN STM32_HSECLK
#elif STM32_PLL1SRC == STM32_PLL1SRC_CSI
#define STM32_PLL1CLKIN (STM32_CSICLK / STM32_PLL1M_VALUE)
#define STM32_PLL1IN STM32_CSICLK
#elif STM32_PLL1SRC == STM32_PLL1SRC_HSI
#define STM32_PLL1CLKIN (STM32_HSICLK / STM32_PLL1M_VALUE)
#define STM32_PLL1IN STM32_HSICLK
#elif STM32_PLL1SRC == STM32_PLL1SRC_NOCLOCK
#define STM32_PLL1CLKIN 0
#define STM32_PLL1IN 0
#else
#error "invalid STM32_PLL1SRC value specified"
@ -2351,16 +2018,16 @@
* @brief PLL2 input clock frequency.
*/
#if (STM32_PLL2SRC == STM32_PLL2SRC_HSE) || defined(__DOXYGEN__)
#define STM32_PLL2CLKIN (STM32_HSECLK / STM32_PLL2M_VALUE)
#define STM32_PLL2IN STM32_HSECLK
#elif STM32_PLL2SRC == STM32_PLL2SRC_CSI
#define STM32_PLL2CLKIN (STM32_CSICLK / STM32_PLL2M_VALUE)
#define STM32_PLL2IN STM32_CSICLK
#elif STM32_PLL2SRC == STM32_PLL2SRC_HSI
#define STM32_PLL2CLKIN (STM32_HSICLK / STM32_PLL2M_VALUE)
#define STM32_PLL2IN STM32_HSICLK
#elif STM32_PLL2SRC == STM32_PLL2SRC_NOCLOCK
#define STM32_PLL2CLKIN 0
#define STM32_PLL2IN 0
#else
#error "invalid STM32_PLL2SRC value specified"
@ -2370,16 +2037,16 @@
* @brief PLL3 input clock frequency.
*/
#if (STM32_PLL3SRC == STM32_PLL3SRC_HSE) || defined(__DOXYGEN__)
#define STM32_PLL3CLKIN (STM32_HSECLK / STM32_PLL3M_VALUE)
#define STM32_PLL3IN STM32_HSECLK
#elif STM32_PLL3SRC == STM32_PLL3SRC_CSI
#define STM32_PLL3CLKIN (STM32_CSICLK / STM32_PLL3M_VALUE)
#define STM32_PLL3IN STM32_CSICLK
#elif STM32_PLL3SRC == STM32_PLL3SRC_HSI
#define STM32_PLL3CLKIN (STM32_HSICLK / STM32_PLL3M_VALUE)
#define STM32_PLL3IN STM32_HSICLK
#elif STM32_PLL3SRC == STM32_PLL3SRC_NOCLOCK
#define STM32_PLL3CLKIN 0
#define STM32_PLL3IN 0
#else
#error "invalid STM32_PLL3SRC value specified"

378
os/hal/ports/STM32/STM32H5xx/stm32_limits.h Normal file
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@ -0,0 +1,378 @@
/*
ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
/**
* @file STM32H5xx/stm32_limits.h
* @brief STM32H5xx device limits header.
*
* @addtogroup HAL
* @{
*/
#ifndef STM32_LIMITS_H
#define STM32_LIMITS_H
/**
* @name Device Limits for VOS range 0
* @{
*/
#define STM32_VOS0_SYSCLK_MAX 250000000
#define STM32_VOS0_HSECLK_MAX 50000000
#define STM32_VOS0_HSECLK_BYP_MAX 50000000
#define STM32_VOS0_HSECLK_MIN 4000000
#define STM32_VOS0_HSECLK_BYP_MIN 4000000
#define STM32_VOS0_LSECLK_MAX 32768
#define STM32_VOS0_LSECLK_BYP_MAX 1000000
#define STM32_VOS0_LSECLK_MIN 32768
#define STM32_VOS0_LSECLK_BYP_MIN 32768
#define STM32_VOS0_PLLIN_MAX 16000000
#define STM32_VOS0_PLLIN_MIN 2000000
#define STM32_VOS0_PLLVCO_MAX 560000000
#define STM32_VOS0_PLLVCO_MIN 128000000
#define STM32_VOS0_PLLP_MAX 250000000
#define STM32_VOS0_PLLP_MIN 1000000
#define STM32_VOS0_PLLQ_MAX 250000000
#define STM32_VOS0_PLLQ_MIN 1000000
#define STM32_VOS0_PLLR_MAX 250000000
#define STM32_VOS0_PLLR_MIN 1000000
#define STM32_VOS0_PCLK1_MAX 250000000
#define STM32_VOS0_PCLK2_MAX 250000000
#define STM32_VOS0_PCLK2_MAX 250000000
#define STM32_VOS0_ADCCLK_MAX 125000000
#define STM32_VOS0_0WS_THRESHOLD 42000000
#define STM32_VOS0_1WS_THRESHOLD 84000000
#define STM32_VOS0_2WS_THRESHOLD 126000000
#define STM32_VOS0_3WS_THRESHOLD 168000000
#define STM32_VOS0_4WS_THRESHOLD 210000000
/** @} */
/**
* @name Device Limits for VOS range 1
* @{
*/
#define STM32_VOS1_SYSCLK_MAX 200000000
#define STM32_VOS1_HSECLK_MAX 50000000
#define STM32_VOS1_HSECLK_BYP_MAX 50000000
#define STM32_VOS1_HSECLK_MIN 4000000
#define STM32_VOS1_HSECLK_BYP_MIN 4000000
#define STM32_VOS1_LSECLK_MAX 32768
#define STM32_VOS1_LSECLK_BYP_MAX 1000000
#define STM32_VOS1_LSECLK_MIN 32768
#define STM32_VOS1_LSECLK_BYP_MIN 32768
#define STM32_VOS1_PLLIN_MAX 16000000
#define STM32_VOS1_PLLIN_MIN 2000000
#define STM32_VOS1_PLLVCO_MAX 560000000
#define STM32_VOS1_PLLVCO_MIN 128000000
#define STM32_VOS1_PLLP_MAX 200000000
#define STM32_VOS1_PLLP_MIN 1000000
#define STM32_VOS1_PLLQ_MAX 200000000
#define STM32_VOS1_PLLQ_MIN 1000000
#define STM32_VOS1_PLLR_MAX 200000000
#define STM32_VOS1_PLLR_MIN 1000000
#define STM32_VOS1_PCLK1_MAX 200000000
#define STM32_VOS1_PCLK2_MAX 200000000
#define STM32_VOS1_PCLK2_MAX 200000000
#define STM32_VOS1_ADCCLK_MAX 100000000
#define STM32_VOS1_0WS_THRESHOLD 34000000
#define STM32_VOS1_1WS_THRESHOLD 68000000
#define STM32_VOS1_2WS_THRESHOLD 102000000
#define STM32_VOS1_3WS_THRESHOLD 136000000
#define STM32_VOS1_4WS_THRESHOLD 170000000
/** @} */
/**
* @name Device Limits for VOS range 2
* @{
*/
#define STM32_VOS2_SYSCLK_MAX 150000000
#define STM32_VOS2_HSECLK_MAX 50000000
#define STM32_VOS2_HSECLK_BYP_MAX 50000000
#define STM32_VOS2_HSECLK_MIN 4000000
#define STM32_VOS2_HSECLK_BYP_MIN 4000000
#define STM32_VOS2_LSECLK_MAX 32768
#define STM32_VOS2_LSECLK_BYP_MAX 1000000
#define STM32_VOS2_LSECLK_MIN 32768
#define STM32_VOS2_LSECLK_BYP_MIN 32768
#define STM32_VOS2_PLLIN_MAX 16000000
#define STM32_VOS2_PLLIN_MIN 2000000
#define STM32_VOS2_PLLVCO_MAX 560000000
#define STM32_VOS2_PLLVCO_MIN 128000000
#define STM32_VOS2_PLLP_MAX 150000000
#define STM32_VOS2_PLLP_MIN 1000000
#define STM32_VOS2_PLLQ_MAX 150000000
#define STM32_VOS2_PLLQ_MIN 1000000
#define STM32_VOS2_PLLR_MAX 150000000
#define STM32_VOS2_PLLR_MIN 1000000
#define STM32_VOS2_PCLK1_MAX 150000000
#define STM32_VOS2_PCLK2_MAX 150000000
#define STM32_VOS2_PCLK3_MAX 150000000
#define STM32_VOS2_ADCCLK_MAX 75000000
#define STM32_VOS2_0WS_THRESHOLD 30000000
#define STM32_VOS2_1WS_THRESHOLD 60000000
#define STM32_VOS2_2WS_THRESHOLD 90000000
#define STM32_VOS2_3WS_THRESHOLD 120000000
#define STM32_VOS2_4WS_THRESHOLD 0
/** @} */
/**
* @name Device Limits for VOS range 3
* @{
*/
#define STM32_VOS3_SYSCLK_MAX 100000000
#define STM32_VOS3_HSECLK_MAX 50000000
#define STM32_VOS3_HSECLK_BYP_MAX 50000000
#define STM32_VOS3_HSECLK_MIN 4000000
#define STM32_VOS3_HSECLK_BYP_MIN 4000000
#define STM32_VOS3_LSECLK_MAX 32768
#define STM32_VOS3_LSECLK_BYP_MAX 1000000
#define STM32_VOS3_LSECLK_MIN 32768
#define STM32_VOS3_LSECLK_BYP_MIN 32768
#define STM32_VOS3_PLLIN_MAX 16000000
#define STM32_VOS3_PLLIN_MIN 2000000
#define STM32_VOS3_PLLVCO_MAX 560000000
#define STM32_VOS3_PLLVCO_MIN 128000000
#define STM32_VOS3_PLLP_MAX 100000000
#define STM32_VOS3_PLLP_MIN 1000000
#define STM32_VOS3_PLLQ_MAX 100000000
#define STM32_VOS3_PLLQ_MIN 1000000
#define STM32_VOS3_PLLR_MAX 100000000
#define STM32_VOS3_PLLR_MIN 1000000
#define STM32_VOS3_PCLK1_MAX 100000000
#define STM32_VOS3_PCLK2_MAX 100000000
#define STM32_VOS3_PCLK3_MAX 100000000
#define STM32_VOS3_ADCCLK_MAX 50000000
#define STM32_VOS3_0WS_THRESHOLD 20000000
#define STM32_VOS3_1WS_THRESHOLD 40000000
#define STM32_VOS3_2WS_THRESHOLD 60000000
#define STM32_VOS3_3WS_THRESHOLD 80000000
#define STM32_VOS3_4WS_THRESHOLD 0
/** @} */
/**
* @name Device Limits for current VOS settings
* @{
*/
#if ((STM32_PWR_VOSCR & STM32_VOS_MASK) == STM32_VOS_RANGE0) || defined(__DOXYGEN__)
#define STM32_SYSCLK_MAX STM32_VOS0_SYSCLK_MAX
#define STM32_HSECLK_MAX STM32_VOS0_HSECLK_MAX
#define STM32_HSECLK_BYP_MAX STM32_VOS0_HSECLK_BYP_MAX
#define STM32_HSECLK_MIN STM32_VOS0_HSECLK_MIN
#define STM32_HSECLK_BYP_MIN STM32_VOS0_HSECLK_BYP_MIN
#define STM32_LSECLK_MAX STM32_VOS0_LSECLK_MAX
#define STM32_LSECLK_BYP_MAX STM32_VOS0_LSECLK_BYP_MAX
#define STM32_LSECLK_MIN STM32_VOS0_LSECLK_MIN
#define STM32_LSECLK_BYP_MIN STM32_VOS0_LSECLK_BYP_MIN
#define STM32_PLLIN_MAX STM32_VOS0_PLLIN_MAX
#define STM32_PLLIN_MIN STM32_VOS0_PLLIN_MIN
#define STM32_PLLVCO_MAX STM32_VOS0_PLLVCO_MAX
#define STM32_PLLVCO_MIN STM32_VOS0_PLLVCO_MIN
#define STM32_PLLP_MAX STM32_VOS0_PLLP_MAX
#define STM32_PLLP_MIN STM32_VOS0_PLLP_MIN
#define STM32_PLLP_MIN STM32_VOS0_PLLP_MIN
#define STM32_PLLQ_MAX STM32_VOS0_PLLQ_MAX
#define STM32_PLLQ_MIN STM32_VOS0_PLLQ_MIN
#define STM32_PLLR_MAX STM32_VOS0_PLLR_MAX
#define STM32_PLLR_MIN STM32_VOS0_PLLR_MIN
#define STM32_PCLK1_MAX STM32_VOS0_PCLK1_MAX
#define STM32_PCLK2_MAX STM32_VOS0_PCLK2_MAX
#define STM32_PCLK3_MAX STM32_VOS0_PCLK3_MAX
#define STM32_ADCCLK_MAX STM32_VOS0_ADCCLK_MAX
#define STM32_0WS_THRESHOLD STM32_VOS0_0WS_THRESHOLD
#define STM32_1WS_THRESHOLD STM32_VOS0_1WS_THRESHOLD
#define STM32_2WS_THRESHOLD STM32_VOS0_2WS_THRESHOLD
#define STM32_3WS_THRESHOLD STM32_VOS0_3WS_THRESHOLD
#define STM32_4WS_THRESHOLD STM32_VOS0_4WS_THRESHOLD
#define STM32_5WS_THRESHOLD STM32_VOS0_5WS_THRESHOLD
#define STM32_6WS_THRESHOLD STM32_VOS0_6WS_THRESHOLD
#define STM32_7WS_THRESHOLD STM32_VOS0_7WS_THRESHOLD
#define STM32_8WS_THRESHOLD STM32_VOS0_8WS_THRESHOLD
/** @} */
#elif (STM32_PWR_VOSCR & STM32_VOS_MASK) == STM32_VOS_RANGE1
#define STM32_SYSCLK_MAX STM32_VOS1_SYSCLK_MAX
#define STM32_HSECLK_MAX STM32_VOS1_HSECLK_MAX
#define STM32_HSECLK_BYP_MAX STM32_VOS1_HSECLK_BYP_MAX
#define STM32_HSECLK_MIN STM32_VOS1_HSECLK_MIN
#define STM32_HSECLK_BYP_MIN STM32_VOS1_HSECLK_BYP_MIN
#define STM32_LSECLK_MAX STM32_VOS1_LSECLK_MAX
#define STM32_LSECLK_BYP_MAX STM32_VOS1_LSECLK_BYP_MAX
#define STM32_LSECLK_MIN STM32_VOS1_LSECLK_MIN
#define STM32_LSECLK_BYP_MIN STM32_VOS1_LSECLK_BYP_MIN
#define STM32_PLLIN_MAX STM32_VOS1_PLLIN_MAX
#define STM32_PLLIN_MIN STM32_VOS1_PLLIN_MIN
#define STM32_PLLVCO_MAX STM32_VOS1_PLLVCO_MAX
#define STM32_PLLVCO_MIN STM32_VOS1_PLLVCO_MIN
#define STM32_PLLP_MAX STM32_VOS1_PLLP_MAX
#define STM32_PLLP_MIN STM32_VOS1_PLLP_MIN
#define STM32_PLLQ_MAX STM32_VOS1_PLLQ_MAX
#define STM32_PLLQ_MIN STM32_VOS1_PLLQ_MIN
#define STM32_PLLR_MAX STM32_VOS1_PLLR_MAX
#define STM32_PLLR_MIN STM32_VOS1_PLLR_MIN
#define STM32_PCLK1_MAX STM32_VOS1_PCLK1_MAX
#define STM32_PCLK2_MAX STM32_VOS1_PCLK2_MAX
#define STM32_PCLK3_MAX STM32_VOS1_PCLK3_MAX
#define STM32_ADCCLK_MAX STM32_VOS1_ADCCLK_MAX
#define STM32_0WS_THRESHOLD STM32_VOS1_0WS_THRESHOLD
#define STM32_1WS_THRESHOLD STM32_VOS1_1WS_THRESHOLD
#define STM32_2WS_THRESHOLD STM32_VOS1_2WS_THRESHOLD
#define STM32_3WS_THRESHOLD STM32_VOS1_3WS_THRESHOLD
#define STM32_4WS_THRESHOLD STM32_VOS1_4WS_THRESHOLD
#define STM32_5WS_THRESHOLD STM32_VOS1_5WS_THRESHOLD
#define STM32_6WS_THRESHOLD STM32_VOS1_6WS_THRESHOLD
#define STM32_7WS_THRESHOLD STM32_VOS1_7WS_THRESHOLD
#define STM32_8WS_THRESHOLD STM32_VOS1_8WS_THRESHOLD
#elif (STM32_PWR_VOSCR & STM32_VOS_MASK) == STM32_VOS_RANGE2
#define STM32_SYSCLK_MAX STM32_VOS2_SYSCLK_MAX
#define STM32_HSECLK_MAX STM32_VOS2_HSECLK_MAX
#define STM32_HSECLK_BYP_MAX STM32_VOS2_HSECLK_BYP_MAX
#define STM32_HSECLK_MIN STM32_VOS2_HSECLK_MIN
#define STM32_HSECLK_BYP_MIN STM32_VOS2_HSECLK_BYP_MIN
#define STM32_LSECLK_MAX STM32_VOS2_LSECLK_MAX
#define STM32_LSECLK_BYP_MAX STM32_VOS2_LSECLK_BYP_MAX
#define STM32_LSECLK_MIN STM32_VOS2_LSECLK_MIN
#define STM32_LSECLK_BYP_MIN STM32_VOS2_LSECLK_BYP_MIN
#define STM32_PLLIN_MAX STM32_VOS2_PLLIN_MAX
#define STM32_PLLIN_MIN STM32_VOS2_PLLIN_MIN
#define STM32_PLLVCO_MAX STM32_VOS2_PLLVCO_MAX
#define STM32_PLLVCO_MIN STM32_VOS2_PLLVCO_MIN
#define STM32_PLLP_MAX STM32_VOS2_PLLP_MAX
#define STM32_PLLP_MIN STM32_VOS2_PLLP_MIN
#define STM32_PLLQ_MAX STM32_VOS2_PLLQ_MAX
#define STM32_PLLQ_MIN STM32_VOS2_PLLQ_MIN
#define STM32_PLLR_MAX STM32_VOS2_PLLR_MAX
#define STM32_PLLR_MIN STM32_VOS2_PLLR_MIN
#define STM32_PCLK1_MAX STM32_VOS2_PCLK1_MAX
#define STM32_PCLK2_MAX STM32_VOS2_PCLK2_MAX
#define STM32_PCLK3_MAX STM32_VOS2_PCLK3_MAX
#define STM32_ADCCLK_MAX STM32_VOS2_ADCCLK_MAX
#define STM32_0WS_THRESHOLD STM32_VOS2_0WS_THRESHOLD
#define STM32_1WS_THRESHOLD STM32_VOS2_1WS_THRESHOLD
#define STM32_2WS_THRESHOLD STM32_VOS2_2WS_THRESHOLD
#define STM32_3WS_THRESHOLD STM32_VOS2_3WS_THRESHOLD
#define STM32_4WS_THRESHOLD STM32_VOS2_4WS_THRESHOLD
#define STM32_5WS_THRESHOLD STM32_VOS2_5WS_THRESHOLD
#define STM32_6WS_THRESHOLD STM32_VOS2_6WS_THRESHOLD
#define STM32_7WS_THRESHOLD STM32_VOS2_7WS_THRESHOLD
#define STM32_8WS_THRESHOLD STM32_VOS2_8WS_THRESHOLD
#elif (STM32_PWR_VOSCR & STM32_VOS_MASK) == STM32_VOS_RANGE3
#define STM32_SYSCLK_MAX STM32_VOS3_SYSCLK_MAX
#define STM32_HSECLK_MAX STM32_VOS3_HSECLK_MAX
#define STM32_HSECLK_BYP_MAX STM32_VOS3_HSECLK_BYP_MAX
#define STM32_HSECLK_MIN STM32_VOS3_HSECLK_MIN
#define STM32_HSECLK_BYP_MIN STM32_VOS3_HSECLK_BYP_MIN
#define STM32_LSECLK_MAX STM32_VOS3_LSECLK_MAX
#define STM32_LSECLK_BYP_MAX STM32_VOS3_LSECLK_BYP_MAX
#define STM32_LSECLK_MIN STM32_VOS3_LSECLK_MIN
#define STM32_LSECLK_BYP_MIN STM32_VOS3_LSECLK_BYP_MIN
#define STM32_PLLIN_MAX STM32_VOS3_PLLIN_MAX
#define STM32_PLLIN_MIN STM32_VOS3_PLLIN_MIN
#define STM32_PLLVCO_MAX STM32_VOS3_PLLVCO_MAX
#define STM32_PLLVCO_MIN STM32_VOS3_PLLVCO_MIN
#define STM32_PLLP_MAX STM32_VOS3_PLLP_MAX
#define STM32_PLLP_MIN STM32_VOS3_PLLP_MIN
#define STM32_PLLQ_MAX STM32_VOS3_PLLQ_MAX
#define STM32_PLLQ_MIN STM32_VOS3_PLLQ_MIN
#define STM32_PLLR_MAX STM32_VOS3_PLLR_MAX
#define STM32_PLLR_MIN STM32_VOS3_PLLR_MIN
#define STM32_PCLK1_MAX STM32_VOS3_PCLK1_MAX
#define STM32_PCLK2_MAX STM32_VOS3_PCLK2_MAX
#define STM32_PCLK3_MAX STM32_VOS3_PCLK3_MAX
#define STM32_ADCCLK_MAX STM32_VOS3_ADCCLK_MAX
#define STM32_0WS_THRESHOLD STM32_VOS3_0WS_THRESHOLD
#define STM32_1WS_THRESHOLD STM32_VOS3_1WS_THRESHOLD
#define STM32_2WS_THRESHOLD STM32_VOS3_2WS_THRESHOLD
#define STM32_3WS_THRESHOLD STM32_VOS3_3WS_THRESHOLD
#define STM32_4WS_THRESHOLD STM32_VOS3_4WS_THRESHOLD
#define STM32_5WS_THRESHOLD STM32_VOS3_5WS_THRESHOLD
#define STM32_6WS_THRESHOLD STM32_VOS3_6WS_THRESHOLD
#define STM32_7WS_THRESHOLD STM32_VOS3_7WS_THRESHOLD
#define STM32_8WS_THRESHOLD STM32_VOS3_8WS_THRESHOLD
#else
#error "invalid STM32_VOS value specified"
#endif
/**
* @name PLL input thresholds
*/
#define STM32_PLLIN_THRESHOLD1 2000000
#define STM32_PLLIN_THRESHOLD2 4000000
#define STM32_PLLIN_THRESHOLD3 8000000
/** @} */
/**
* @name PLL dividers ranges
* @{
*/
#define STM32_PLL1M_VALUE_MAX 63
#define STM32_PLL1M_VALUE_MIN 1
#define STM32_PLL1N_ODDVALID TRUE
#define STM32_PLL1N_VALUE_MAX 512
#define STM32_PLL1N_VALUE_MIN 4
#define STM32_PLL1P_ODDVALID FALSE
#define STM32_PLL1P_VALUE_MAX 128
#define STM32_PLL1P_VALUE_MIN 2
#define STM32_PLL1Q_ODDVALID TRUE
#define STM32_PLL1Q_VALUE_MAX 128
#define STM32_PLL1Q_VALUE_MIN 1
#define STM32_PLL1R_ODDVALID TRUE
#define STM32_PLL1R_VALUE_MAX 128
#define STM32_PLL1R_VALUE_MIN 1
#define STM32_PLL2M_VALUE_MAX 63
#define STM32_PLL2M_VALUE_MIN 1
#define STM32_PLL2N_ODDVALID TRUE
#define STM32_PLL2N_VALUE_MAX 512
#define STM32_PLL2N_VALUE_MIN 4
#define STM32_PLL2P_ODDVALID TRUE
#define STM32_PLL2P_VALUE_MAX 128
#define STM32_PLL2P_VALUE_MIN 2
#define STM32_PLL2Q_ODDVALID TRUE
#define STM32_PLL2Q_VALUE_MAX 128
#define STM32_PLL2Q_VALUE_MIN 1
#define STM32_PLL2R_ODDVALID TRUE
#define STM32_PLL2R_VALUE_MAX 128
#define STM32_PLL2R_VALUE_MIN 1
#define STM32_PLL3M_VALUE_MAX 63
#define STM32_PLL3M_VALUE_MIN 1
#define STM32_PLL3N_ODDVALID TRUE
#define STM32_PLL3N_VALUE_MAX 512
#define STM32_PLL3N_VALUE_MIN 4
#define STM32_PLL3P_ODDVALID TRUE
#define STM32_PLL3P_VALUE_MAX 128
#define STM32_PLL3P_VALUE_MIN 2
#define STM32_PLL3Q_ODDVALID TRUE
#define STM32_PLL3Q_VALUE_MAX 128
#define STM32_PLL3Q_VALUE_MIN 1
#define STM32_PLL3R_ODDVALID TRUE
#define STM32_PLL3R_VALUE_MAX 128
#define STM32_PLL3R_VALUE_MIN 1
/** @} */
#endif /* STM32_LIMITS_H */
/** @} */