andreika-git
/
ChibiOS
mirror of https://github.com/andreika-git/ChibiOS.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

Added clock sources for timers and more CFGR settings. 

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@11186 35acf78f-673a-0410-8e92-d51de3d6d3f4
This commit is contained in:
Giovanni Di Sirio 2017-12-26 09:10:43 +00:00
parent eb4d803488
commit c7f42d1d71
3 changed files with 82 additions and 30 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
demos/STM32/RT-STM32H743I-NUCLEO144/mcuconf.h
View File

@ -64,7 +64,6 @@
#define STM32_HSE_ENABLED TRUE
#define STM32_LSE_ENABLED TRUE
#define STM32_HSIDIV STM32_HSIDIV_DIV1
#define STM32_RTCPRE_VALUE 8
/*
* PLLs static settings.
@ -124,6 +123,11 @@
#define STM32_MCO1PRE_VALUE 4
#define STM32_MCO2SEL STM32_MCO2SEL_SYS_CK
#define STM32_MCO2PRE_VALUE 4
#define STM32_TIMPRE_ENABLE TRUE
#define STM32_HRTIMSEL 0
#define STM32_STOPKERWUCK 0
#define STM32_STOPWUCK 0
#define STM32_RTCPRE_VALUE 8
#define STM32_CKPERSEL STM32_CKPERSEL_HSE_CK
#define STM32_SDMMCSEL STM32_SDMMCSEL_PLL1_Q_CK
#define STM32_QSPISEL STM32_QSPISEL_HCLK

11
os/hal/ports/STM32/STM32H7xx/hal_lld.c
View File

@ -157,6 +157,8 @@ void hal_lld_init(void) {
* @special
*/
void stm32_clock_init(void) {
uint32_t cfgr;
#if 0
RCC_TypeDef *rcc = RCC; /* For inspection.*/
(void)rcc;
@ -197,9 +199,14 @@ void stm32_clock_init(void) {
/* Other clock-related settings, done before other things because
recommended in the RM.*/
RCC->CFGR = STM32_MCO2SEL | RCC_CFGR_MCO2PRE_VALUE(STM32_MCO2PRE_VALUE) |
cfgr = STM32_MCO2SEL | RCC_CFGR_MCO2PRE_VALUE(STM32_MCO2PRE_VALUE) |
STM32_MCO1SEL | RCC_CFGR_MCO1PRE_VALUE(STM32_MCO1PRE_VALUE) |
RCC_CFGR_RTCPRE_VALUE(STM32_RTCPRE_VALUE);
RCC_CFGR_RTCPRE_VALUE(STM32_RTCPRE_VALUE) |
STM32_HRTIMSEL | STM32_STOPKERWUCK | STM32_STOPWUCK;
#if STM32_TIMPRE_ENABLE == TRUE
cfgr |= RCC_CFGR_TIMPRE;
#endif
RCC->CFGR = cfgr;
/* HSE activation with optional bypass.*/
#if STM32_HSE_ENABLED == TRUE

93
os/hal/ports/STM32/STM32H7xx/hal_lld.h
View File

@ -360,6 +360,12 @@
#define STM32_RTCSEL_LSI_CK RCC_BDCR_RTCSEL_VALUE(2U)
#define STM32_RTCSEL_HSE_1M_CK RCC_BDCR_RTCSEL_VALUE(3U)
#define STM32_HRTIMSEL_C_CLK RCC_CFGR_HRTIMSEL
#define STM32_STOPKERWUCK_ENABLED RCC_CFGR_STOPKERWUCK
#define STM32_STOPWUCK_ENABLED RCC_CFGR_STOPKERWUCK
#define STM32_PLLSRC_HSI_CK RCC_PLLCKSELR_PLLSRC_VALUE(0U)
#define STM32_PLLSRC_CSI_CK RCC_PLLCKSELR_PLLSRC_VALUE(1U)
#define STM32_PLLSRC_HSE_CK RCC_PLLCKSELR_PLLSRC_VALUE(2U)
@ -622,14 +628,6 @@
#define STM32_HSIDIV STM32_HSIDIV_DIV1
#endif
/**
* @brief RTC HSE prescaler value.
* @note The allowed values are 2..63.
*/
#if !defined(STM32_RTCPRE_VALUE) || defined(__DOXYGEN__)
#define STM32_RTCPRE_VALUE 8
#endif
/**
* @brief Clock source for all PLLs.
*/
@ -910,6 +908,42 @@
#define STM32_MCO2PRE_VALUE 4
#endif
/**
* @brief TIM clock prescaler selection.
*/
#if !defined(STM32_TIMPRE_ENABLE) || defined(__DOXYGEN__)
#define STM32_TIMPRE_ENABLE FALSE
#endif
/**
* @brief HRTIM clock prescaler selection.
*/
#if !defined(STM32_HRTIMSEL) || defined(__DOXYGEN__)
#define STM32_HRTIMSEL 0
#endif
/**
* @brief Kernel clock selection after a wake up from system Stop.
*/
#if !defined(STM32_STOPKERWUCK) || defined(__DOXYGEN__)
#define STM32_STOPKERWUCK 0
#endif
/**
* @brief System clock selection after a wake up from system Stop.
*/
#if !defined(STM32_STOPWUCK) || defined(__DOXYGEN__)
#define STM32_STOPWUCK 0
#endif
/**
* @brief RTC HSE prescaler value.
* @note The allowed values are 2..63.
*/
#if !defined(STM32_RTCPRE_VALUE) || defined(__DOXYGEN__)
#define STM32_RTCPRE_VALUE 8
#endif
/**
* @brief Main clock source selection.
* @note This setting can be modified at runtime.
@ -2220,6 +2254,31 @@
#define STM32_FLASHBITS 0x00000007
#endif
/**
* @brief Clock of timers connected to APB1
*/
#if (STM32_D2PPRE1 == STM32_D2PPRE1_DIV1) || defined(__DOXYGEN__)
#define STM32_TIMCLK1 (STM32_PCLK1 * 1)
#else
#if (STM32_TIMPRE_ENABLE == FALSE) || (STM32_D2PPRE1 == STM32_D2PPRE1_DIV2)
#define STM32_TIMCLK1 (STM32_PCLK1 * 2)
#else
#define STM32_TIMCLK1 (STM32_PCLK1 * 4)
#endif
#endif
/**
* @brief Clock of timers connected to APB2.
*/
#if (STM32_D2PPRE2 == STM32_D2PPRE2_DIV1) || defined(__DOXYGEN__)
#define STM32_TIMCLK2 (STM32_PCLK2 * 1)
#else
#if (STM32_TIMPRE_ENABLE == FALSE) || (STM32_D2PPRE2 == STM32_D2PPRE2_DIV2)
#define STM32_TIMCLK2 (STM32_PCLK2 * 2)
#else
#define STM32_TIMCLK2 (STM32_PCLK2 * 4)
#endif
#endif
@ -2499,24 +2558,6 @@
#else
#error "invalid source selected for SDMMC clock"
#endif
/**
* @brief Clock of timers connected to APB1
*/
#if (STM32_PPRE1 == STM32_PPRE1_DIV1) || defined(__DOXYGEN__)
#define STM32_TIMCLK1 (STM32_PCLK1 * 1)
#else
#define STM32_TIMCLK1 (STM32_PCLK1 * 2)
#endif
/**
* @brief Clock of timers connected to APB2.
*/
#if (STM32_PPRE2 == STM32_PPRE2_DIV1) || defined(__DOXYGEN__)
#define STM32_TIMCLK2 (STM32_PCLK2 * 1)
#else
#define STM32_TIMCLK2 (STM32_PCLK2 * 2)
#endif
#endif
/*===========================================================================*/