From c84a7c61b74887266a97f899e416ec49b2d2c7dd Mon Sep 17 00:00:00 2001 From: Giovanni Di Sirio Date: Thu, 10 Aug 2023 14:46:18 +0000 Subject: [PATCH] git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@16369 27425a3e-05d8-49a3-a47f-9c15f0e5edd8 --- .../RT-STM32H563ZI-NUCLEO144/cfg/mcuconf.h | 10 +- os/hal/ports/STM32/LLD/RCCv1/stm32_apb1.inc | 12 +- os/hal/ports/STM32/LLD/RCCv1/stm32_apb2.inc | 12 +- os/hal/ports/STM32/LLD/RCCv1/stm32_apb3.inc | 12 +- os/hal/ports/STM32/LLD/RCCv1/stm32_csi.inc | 6 +- os/hal/ports/STM32/LLD/RCCv1/stm32_hsidiv.inc | 6 +- os/hal/ports/STM32/LLD/RCCv1/stm32_lsi.inc | 9 + os/hal/ports/STM32/LLD/RCCv1/stm32_lsi_v3.inc | 37 +-- os/hal/ports/STM32/LLD/RCCv1/stm32_pll1.inc | 254 ++++++++++-------- os/hal/ports/STM32/LLD/RCCv1/stm32_pll2.inc | 4 - os/hal/ports/STM32/LLD/RCCv1/stm32_pll3.inc | 4 - os/hal/ports/STM32/STM32H5xx/hal_lld.h | 97 ++++--- os/hal/ports/STM32/STM32H5xx/platform.mk | 1 + os/hal/ports/STM32/STM32H5xx/stm32_registry.h | 1 + 14 files changed, 259 insertions(+), 206 deletions(-) diff --git a/demos/STM32/RT-STM32H563ZI-NUCLEO144/cfg/mcuconf.h b/demos/STM32/RT-STM32H563ZI-NUCLEO144/cfg/mcuconf.h index 29bcbbb7c..93197afcd 100644 --- a/demos/STM32/RT-STM32H563ZI-NUCLEO144/cfg/mcuconf.h +++ b/demos/STM32/RT-STM32H563ZI-NUCLEO144/cfg/mcuconf.h @@ -32,9 +32,9 @@ #define MCUCONF_H #define STM32H5xx_MCUCONF -#define STM32H562xx -#define STM32H563xx -#define STM32H573xx +#define STM32H562_MCUCONF +#define STM32H563_MCUCONF +#define STM32H573_MCUCONF /* * HAL driver system settings. @@ -114,10 +114,6 @@ #define STM32_USART11SEL STM32_USART11SEL_PCLK1 #define STM32_UART12SEL STM32_UART12SEL_PCLK1 #define STM32_LPUART1SEL STM32_LPUART1SEL_SYSCLK -#define STM32_I2C1SEL STM32_I2C1SEL_PCLK1 -#define STM32_I2C2SEL STM32_I2C2SEL_PCLK1 -#define STM32_I2C3SEL STM32_I2C3SEL_PCLK1 -#define STM32_I2C4SEL STM32_I2C4SEL_PCLK1 #define STM32_TIMICSEL STM32_TIMICSEL_NOCLK #define STM32_LPTIM1SEL STM32_LPTIM1SEL_PCLK3 #define STM32_LPTIM2SEL STM32_LPTIM2SEL_PCLK3 diff --git a/os/hal/ports/STM32/LLD/RCCv1/stm32_apb1.inc b/os/hal/ports/STM32/LLD/RCCv1/stm32_apb1.inc index a23c2845f..df294b0ca 100644 --- a/os/hal/ports/STM32/LLD/RCCv1/stm32_apb1.inc +++ b/os/hal/ports/STM32/LLD/RCCv1/stm32_apb1.inc @@ -26,12 +26,20 @@ /* Driver local definitions. */ /*===========================================================================*/ +#if defined(RCC_CFGR_PPRE1_Pos) +#define STM32_PPRE1_POS RCC_CFGR_PPRE1_Pos +#elif defined(RCC_CFGR2_PPRE1_Pos) +#define STM32_PPRE1_POS RCC_CFGR2_PPRE1_Pos +#else +#error "unknown register name" +#endif + /** * @name PPRE1 field bits definitions * @{ */ -#define STM32_PPRE1_MASK (7U << RCC_CFGR_PPRE1_Pos) -#define STM32_PPRE1_FIELD(n) ((n) << RCC_CFGR_PPRE1_Pos) +#define STM32_PPRE1_MASK (7U << STM32_PPRE1_POS) +#define STM32_PPRE1_FIELD(n) ((n) << STM32_PPRE1_POS) #define STM32_PPRE1_DIV1 STM32_PPRE1_FIELD(0U) #define STM32_PPRE1_DIV2 STM32_PPRE1_FIELD(4U) #define STM32_PPRE1_DIV4 STM32_PPRE1_FIELD(5U) diff --git a/os/hal/ports/STM32/LLD/RCCv1/stm32_apb2.inc b/os/hal/ports/STM32/LLD/RCCv1/stm32_apb2.inc index 8e646d536..497fe178a 100644 --- a/os/hal/ports/STM32/LLD/RCCv1/stm32_apb2.inc +++ b/os/hal/ports/STM32/LLD/RCCv1/stm32_apb2.inc @@ -26,12 +26,20 @@ /* Driver local definitions. */ /*===========================================================================*/ +#if defined(RCC_CFGR_PPRE2_Pos) +#define STM32_PPRE2_POS RCC_CFGR_PPRE2_Pos +#elif defined(RCC_CFGR2_PPRE2_Pos) +#define STM32_PPRE2_POS RCC_CFGR2_PPRE2_Pos +#else +#error "unknown register name" +#endif + /** * @name PPRE2 field bits definitions * @{ */ -#define STM32_PPRE2_MASK (7U << RCC_CFGR_PPRE2_Pos) -#define STM32_PPRE2_FIELD(n) ((n) << RCC_CFGR_PPRE2_Pos) +#define STM32_PPRE2_MASK (7U << STM32_PPRE2_POS) +#define STM32_PPRE2_FIELD(n) ((n) << STM32_PPRE2_POS) #define STM32_PPRE2_DIV1 STM32_PPRE2_FIELD(0U) #define STM32_PPRE2_DIV2 STM32_PPRE2_FIELD(4U) #define STM32_PPRE2_DIV4 STM32_PPRE2_FIELD(5U) diff --git a/os/hal/ports/STM32/LLD/RCCv1/stm32_apb3.inc b/os/hal/ports/STM32/LLD/RCCv1/stm32_apb3.inc index 137cdb2ce..2d16f6b3d 100644 --- a/os/hal/ports/STM32/LLD/RCCv1/stm32_apb3.inc +++ b/os/hal/ports/STM32/LLD/RCCv1/stm32_apb3.inc @@ -26,12 +26,20 @@ /* Driver local definitions. */ /*===========================================================================*/ +#if defined(RCC_CFGR_PPRE3_Pos) +#define STM32_PPRE3_POS RCC_CFGR_PPRE3_Pos +#elif defined(RCC_CFGR2_PPRE2_Pos) +#define STM32_PPRE3_POS RCC_CFGR2_PPRE3_Pos +#else +#error "unknown register name" +#endif + /** * @name PPRE3 field bits definitions * @{ */ -#define STM32_PPRE3_MASK (7U << RCC_CFGR_PPRE3_Pos) -#define STM32_PPRE3_FIELD(n) ((n) << RCC_CFGR_PPRE3_Pos) +#define STM32_PPRE3_MASK (7U << STM32_PPRE3_POS) +#define STM32_PPRE3_FIELD(n) ((n) << STM32_PPRE3_POS) #define STM32_PPRE3_DIV1 STM32_PPRE3_FIELD(0U) #define STM32_PPRE3_DIV2 STM32_PPRE3_FIELD(4U) #define STM32_PPRE3_DIV4 STM32_PPRE3_FIELD(5U) diff --git a/os/hal/ports/STM32/LLD/RCCv1/stm32_csi.inc b/os/hal/ports/STM32/LLD/RCCv1/stm32_csi.inc index aea1debab..6cf1c56ae 100644 --- a/os/hal/ports/STM32/LLD/RCCv1/stm32_csi.inc +++ b/os/hal/ports/STM32/LLD/RCCv1/stm32_csi.inc @@ -59,15 +59,15 @@ __STATIC_FORCEINLINE void csi_enable(void) { - RCC->OCENSETR = RCC_OCENSETR_CSION; - while ((RCC->OCRDYR & RCC_OCRDYR_CSIRDY) == 0U) { + RCC->CR |= RCC_CR_CSION; + while ((RCC->CR & RCC_CR_CSIRDY) == 0U) { /* Waiting for CSI activation.*/ } } __STATIC_FORCEINLINE void csi_disable(void) { - RCC->OCENCLRR = RCC_OCENCLRR_CSION; + RCC->CR &= ~RCC_CR_CSION; } __STATIC_FORCEINLINE void csi_init(void) { diff --git a/os/hal/ports/STM32/LLD/RCCv1/stm32_hsidiv.inc b/os/hal/ports/STM32/LLD/RCCv1/stm32_hsidiv.inc index f87b71295..98d83e6cb 100644 --- a/os/hal/ports/STM32/LLD/RCCv1/stm32_hsidiv.inc +++ b/os/hal/ports/STM32/LLD/RCCv1/stm32_hsidiv.inc @@ -94,15 +94,15 @@ __STATIC_INLINE void hsi_reset(void) { hsi_enable(); /* Clocking from HSI, in case HSI was not the default source.*/ - RCC->CFGR = RCC_CFGR_SW_HSI; - while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_HSI) { + RCC->CFGR1 = STM32_SW_HSI; + while ((RCC->CFGR1 & STM32_SWS_MASK) != STM32_SWS_HSI) { /* Wait until HSI is selected.*/ } } __STATIC_INLINE void hsi16_init(void) { -#if STM32_HSI16_ENABLED +#if STM32_HSI_ENABLED /* HSI activation.*/ hsi_enable(); #endif diff --git a/os/hal/ports/STM32/LLD/RCCv1/stm32_lsi.inc b/os/hal/ports/STM32/LLD/RCCv1/stm32_lsi.inc index 0352f8f84..eea0909bb 100644 --- a/os/hal/ports/STM32/LLD/RCCv1/stm32_lsi.inc +++ b/os/hal/ports/STM32/LLD/RCCv1/stm32_lsi.inc @@ -95,10 +95,19 @@ __STATIC_INLINE void lsi_init(void) { #if STM32_LSI_ENABLED +#if defined(RCC_CSR_LSION) /* LSI activation.*/ RCC->CSR |= STM32_LSIPRE | RCC_CSR_LSION; while ((RCC->CSR & RCC_CSR_LSIRDY) == 0U) { } +#elif defined(RCC_BDCR_LSION) + /* LSI activation.*/ + RCC->BDCR |= STM32_LSIPRE | RCC_BDCR_LSION; + while ((RCC->CSR & RCC_BDCR_LSIRDY) == 0U) { + } +#else +#error "unknown register name" +#endif #endif } diff --git a/os/hal/ports/STM32/LLD/RCCv1/stm32_lsi_v3.inc b/os/hal/ports/STM32/LLD/RCCv1/stm32_lsi_v3.inc index 536f8a721..94d15da2b 100644 --- a/os/hal/ports/STM32/LLD/RCCv1/stm32_lsi_v3.inc +++ b/os/hal/ports/STM32/LLD/RCCv1/stm32_lsi_v3.inc @@ -29,16 +29,7 @@ /** * @brief LSI clock frequency. */ -#define STM32_LSIRCCLK 32000U - -/** - * @name RCC_CSR2 register bits definitions - * @{ - */ -#define STM32_LSIPRE_MASK (1U << RCC_CSR2_LSIPRE_Pos) -#define STM32_LSIPRE_NODIV (0U << RCC_CSR2_LSIPRE_Pos) -#define STM32_LSIPRE_DIV128 (1U << RCC_CSR2_LSIPRE_Pos) -/** @} */ +#define STM32_LSICLK 32000U /*===========================================================================*/ /* Derived constants and error checks. */ @@ -49,37 +40,11 @@ #error "STM32_RCC_HAS_LSI not defined in stm32_registry.h" #endif -#if !defined(STM32_RCC_HAS_LSI_PRESCALER) -#error "STM32_RCC_HAS_LSI_PRESCALER not defined in stm32_registry.h" -#endif - /* Checks on configurations.*/ #if !defined(STM32_LSI_ENABLED) #error "STM32_LSI_ENABLED not defined in mcuconf.h" #endif -#if STM32_RCC_HAS_LSI_PRESCALER || defined(__DOXYGEN__) - -#if !defined(STM32_LSIPRE) -#error "STM32_LSIPRE not defined in mcuconf.h" -#endif - -/** - * @brief LSI frequency. - */ -#if (STM32_LSIPRE == STM32_LSIPRE_NODIV) || defined(__DOXYGEN__) -#define STM32_LSICLK (STM32_LSIRCCLK) -#elif STM32_LSIPRE == STM32_LSIPRE_DIV128 -#define STM32_LSICLK (STM32_LSIRCCLK / 128U) -#else -#error "invalid STM32_LSIPRE value specified" -#endif - -#else /* !STM32_RCC_HAS_LSI_PRESCALER */ -#define STM32_LSIPRE 0U -#define STM32_LSICLK (STM32_LSIRCCLK) -#endif /* !STM32_RCC_HAS_LSI_PRESCALER */ - /*===========================================================================*/ /* Driver exported variables. */ /*===========================================================================*/ diff --git a/os/hal/ports/STM32/LLD/RCCv1/stm32_pll1.inc b/os/hal/ports/STM32/LLD/RCCv1/stm32_pll1.inc index 3a3923853..8dd099b7e 100644 --- a/os/hal/ports/STM32/LLD/RCCv1/stm32_pll1.inc +++ b/os/hal/ports/STM32/LLD/RCCv1/stm32_pll1.inc @@ -62,10 +62,6 @@ #error "STM32_PLL1N_VALUE not defined in mcuconf.h" #endif -#if !defined(STM32_PLL1PDIV_VALUE) -#error "STM32_PLL1PDIV_VALUE not defined in mcuconf.h" -#endif - #if STM32_RCC_PLL1_HAS_P && !defined(STM32_PLL1P_VALUE) #error "STM32_PLL1P_VALUE not defined in mcuconf.h" #endif @@ -78,45 +74,102 @@ #error "STM32_PLL1R_VALUE not defined in mcuconf.h" #endif +/* Check on valid values.*/ +#if !defined(STM32_PLL1M_VALUE_MAX) +#error "STM32_PLL1M_VALUE_MAX not defined in hal_lld.h" +#endif + +#if !defined(STM32_PLL1M_VALUE_MIN) +#error "STM32_PLL1M_VALUE_MIN not defined in hal_lld.h" +#endif + +#if !defined(STM32_PLL1N_ODDVALID) +#error "STM32_PLL1N_ODDVALID not defined in hal_lld.h" +#endif + +#if !defined(STM32_PLL1N_VALUE_MAX) +#error "STM32_PLL1N_VALUE_MAX not defined in hal_lld.h" +#endif + +#if !defined(STM32_PLL1N_VALUE_MIN) +#error "STM32_PLL1N_VALUE_MIN not defined in hal_lld.h" +#endif + +#if !defined(STM32_PLL1P_ODDVALID) +#error "STM32_PLL1P_ODDVALID not defined in hal_lld.h" +#endif + +#if !defined(STM32_PLL1P_VALUE_MAX) +#error "STM32_PLL1P_VALUE_MAX not defined in hal_lld.h" +#endif + +#if !defined(STM32_PLL1P_VALUE_MIN) +#error "STM32_PLL1P_VALUE_MIN not defined in hal_lld.h" +#endif + +#if !defined(STM32_PLL1Q_ODDVALID) +#error "STM32_PLL1Q_ODDVALID not defined in hal_lld.h" +#endif + +#if !defined(STM32_PLL1Q_VALUE_MAX) +#error "STM32_PLL1Q_VALUE_MAX not defined in hal_lld.h" +#endif + +#if !defined(STM32_PLL1Q_VALUE_MIN) +#error "STM32_PLL1Q_VALUE_MIN not defined in hal_lld.h" +#endif + +#if !defined(STM32_PLL1R_ODDVALID) +#error "STM32_PLL1R_ODDVALID not defined in hal_lld.h" +#endif + +#if !defined(STM32_PLL1R_VALUE_MAX) +#error "STM32_PLL1R_VALUE_MAX not defined in hal_lld.h" +#endif + +#if !defined(STM32_PLL1R_VALUE_MIN) +#error "STM32_PLL1R_VALUE_MIN not defined in hal_lld.h" +#endif + /* Check on limits.*/ -#if !defined(STM32_PLL1IN_MAX) -#error "STM32_PLL1IN_MAX not defined in hal_lld.h" +#if !defined(STM32_PLLIN_MAX) +#error "STM32_PLLIN_MAX not defined in hal_lld.h" #endif -#if !defined(STM32_PLL1IN_MIN) -#error "STM32_PLL1IN_MIN not defined in hal_lld.h" +#if !defined(STM32_PLLIN_MIN) +#error "STM32_PLLIN_MIN not defined in hal_lld.h" #endif -#if !defined(STM32_PLL1VCO_MAX) -#error "STM32_PLL1VCO_MAX not defined in hal_lld.h" +#if !defined(STM32_PLLVCO_MAX) +#error "STM32_PLLVCO_MAX not defined in hal_lld.h" #endif -#if !defined(STM32_PLL1VCO_MIN) -#error "STM32_PLL1VCO_MIN not defined in hal_lld.h" +#if !defined(STM32_PLLVCO_MIN) +#error "STM32_PLLVCO_MIN not defined in hal_lld.h" #endif -#if !defined(STM32_PLL1P_MAX) -#error "STM32_PLL1P_MAX not defined in hal_lld.h" +#if !defined(STM32_PLLP_MAX) +#error "STM32_PLLP_MAX not defined in hal_lld.h" #endif -#if !defined(STM32_PLL1P_MIN) -#error "STM32_PLL1P_MIN not defined in hal_lld.h" +#if !defined(STM32_PLLP_MIN) +#error "STM32_PLLP_MIN not defined in hal_lld.h" #endif -#if !defined(STM32_PLL1Q_MAX) -#error "STM32_PLL1Q_MAX not defined in hal_lld.h" +#if !defined(STM32_PLLQ_MAX) +#error "STM32_PLLQ_MAX not defined in hal_lld.h" #endif -#if !defined(STM32_PLL1Q_MIN) -#error "STM32_PLL1Q_MIN not defined in hal_lld.h" +#if !defined(STM32_PLLQ_MIN) +#error "STM32_PLLQ_MIN not defined in hal_lld.h" #endif -#if !defined(STM32_PLL1R_MAX) -#error "STM32_PLL1R_MAX not defined in hal_lld.h" +#if !defined(STM32_PLLR_MAX) +#error "STM32_PLLR_MAX not defined in hal_lld.h" #endif -#if !defined(STM32_PLL1R_MIN) -#error "STM32_PLL1R_MIN not defined in hal_lld.h" +#if !defined(STM32_PLLR_MIN) +#error "STM32_PLLR_MIN not defined in hal_lld.h" #endif /* Input checks.*/ @@ -141,14 +194,15 @@ #endif #if (STM32_PLL1CLKIN != 0) && \ - ((STM32_PLL1CLKIN < STM32_PLL1IN_MIN) || (STM32_PLL1CLKIN > STM32_PLL1IN_MAX)) -#error "STM32_PLL1CLKIN outside acceptable range (STM32_PLL1IN_MIN...STM32_PLL1IN_MAX)" + ((STM32_PLL1CLKIN < STM32_PLLIN_MIN) || (STM32_PLL1CLKIN > STM32_PLLIN_MAX)) +#error "STM32_PLL1CLKIN outside acceptable range (STM32_PLLIN_MIN...STM32_PLLIN_MAX)" #endif /** * @brief STM32_PLL1M field. */ -#if ((STM32_PLL1M_VALUE >= 1) && (STM32_PLL1M_VALUE <= 16)) || \ +#if ((STM32_PLL1M_VALUE >= STM32_PLL1M_VALUE_MIN) && \ + (STM32_PLL1M_VALUE <= STM32_PLL1M_VALUE_MAX)) || \ defined(__DOXYGEN__) #define STM32_PLL1M ((STM32_PLL1M_VALUE - 1U) << RCC_PLL1CFGR_PLL1M_Pos) @@ -159,9 +213,10 @@ /** * @brief STM32_PLL1N field. */ -#if ((STM32_PLL1N_VALUE >= 8) && (STM32_PLL1N_VALUE <= 127)) || \ +#if ((STM32_PLL1N_VALUE >= STM32_PLL1N_VALUE_MIN) && \ + (STM32_PLL1N_VALUE <= STM32_PLL1N_VALUE_MAX)) || \ defined(__DOXYGEN__) -#define STM32_PLL1N (STM32_PLL1N_VALUE << RCC_PLL1CFGR_PLL1N_Pos) +#define STM32_PLL1N (STM32_PLL1N_VALUE << RCC_PLL1DIVR_PLL1N_Pos) #else #error "invalid STM32_PLL1N_VALUE value specified" @@ -176,7 +231,7 @@ * PLL1 VCO frequency range check. */ #if STM32_ACTIVATE_PLL1 && \ - ((STM32_PLL1VCO < STM32_PLL1VCO_MIN) || (STM32_PLL1VCO > STM32_PLL1VCO_MAX)) + ((STM32_PLL1VCO < STM32_PLLVCO_MIN) || (STM32_PLL1VCO > STM32_PLLVCO_MAX)) #error "STM32_PLL1VCO outside acceptable range (STM32_PLL1VCO_MIN...STM32_PLL1VCO_MAX)" #endif @@ -184,137 +239,114 @@ /* P output, if present. */ /*---------------------------------------------------------------------------*/ #if STM32_RCC_PLL1_HAS_P || defined(__DOXYGEN__) + +#if !STM32_PLL1P_ODDVALID && ((STM32_PLL1P_VALUE & 1) != 0) +#error "odd STM32_PLL1P_VALUE value specified" +#endif + /** * @brief STM32_PLL1P field. */ -#if (STM32_PLL1P_VALUE == 7) || defined(__DOXYGEN__) -#define STM32_PLL1P (0U << RCC_PLL1CFGR_PLL1P_Pos) - -#elif STM32_PLL1P_VALUE == 17 -#define STM32_PLL1P (1U << RCC_PLL1CFGR_PLL1P_Pos) - -#else -#error "invalid STM32_PLL1P_VALUE value specified" -#endif - -/* PDIV is not present on all devices.*/ -#if defined(RCC_PLL1CFGR_PLL1PDIV_Pos) || defined(__DOXYGEN__) -/** - * @brief STM32_PLL1PDIV field. - */ -#if (STM32_PLL1PDIV_VALUE == 0) || \ - ((STM32_PLL1PDIV_VALUE >= 2) && (STM32_PLL1PDIV_VALUE <= 31)) || \ +#if ((STM32_PLL1P_VALUE >= STM32_PLL1P_VALUE_MIN) && \ + (STM32_PLL1P_VALUE <= STM32_PLL1P_VALUE_MAX)) || \ defined(__DOXYGEN__) -#define STM32_PLL1PDIV (STM32_PLL1PDIV_VALUE << RCC_PLL1CFGR_PLL1PDIV_Pos) +#define STM32_PLL1P ((STM32_PLL1P_VALUE - 1) << RCC_PLL1DIVR_PLL1P_Pos) #else -#error "invalid STM32_PLL1PDIV_VALUE value specified" +#error "out of range STM32_PLL1P_VALUE value specified" #endif /** - * @brief PLL1 P output clock frequency. + * @brief PLL1P output clock frequency. */ -#if (STM32_PLL1PDIV_VALUE == 0) || defined(__DOXYGEN__) #define STM32_PLL1_P_CLKOUT (STM32_PLL1VCO / STM32_PLL1P_VALUE) -#else -#define STM32_PLL1_P_CLKOUT (STM32_PLL1VCO / STM32_PLL1PDIV_VALUE) -#endif - -#else -#define STM32_PLL1_P_CLKOUT (STM32_PLL1VCO / STM32_PLL1P_VALUE) -#define STM32_PLL1PDIV 0U -#endif /* - * PLL1-P output frequency range check. + * PLL1P output frequency range check. */ #if STM32_ACTIVATE_PLL1 && \ - ((STM32_PLL1_P_CLKOUT < STM32_PLL1P_MIN) || (STM32_PLL1_P_CLKOUT > STM32_PLL1P_MAX)) -#error "STM32_PLL1_P_CLKOUT outside acceptable range (STM32_PLL1P_MIN...STM32_PLL1P_MAX)" + ((STM32_PLL1_P_CLKOUT < STM32_PLLP_MIN) || \ + (STM32_PLL1_P_CLKOUT > STM32_PLLP_MAX)) +#error "STM32_PLL1_P_CLKOUT outside acceptable range (STM32_PLLP_MIN...STM32_PLLP_MAX)" #endif #else /* !STM32_RCC_PLL1_HAS_P */ -#define STM32_PLL1P 0U -#define STM32_PLL1PDIV 0U +#define STM32_PLL1P 0 #endif /* !STM32_RCC_PLL1_HAS_P */ /*---------------------------------------------------------------------------*/ /* Q output, if present. */ /*---------------------------------------------------------------------------*/ #if STM32_RCC_PLL1_HAS_Q || defined(__DOXYGEN__) -/** - * @brief STM32_PLL1Q field. - */ -#if (STM32_PLL1Q_VALUE == 2) || defined(__DOXYGEN__) -#define STM32_PLL1Q (0U << RCC_PLL1CFGR_PLL1Q_Pos) -#elif STM32_PLL1Q_VALUE == 4 -#define STM32_PLL1Q (1U << RCC_PLL1CFGR_PLL1Q_Pos) - -#elif STM32_PLL1Q_VALUE == 6 -#define STM32_PLL1Q (2U << RCC_PLL1CFGR_PLL1Q_Pos) - -#elif STM32_PLL1Q_VALUE == 8 -#define STM32_PLL1Q (3U << RCC_PLL1CFGR_PLL1Q_Pos) - -#else -#error "invalid STM32_PLL1Q_VALUE value specified" +#if !STM32_PLL1Q_ODDVALID && ((STM32_PLL1Q_VALUE & 1) != 0) +#error "odd STM32_PLL1Q_VALUE value specified" #endif /** - * @brief PLL1 Q output clock frequency. + * @brief STM32_PLL1Q field. + */ +#if ((STM32_PLL1Q_VALUE >= STM32_PLL1Q_VALUE_MIN) && \ + (STM32_PLL1Q_VALUE <= STM32_PLL1Q_VALUE_MAX)) || \ + defined(__DOXYGEN__) +#define STM32_PLL1Q ((STM32_PLL1Q_VALUE - 1) << RCC_PLL1DIVR_PLL1Q_Pos) +#else +#error "out of range STM32_PLL1Q_VALUE value specified" +#endif + +/** + * @brief PLL1Q output clock frequency. */ #define STM32_PLL1_Q_CLKOUT (STM32_PLL1VCO / STM32_PLL1Q_VALUE) /* - * PLL1-Q output frequency range check. + * PLL1P output frequency range check. */ #if STM32_ACTIVATE_PLL1 && \ - ((STM32_PLL1_Q_CLKOUT < STM32_PLL1Q_MIN) || (STM32_PLL1_Q_CLKOUT > STM32_PLL1Q_MAX)) -#error "STM32_PLL1_Q_CLKOUT outside acceptable range (STM32_PLL1Q_MIN...STM32_PLL1Q_MAX)" + ((STM32_PLL1_Q_CLKOUT < STM32_PLLQ_MIN) || \ + (STM32_PLL1_Q_CLKOUT > STM32_PLLQ_MAX)) +#error "STM32_PLL1_Q_CLKOUT outside acceptable range (STM32_PLLQ_MIN...STM32_PLLQ_MAX)" #endif #else /* !STM32_RCC_PLL1_HAS_Q */ -#define STM32_PLL1Q 0U +#define STM32_PLL1Q 0 #endif /* !STM32_RCC_PLL1_HAS_Q */ /*---------------------------------------------------------------------------*/ /* R output, if present. */ /*---------------------------------------------------------------------------*/ #if STM32_RCC_PLL1_HAS_R || defined(__DOXYGEN__) -/** - * @brief STM32_PLL1R field. - */ -#if (STM32_PLL1R_VALUE == 2) || defined(__DOXYGEN__) -#define STM32_PLL1R (0U << RCC_PLL1CFGR_PLL1R_Pos) -#elif STM32_PLL1R_VALUE == 4 -#define STM32_PLL1R (1U << RCC_PLL1CFGR_PLL1R_Pos) - -#elif STM32_PLL1R_VALUE == 6 -#define STM32_PLL1R (2U << RCC_PLL1CFGR_PLL1R_Pos) - -#elif STM32_PLL1R_VALUE == 8 -#define STM32_PLL1R (3U << RCC_PLL1CFGR_PLL1R_Pos) - -#else -#error "invalid STM32_PLL1R_VALUE value specified" +#if !STM32_PLL1R_ODDVALID && ((STM32_PLL1R_VALUE & 1) != 0) +#error "odd STM32_PLL1R_VALUE value specified" #endif /** - * @brief PLL1 R output clock frequency. + * @brief STM32_PLL1R field. + */ +#if ((STM32_PLL1R_VALUE >= STM32_PLL1R_VALUE_MIN) && \ + (STM32_PLL1R_VALUE <= STM32_PLL1R_VALUE_MAX)) || \ + defined(__DOXYGEN__) +#define STM32_PLL1R ((STM32_PLL1R_VALUE - 1) << RCC_PLL1DIVR_PLL1R_Pos) +#else +#error "out of range STM32_PLL1R_VALUE value specified" +#endif + +/** + * @brief PLL1R output clock frequency. */ #define STM32_PLL1_R_CLKOUT (STM32_PLL1VCO / STM32_PLL1R_VALUE) /* - * PLL1-R output frequency range check. + * PLL1R output frequency range check. */ #if STM32_ACTIVATE_PLL1 && \ - ((STM32_PLL1_R_CLKOUT < STM32_PLL1R_MIN) || (STM32_PLL1_R_CLKOUT > STM32_PLL1R_MAX)) -#error "STM32_PLL1_R_CLKOUT outside acceptable range (STM32_PLL1R_MIN...STM32_PLL1R_MAX)" + ((STM32_PLL1_R_CLKOUT < STM32_PLLR_MIN) || \ + (STM32_PLL1_R_CLKOUT > STM32_PLLR_MAX)) +#error "STM32_PLL1_R_CLKOUT outside acceptable range (STM32_PLLR_MIN...STM32_PLLR_MAX)" #endif #else /* !STM32_RCC_PLL1_HAS_R */ -#define STM32_PLL1R 0U +#define STM32_PLL1R 0 #endif /* !STM32_RCC_PLL1_HAS_R */ /*===========================================================================*/ @@ -348,11 +380,11 @@ __STATIC_INLINE void pll1_init(void) { #if STM32_RCC_HAS_PLL1 #if STM32_ACTIVATE_PLL1 /* PLL1 activation.*/ - RCC->PLL1CFGR = STM32_PLL1PDIV | STM32_PLL1R | - STM32_PLL1REN | STM32_PLL1Q | - STM32_PLL1QEN | STM32_PLL1P | - STM32_PLL1PEN | STM32_PLL1N | - STM32_PLL1M | STM32_PLL1SRC; + RCC->PLL1CFGR = STM32_PLL1REN | STM32_PLL1QEN | + STM32_PLL1PEN | STM32_PLL1M | + STM32_PLL1SRC; /* TODO PLL1VCOSEL, PLL1FRACEN, PLL1RGE */ + RCC->PLL1DIVR = STM32_PLL1R | STM32_PLL1Q | + STM32_PLL1P | STM32_PLL1N; RCC->CR |= RCC_CR_PLL1ON; pll1_wait_lock(); diff --git a/os/hal/ports/STM32/LLD/RCCv1/stm32_pll2.inc b/os/hal/ports/STM32/LLD/RCCv1/stm32_pll2.inc index 999897f54..e7a7494c4 100644 --- a/os/hal/ports/STM32/LLD/RCCv1/stm32_pll2.inc +++ b/os/hal/ports/STM32/LLD/RCCv1/stm32_pll2.inc @@ -62,10 +62,6 @@ #error "STM32_PLL2N_VALUE not defined in mcuconf.h" #endif -#if !defined(STM32_PLL2PDIV_VALUE) -#error "STM32_PLL2PDIV_VALUE not defined in mcuconf.h" -#endif - #if STM32_RCC_PLL2_HAS_P && !defined(STM32_PLL2P_VALUE) #error "STM32_PLL2P_VALUE not defined in mcuconf.h" #endif diff --git a/os/hal/ports/STM32/LLD/RCCv1/stm32_pll3.inc b/os/hal/ports/STM32/LLD/RCCv1/stm32_pll3.inc index 43fc24f09..e10fd34de 100644 --- a/os/hal/ports/STM32/LLD/RCCv1/stm32_pll3.inc +++ b/os/hal/ports/STM32/LLD/RCCv1/stm32_pll3.inc @@ -62,10 +62,6 @@ #error "STM32_PLL3N_VALUE not defined in mcuconf.h" #endif -#if !defined(STM32_PLL3PDIV_VALUE) -#error "STM32_PLL3PDIV_VALUE not defined in mcuconf.h" -#endif - #if STM32_RCC_PLL3_HAS_P && !defined(STM32_PLL3P_VALUE) #error "STM32_PLL3P_VALUE not defined in mcuconf.h" #endif diff --git a/os/hal/ports/STM32/STM32H5xx/hal_lld.h b/os/hal/ports/STM32/STM32H5xx/hal_lld.h index 35df15d0e..bfbaa4efb 100644 --- a/os/hal/ports/STM32/STM32H5xx/hal_lld.h +++ b/os/hal/ports/STM32/STM32H5xx/hal_lld.h @@ -132,6 +132,13 @@ #define STM32_SW_HSE STM32_SW_FIELD(2U) #define STM32_SW_PLL1P STM32_SW_FIELD(3U) +#define STM32_SWS_MASK (3U << 3) +#define STM32_SWS_FIELD(n) ((n) << 3) +#define STM32_SWS_HSI STM32_SWS_FIELD(1U) +#define STM32_SWS_CSI STM32_SWS_FIELD(2U) +#define STM32_SWS_HSE STM32_SWS_FIELD(2U) +#define STM32_SWS_PLL1P STM32_SWS_FIELD(3U) + #define STM32_STOPWUCK_MASK (1U << 6) #define STM32_STOPWUCK_FIELD(n) ((n) << 6) #define STM32_STOPWUCK_HSI STM32_STOPWUCK_FIELD(0U) @@ -152,7 +159,7 @@ #define STM32_TIMPRE_HIGH STM32_TIMPRE_FIELD(1U) #define STM32_MCO1SEL_MASK (7U << 22) -#define STM32_MCO1PRE_FIELD(n) ((n) << 22) +#define STM32_MCO1SEL_FIELD(n) ((n) << 22) #define STM32_MCO1SEL_HSI STM32_MCO1PRE_FIELD(0U) #define STM32_MCO1SEL_LSE STM32_MCO1PRE_FIELD(1U) #define STM32_MCO1SEL_HSE STM32_MCO1PRE_FIELD(2U) @@ -164,7 +171,8 @@ #define STM32_MCO1PRE_NOCLOCK STM32_MCO1PRE_FIELD(0U) #define STM32_MCO2SEL_MASK (7U << 29) -#define STM32_MCO2PRE_FIELD(n) ((n) << 29) +#define STM32_MCO2SEL_FIELD(n) ((n) << 29) + #define STM32_MCO2SEL_SYSCLK STM32_MCO2PRE_FIELD(0U) #define STM32_MCO2SEL_PLL2P STM32_MCO2PRE_FIELD(1U) #define STM32_MCO2SEL_HSE STM32_MCO2PRE_FIELD(2U) @@ -1072,34 +1080,6 @@ #define STM32_LPUART1SEL STM32_LPUART1SEL_SYSCLK #endif -/** - * @brief I2C1 clock source. - */ -#if !defined(STM32_I2C1SEL) || defined(__DOXYGEN__) -#define STM32_I2C1SEL STM32_I2C1SEL_PCLK1 -#endif - -/** - * @brief I2C2 clock source. - */ -#if !defined(STM32_I2C2SEL) || defined(__DOXYGEN__) -#define STM32_I2C2SEL STM32_I2C2SEL_PCLK1 -#endif - -/** - * @brief I2C3 clock source. - */ -#if !defined(STM32_I2C3SEL) || defined(__DOXYGEN__) -#define STM32_I2C3SEL STM32_I2C3SEL_PCLK1 -#endif - -/** - * @brief I2C4 clock source. - */ -#if !defined(STM32_I2C4SEL) || defined(__DOXYGEN__) -#define STM32_I2C4SEL STM32_I2C4SEL_PCLK1 -#endif - /** * @brief LPTIM1 clock source. */ @@ -1443,7 +1423,7 @@ #define STM32_VOS2_PLLR_MIN 1000000 #define STM32_VOS2_PCLK1_MAX 150000000 #define STM32_VOS2_PCLK2_MAX 150000000 -#define STM32_VOS2_PCLK2_MAX 150000000 +#define STM32_VOS2_PCLK3_MAX 150000000 #define STM32_VOS2_ADCCLK_MAX 75000000 #define STM32_VOS2_0WS_THRESHOLD 30000000 @@ -1478,7 +1458,7 @@ #define STM32_VOS3_PLLR_MIN 1000000 #define STM32_VOS3_PCLK1_MAX 100000000 #define STM32_VOS3_PCLK2_MAX 100000000 -#define STM32_VOS3_PCLK2_MAX 100000000 +#define STM32_VOS3_PCLK3_MAX 100000000 #define STM32_VOS3_ADCCLK_MAX 50000000 #define STM32_VOS3_0WS_THRESHOLD 20000000 @@ -1505,6 +1485,7 @@ #define STM32_PLLVCO_MIN STM32_VOS0_PLLVCO_MIN #define STM32_PLLP_MAX STM32_VOS0_PLLP_MAX #define STM32_PLLP_MIN STM32_VOS0_PLLP_MIN +#define STM32_PLLP_MIN STM32_VOS0_PLLP_MIN #define STM32_PLLQ_MAX STM32_VOS0_PLLQ_MAX #define STM32_PLLQ_MIN STM32_VOS0_PLLQ_MIN #define STM32_PLLR_MAX STM32_VOS0_PLLR_MAX @@ -1581,6 +1562,7 @@ #define STM32_PLLR_MIN STM32_VOS2_PLLR_MIN #define STM32_PCLK1_MAX STM32_VOS2_PCLK1_MAX #define STM32_PCLK2_MAX STM32_VOS2_PCLK2_MAX +#define STM32_PCLK3_MAX STM32_VOS2_PCLK3_MAX #define STM32_ADCCLK_MAX STM32_VOS2_ADCCLK_MAX #define STM32_0WS_THRESHOLD STM32_VOS2_0WS_THRESHOLD @@ -1615,6 +1597,7 @@ #define STM32_PLLR_MIN STM32_VOS3_PLLR_MIN #define STM32_PCLK1_MAX STM32_VOS3_PCLK1_MAX #define STM32_PCLK2_MAX STM32_VOS3_PCLK2_MAX +#define STM32_PCLK3_MAX STM32_VOS3_PCLK3_MAX #define STM32_ADCCLK_MAX STM32_VOS3_ADCCLK_MAX #define STM32_0WS_THRESHOLD STM32_VOS3_0WS_THRESHOLD @@ -1631,6 +1614,56 @@ #error "invalid STM32_VOS value specified" #endif +/** + * @name PLLs dividers ranges + * @{ + */ +#define STM32_PLL1M_VALUE_MAX 63 +#define STM32_PLL1M_VALUE_MIN 1 +#define STM32_PLL1N_ODDVALID TRUE +#define STM32_PLL1N_VALUE_MAX 512 +#define STM32_PLL1N_VALUE_MIN 4 +#define STM32_PLL1P_ODDVALID FALSE +#define STM32_PLL1P_VALUE_MAX 128 +#define STM32_PLL1P_VALUE_MIN 2 +#define STM32_PLL1Q_ODDVALID TRUE +#define STM32_PLL1Q_VALUE_MAX 128 +#define STM32_PLL1Q_VALUE_MIN 1 +#define STM32_PLL1R_ODDVALID TRUE +#define STM32_PLL1R_VALUE_MAX 128 +#define STM32_PLL1R_VALUE_MIN 1 + +#define STM32_PLL2M_VALUE_MAX 63 +#define STM32_PLL2M_VALUE_MIN 1 +#define STM32_PLL2N_ODDVALID TRUE +#define STM32_PLL2N_VALUE_MAX 512 +#define STM32_PLL2N_VALUE_MIN 4 +#define STM32_PLL2P_ODDVALID TRUE +#define STM32_PLL2P_VALUE_MAX 128 +#define STM32_PLL2P_VALUE_MIN 2 +#define STM32_PLL2Q_ODDVALID TRUE +#define STM32_PLL2Q_VALUE_MAX 128 +#define STM32_PLL2Q_VALUE_MIN 1 +#define STM32_PLL2R_ODDVALID TRUE +#define STM32_PLL2R_VALUE_MAX 128 +#define STM32_PLL2R_VALUE_MIN 1 + +#define STM32_PLL3M_VALUE_MAX 63 +#define STM32_PLL3M_VALUE_MIN 1 +#define STM32_PLL3N_ODDVALID TRUE +#define STM32_PLL3N_VALUE_MAX 512 +#define STM32_PLL3N_VALUE_MIN 4 +#define STM32_PLL3P_ODDVALID TRUE +#define STM32_PLL3P_VALUE_MAX 128 +#define STM32_PLL3P_VALUE_MIN 2 +#define STM32_PLL3Q_ODDVALID TRUE +#define STM32_PLL3Q_VALUE_MAX 128 +#define STM32_PLL3Q_VALUE_MIN 1 +#define STM32_PLL3R_ODDVALID TRUE +#define STM32_PLL3R_VALUE_MAX 128 +#define STM32_PLL3R_VALUE_MIN 1 +/** @} */ + /* Clock handlers.*/ #include "stm32_lsi.inc" #include "stm32_csi.inc" diff --git a/os/hal/ports/STM32/STM32H5xx/platform.mk b/os/hal/ports/STM32/STM32H5xx/platform.mk index 894795d4d..e64e1f02e 100644 --- a/os/hal/ports/STM32/STM32H5xx/platform.mk +++ b/os/hal/ports/STM32/STM32H5xx/platform.mk @@ -26,6 +26,7 @@ endif # Drivers compatible with the platform. include $(CHIBIOS)/os/hal/ports/STM32/LLD/GPIOv2/driver.mk +include $(CHIBIOS)/os/hal/ports/STM32/LLD/RCCv1/driver.mk include $(CHIBIOS)/os/hal/ports/STM32/LLD/SYSTICKv1/driver.mk include $(CHIBIOS)/os/hal/ports/STM32/LLD/TIMv1/driver.mk include $(CHIBIOS)/os/hal/ports/STM32/LLD/USARTv3/driver.mk diff --git a/os/hal/ports/STM32/STM32H5xx/stm32_registry.h b/os/hal/ports/STM32/STM32H5xx/stm32_registry.h index cff418b7b..2fa88256e 100644 --- a/os/hal/ports/STM32/STM32H5xx/stm32_registry.h +++ b/os/hal/ports/STM32/STM32H5xx/stm32_registry.h @@ -43,6 +43,7 @@ /* RCC attributes.*/ #define STM32_RCC_HAS_LSI TRUE +#define STM32_RCC_HAS_LSI_PRESCALER FALSE #define STM32_RCC_HAS_CSI TRUE #define STM32_RCC_HAS_HSI48 TRUE #define STM32_RCC_HAS_HSI TRUE