making Eclipse happy
This commit is contained in:
rusefi
Fabien Poussin
parent
6feb76a6a2
commit
c924f7f7ce
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@ -1,256 +0,0 @@
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/*
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ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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/**
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* @file crt0_v6m.s
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* @brief Generic ARMv6-M (Cortex-M0/M1) startup file for ChibiOS.
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*
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* @addtogroup ARMCMx_GCC_STARTUP_V6M
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* @{
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*/
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/*===========================================================================*/
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/* Module constants. */
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/*===========================================================================*/
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#if !defined(FALSE) || defined(__DOXYGEN__)
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#define FALSE 0
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#endif
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#if !defined(TRUE) || defined(__DOXYGEN__)
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#define TRUE 1
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#endif
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#define CONTROL_MODE_PRIVILEGED 0
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#define CONTROL_MODE_UNPRIVILEGED 1
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#define CONTROL_USE_MSP 0
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#define CONTROL_USE_PSP 2
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/*===========================================================================*/
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/* Module pre-compile time settings. */
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/*===========================================================================*/
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/**
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* @brief Control special register initialization value.
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* @details The system is setup to run in privileged mode using the PSP
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* stack (dual stack mode).
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*/
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#if !defined(CRT0_CONTROL_INIT) || defined(__DOXYGEN__)
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#define CRT0_CONTROL_INIT (CONTROL_USE_PSP | \
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CONTROL_MODE_PRIVILEGED)
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#endif
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/**
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* @brief Core initialization switch.
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*/
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#if !defined(CRT0_INIT_CORE) || defined(__DOXYGEN__)
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#define CRT0_INIT_CORE TRUE
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#endif
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/**
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* @brief Stack segments initialization switch.
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*/
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#if !defined(CRT0_STACKS_FILL_PATTERN) || defined(__DOXYGEN__)
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#define CRT0_STACKS_FILL_PATTERN 0x55555555
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#endif
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/**
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* @brief Stack segments initialization switch.
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*/
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#if !defined(CRT0_INIT_STACKS) || defined(__DOXYGEN__)
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#define CRT0_INIT_STACKS TRUE
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#endif
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/**
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* @brief DATA segment initialization switch.
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*/
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#if !defined(CRT0_INIT_DATA) || defined(__DOXYGEN__)
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#define CRT0_INIT_DATA TRUE
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#endif
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/**
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* @brief BSS segment initialization switch.
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*/
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#if !defined(CRT0_INIT_BSS) || defined(__DOXYGEN__)
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#define CRT0_INIT_BSS TRUE
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#endif
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/**
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* @brief RAM areas initialization switch.
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*/
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#if !defined(CRT0_INIT_RAM_AREAS) || defined(__DOXYGEN__)
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#define CRT0_INIT_RAM_AREAS TRUE
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#endif
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/**
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* @brief Constructors invocation switch.
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*/
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#if !defined(CRT0_CALL_CONSTRUCTORS) || defined(__DOXYGEN__)
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#define CRT0_CALL_CONSTRUCTORS TRUE
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#endif
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/**
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* @brief Destructors invocation switch.
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*/
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#if !defined(CRT0_CALL_DESTRUCTORS) || defined(__DOXYGEN__)
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#define CRT0_CALL_DESTRUCTORS TRUE
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#endif
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/*===========================================================================*/
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/* Code section. */
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/*===========================================================================*/
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#if !defined(__DOXYGEN__)
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.cpu cortex-m0
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.fpu softvfp
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.thumb
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.text
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/*
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* Reset handler.
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*/
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.align 2
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.thumb_func
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.global Reset_Handler
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Reset_Handler:
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/* Interrupts are globally masked initially.*/
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cpsid i
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/* PSP stack pointers initialization.*/
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ldr r0, =__process_stack_end__
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msr PSP, r0
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/* CPU mode initialization as configured.*/
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movs r0, #CRT0_CONTROL_INIT
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msr CONTROL, r0
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isb
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#if CRT0_INIT_CORE == TRUE
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/* Core initialization.*/
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bl __core_init
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#endif
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/* Early initialization..*/
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bl __early_init
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#if CRT0_INIT_STACKS == TRUE
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ldr r0, =CRT0_STACKS_FILL_PATTERN
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/* Main Stack initialization. Note, it assumes that the
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stack size is a multiple of 4 so the linker file must
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ensure this.*/
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ldr r1, =__main_stack_base__
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ldr r2, =__main_stack_end__
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msloop:
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cmp r1, r2
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bge endmsloop
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str r0, [r1]
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add r1, r1, #4
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b msloop
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endmsloop:
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/* Process Stack initialization. Note, it assumes that the
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stack size is a multiple of 4 so the linker file must
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ensure this.*/
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ldr r1, =__process_stack_base__
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ldr r2, =__process_stack_end__
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psloop:
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cmp r1, r2
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bge endpsloop
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str r0, [r1]
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add r1, r1, #4
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b psloop
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endpsloop:
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#endif
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#if CRT0_INIT_DATA == TRUE
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/* Data initialization. Note, it assumes that the DATA size
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is a multiple of 4 so the linker file must ensure this.*/
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ldr r1, =_textdata
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ldr r2, =_data
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ldr r3, =_edata
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dloop:
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cmp r2, r3
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bge enddloop
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ldr r0, [r1]
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str r0, [r2]
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add r1, r1, #4
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add r2, r2, #4
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b dloop
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enddloop:
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#endif
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#if CRT0_INIT_BSS == TRUE
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/* BSS initialization. Note, it assumes that the DATA size
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is a multiple of 4 so the linker file must ensure this.*/
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movs r0, #0
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ldr r1, =_bss_start
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ldr r2, =_bss_end
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bloop:
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cmp r1, r2
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bge endbloop
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str r0, [r1]
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add r1, r1, #4
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b bloop
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endbloop:
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#endif
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#if CRT0_INIT_RAM_AREAS == TRUE
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/* RAM areas initialization.*/
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bl __init_ram_areas
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#endif
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/* Late initialization..*/
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bl __late_init
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#if CRT0_CALL_CONSTRUCTORS == TRUE
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/* Constructors invocation.*/
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ldr r4, =__init_array_start
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ldr r5, =__init_array_end
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initloop:
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cmp r4, r5
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bge endinitloop
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ldr r1, [r4]
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blx r1
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add r4, r4, #4
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b initloop
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endinitloop:
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#endif
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/* Main program invocation, r0 contains the returned value.*/
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bl main
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#if CRT0_CALL_DESTRUCTORS == TRUE
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/* Destructors invocation.*/
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ldr r4, =__fini_array_start
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ldr r5, =__fini_array_end
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finiloop:
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cmp r4, r5
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bge endfiniloop
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ldr r1, [r4]
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blx r1
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add r4, r4, #4
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b finiloop
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endfiniloop:
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#endif
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/* Branching to the defined exit handler.*/
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ldr r1, =__default_exit
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bx r1
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#endif
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/** @} */
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@ -1,319 +1,319 @@
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/*
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ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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/**
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* @file crt0_v7m.s
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* @brief Generic ARMv7-M (Cortex-M3/M4/M7) startup file for ChibiOS.
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*
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* @addtogroup ARMCMx_GCC_STARTUP_V7M
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* @{
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*/
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/*===========================================================================*/
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/* Module constants. */
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/*===========================================================================*/
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#if !defined(FALSE) || defined(__DOXYGEN__)
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#define FALSE 0
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#endif
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#if !defined(TRUE) || defined(__DOXYGEN__)
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#define TRUE 1
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#endif
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#define CONTROL_MODE_PRIVILEGED 0
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#define CONTROL_MODE_UNPRIVILEGED 1
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#define CONTROL_USE_MSP 0
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#define CONTROL_USE_PSP 2
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#define CONTROL_FPCA 4
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#define FPCCR_ASPEN (1 << 31)
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#define FPCCR_LSPEN (1 << 30)
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#define SCB_CPACR 0xE000ED88
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#define SCB_FPCCR 0xE000EF34
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#define SCB_FPDSCR 0xE000EF3C
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/*===========================================================================*/
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/* Module pre-compile time settings. */
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/*===========================================================================*/
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/**
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* @brief FPU initialization switch.
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*/
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#if !defined(CRT0_INIT_FPU) || defined(__DOXYGEN__)
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#if defined(CORTEX_USE_FPU) || defined(__DOXYGEN__)
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#define CRT0_INIT_FPU CORTEX_USE_FPU
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#else
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#define CRT0_INIT_FPU FALSE
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#endif
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#endif
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/**
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* @brief Control special register initialization value.
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* @details The system is setup to run in privileged mode using the PSP
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* stack (dual stack mode).
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*/
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#if !defined(CRT0_CONTROL_INIT) || defined(__DOXYGEN__)
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#define CRT0_CONTROL_INIT (CONTROL_USE_PSP | \
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CONTROL_MODE_PRIVILEGED)
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#endif
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/**
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* @brief Core initialization switch.
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*/
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#if !defined(CRT0_INIT_CORE) || defined(__DOXYGEN__)
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#define CRT0_INIT_CORE TRUE
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#endif
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/**
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* @brief Stack segments initialization switch.
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*/
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#if !defined(CRT0_STACKS_FILL_PATTERN) || defined(__DOXYGEN__)
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#define CRT0_STACKS_FILL_PATTERN 0x55555555
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#endif
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/**
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* @brief Stack segments initialization switch.
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*/
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#if !defined(CRT0_INIT_STACKS) || defined(__DOXYGEN__)
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#define CRT0_INIT_STACKS TRUE
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#endif
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/**
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* @brief DATA segment initialization switch.
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*/
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#if !defined(CRT0_INIT_DATA) || defined(__DOXYGEN__)
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#define CRT0_INIT_DATA TRUE
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#endif
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/**
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* @brief BSS segment initialization switch.
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*/
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#if !defined(CRT0_INIT_BSS) || defined(__DOXYGEN__)
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#define CRT0_INIT_BSS TRUE
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#endif
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/**
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* @brief RAM areas initialization switch.
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*/
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#if !defined(CRT0_INIT_RAM_AREAS) || defined(__DOXYGEN__)
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#define CRT0_INIT_RAM_AREAS TRUE
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#endif
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/**
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* @brief Constructors invocation switch.
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*/
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#if !defined(CRT0_CALL_CONSTRUCTORS) || defined(__DOXYGEN__)
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#define CRT0_CALL_CONSTRUCTORS TRUE
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#endif
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/**
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* @brief Destructors invocation switch.
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*/
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#if !defined(CRT0_CALL_DESTRUCTORS) || defined(__DOXYGEN__)
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#define CRT0_CALL_DESTRUCTORS TRUE
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#endif
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/**
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* @brief FPU FPCCR register initialization value.
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* @note Only used if @p CRT0_INIT_FPU is equal to @p TRUE.
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*/
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#if !defined(CRT0_FPCCR_INIT) || defined(__DOXYGEN__)
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#define CRT0_FPCCR_INIT (FPCCR_ASPEN | FPCCR_LSPEN)
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#endif
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/**
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* @brief CPACR register initialization value.
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* @note Only used if @p CRT0_INIT_FPU is equal to @p TRUE.
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*/
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#if !defined(CRT0_CPACR_INIT) || defined(__DOXYGEN__)
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#define CRT0_CPACR_INIT 0x00F00000
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#endif
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/*===========================================================================*/
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/* Code section. */
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/*===========================================================================*/
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#if !defined(__DOXYGEN__)
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.syntax unified
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.cpu cortex-m3
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#if CRT0_INIT_FPU == TRUE
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.fpu fpv4-sp-d16
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#else
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.fpu softvfp
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#endif
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.thumb
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.text
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/*
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* Reset handler.
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||||
*/
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.align 2
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.thumb_func
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.global Reset_Handler
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Reset_Handler:
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/* Interrupts are globally masked initially.*/
|
||||
cpsid i
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|
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/* PSP stack pointers initialization.*/
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||||
ldr r0, =__process_stack_end__
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msr PSP, r0
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#if CRT0_INIT_FPU == TRUE
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/* FPU FPCCR initialization.*/
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movw r0, #CRT0_FPCCR_INIT & 0xFFFF
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movt r0, #CRT0_FPCCR_INIT >> 16
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movw r1, #SCB_FPCCR & 0xFFFF
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movt r1, #SCB_FPCCR >> 16
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str r0, [r1]
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dsb
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isb
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/* CPACR initialization.*/
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movw r0, #CRT0_CPACR_INIT & 0xFFFF
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movt r0, #CRT0_CPACR_INIT >> 16
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movw r1, #SCB_CPACR & 0xFFFF
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movt r1, #SCB_CPACR >> 16
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str r0, [r1]
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dsb
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isb
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/* FPU FPSCR initially cleared.*/
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mov r0, #0
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vmsr FPSCR, r0
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/* FPU FPDSCR initially cleared.*/
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movw r1, #SCB_FPDSCR & 0xFFFF
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movt r1, #SCB_FPDSCR >> 16
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str r0, [r1]
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/* Enforcing FPCA bit in the CONTROL register.*/
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movs r0, #CRT0_CONTROL_INIT | CONTROL_FPCA
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#else
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movs r0, #CRT0_CONTROL_INIT
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#endif
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||||
/* CONTROL register initialization as configured.*/
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||||
msr CONTROL, r0
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||||
isb
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||||
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||||
#if CRT0_INIT_CORE == TRUE
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||||
/* Core initialization.*/
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||||
bl __core_init
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||||
#endif
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||||
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||||
/* Early initialization.*/
|
||||
bl __early_init
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||||
#if CRT0_INIT_STACKS == TRUE
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||||
ldr r0, =CRT0_STACKS_FILL_PATTERN
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||||
/* Main Stack initialization. Note, it assumes that the
|
||||
stack size is a multiple of 4 so the linker file must
|
||||
ensure this.*/
|
||||
ldr r1, =__main_stack_base__
|
||||
ldr r2, =__main_stack_end__
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||||
msloop:
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cmp r1, r2
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itt lo
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strlo r0, [r1], #4
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||||
blo msloop
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||||
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||||
/* Process Stack initialization. Note, it assumes that the
|
||||
stack size is a multiple of 4 so the linker file must
|
||||
ensure this.*/
|
||||
ldr r1, =__process_stack_base__
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||||
ldr r2, =__process_stack_end__
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||||
psloop:
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cmp r1, r2
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||||
itt lo
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||||
strlo r0, [r1], #4
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||||
blo psloop
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||||
#endif
|
||||
|
||||
#if CRT0_INIT_DATA == TRUE
|
||||
/* Data initialization. Note, it assumes that the DATA size
|
||||
is a multiple of 4 so the linker file must ensure this.*/
|
||||
ldr r1, =_textdata_start
|
||||
ldr r2, =_data_start
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||||
ldr r3, =_data_end
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||||
dloop:
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||||
cmp r2, r3
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||||
ittt lo
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||||
ldrlo r0, [r1], #4
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||||
strlo r0, [r2], #4
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||||
blo dloop
|
||||
#endif
|
||||
|
||||
#if CRT0_INIT_BSS == TRUE
|
||||
/* BSS initialization. Note, it assumes that the DATA size
|
||||
is a multiple of 4 so the linker file must ensure this.*/
|
||||
movs r0, #0
|
||||
ldr r1, =_bss_start
|
||||
ldr r2, =_bss_end
|
||||
bloop:
|
||||
cmp r1, r2
|
||||
itt lo
|
||||
strlo r0, [r1], #4
|
||||
blo bloop
|
||||
#endif
|
||||
|
||||
#if CRT0_INIT_RAM_AREAS == TRUE
|
||||
/* RAM areas initialization.*/
|
||||
bl __init_ram_areas
|
||||
#endif
|
||||
|
||||
/* Late initialization..*/
|
||||
bl __late_init
|
||||
|
||||
#if CRT0_CALL_CONSTRUCTORS == TRUE
|
||||
/* Constructors invocation.*/
|
||||
ldr r4, =__init_array_start
|
||||
ldr r5, =__init_array_end
|
||||
initloop:
|
||||
cmp r4, r5
|
||||
bge endinitloop
|
||||
ldr r1, [r4], #4
|
||||
blx r1
|
||||
b initloop
|
||||
endinitloop:
|
||||
#endif
|
||||
|
||||
/* Main program invocation, r0 contains the returned value.*/
|
||||
bl main
|
||||
|
||||
#if CRT0_CALL_DESTRUCTORS == TRUE
|
||||
/* Destructors invocation.*/
|
||||
ldr r4, =__fini_array_start
|
||||
ldr r5, =__fini_array_end
|
||||
finiloop:
|
||||
cmp r4, r5
|
||||
bge endfiniloop
|
||||
ldr r1, [r4], #4
|
||||
blx r1
|
||||
b finiloop
|
||||
endfiniloop:
|
||||
#endif
|
||||
|
||||
/* Branching to the defined exit handler.*/
|
||||
b __default_exit
|
||||
|
||||
#endif /* !defined(__DOXYGEN__) */
|
||||
|
||||
/** @} */
|
||||
/*
|
||||
ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
|
||||
|
||||
Licensed under the Apache License, Version 2.0 (the "License");
|
||||
you may not use this file except in compliance with the License.
|
||||
You may obtain a copy of the License at
|
||||
|
||||
http://www.apache.org/licenses/LICENSE-2.0
|
||||
|
||||
Unless required by applicable law or agreed to in writing, software
|
||||
distributed under the License is distributed on an "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
See the License for the specific language governing permissions and
|
||||
limitations under the License.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file crt0_v7m.s
|
||||
* @brief Generic ARMv7-M (Cortex-M3/M4/M7) startup file for ChibiOS.
|
||||
*
|
||||
* @addtogroup ARMCMx_GCC_STARTUP_V7M
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Module constants. */
|
||||
/*===========================================================================*/
|
||||
|
||||
#if !defined(FALSE) || defined(__DOXYGEN__)
|
||||
#define FALSE 0
|
||||
#endif
|
||||
|
||||
#if !defined(TRUE) || defined(__DOXYGEN__)
|
||||
#define TRUE 1
|
||||
#endif
|
||||
|
||||
#define CONTROL_MODE_PRIVILEGED 0
|
||||
#define CONTROL_MODE_UNPRIVILEGED 1
|
||||
#define CONTROL_USE_MSP 0
|
||||
#define CONTROL_USE_PSP 2
|
||||
#define CONTROL_FPCA 4
|
||||
|
||||
#define FPCCR_ASPEN (1 << 31)
|
||||
#define FPCCR_LSPEN (1 << 30)
|
||||
|
||||
#define SCB_CPACR 0xE000ED88
|
||||
#define SCB_FPCCR 0xE000EF34
|
||||
#define SCB_FPDSCR 0xE000EF3C
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Module pre-compile time settings. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @brief FPU initialization switch.
|
||||
*/
|
||||
#if !defined(CRT0_INIT_FPU) || defined(__DOXYGEN__)
|
||||
#if defined(CORTEX_USE_FPU) || defined(__DOXYGEN__)
|
||||
#define CRT0_INIT_FPU CORTEX_USE_FPU
|
||||
#else
|
||||
#define CRT0_INIT_FPU FALSE
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Control special register initialization value.
|
||||
* @details The system is setup to run in privileged mode using the PSP
|
||||
* stack (dual stack mode).
|
||||
*/
|
||||
#if !defined(CRT0_CONTROL_INIT) || defined(__DOXYGEN__)
|
||||
#define CRT0_CONTROL_INIT (CONTROL_USE_PSP | \
|
||||
CONTROL_MODE_PRIVILEGED)
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Core initialization switch.
|
||||
*/
|
||||
#if !defined(CRT0_INIT_CORE) || defined(__DOXYGEN__)
|
||||
#define CRT0_INIT_CORE TRUE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Stack segments initialization switch.
|
||||
*/
|
||||
#if !defined(CRT0_STACKS_FILL_PATTERN) || defined(__DOXYGEN__)
|
||||
#define CRT0_STACKS_FILL_PATTERN 0x55555555
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Stack segments initialization switch.
|
||||
*/
|
||||
#if !defined(CRT0_INIT_STACKS) || defined(__DOXYGEN__)
|
||||
#define CRT0_INIT_STACKS TRUE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief DATA segment initialization switch.
|
||||
*/
|
||||
#if !defined(CRT0_INIT_DATA) || defined(__DOXYGEN__)
|
||||
#define CRT0_INIT_DATA TRUE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief BSS segment initialization switch.
|
||||
*/
|
||||
#if !defined(CRT0_INIT_BSS) || defined(__DOXYGEN__)
|
||||
#define CRT0_INIT_BSS TRUE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief RAM areas initialization switch.
|
||||
*/
|
||||
#if !defined(CRT0_INIT_RAM_AREAS) || defined(__DOXYGEN__)
|
||||
#define CRT0_INIT_RAM_AREAS TRUE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Constructors invocation switch.
|
||||
*/
|
||||
#if !defined(CRT0_CALL_CONSTRUCTORS) || defined(__DOXYGEN__)
|
||||
#define CRT0_CALL_CONSTRUCTORS TRUE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Destructors invocation switch.
|
||||
*/
|
||||
#if !defined(CRT0_CALL_DESTRUCTORS) || defined(__DOXYGEN__)
|
||||
#define CRT0_CALL_DESTRUCTORS TRUE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief FPU FPCCR register initialization value.
|
||||
* @note Only used if @p CRT0_INIT_FPU is equal to @p TRUE.
|
||||
*/
|
||||
#if !defined(CRT0_FPCCR_INIT) || defined(__DOXYGEN__)
|
||||
#define CRT0_FPCCR_INIT (FPCCR_ASPEN | FPCCR_LSPEN)
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief CPACR register initialization value.
|
||||
* @note Only used if @p CRT0_INIT_FPU is equal to @p TRUE.
|
||||
*/
|
||||
#if !defined(CRT0_CPACR_INIT) || defined(__DOXYGEN__)
|
||||
#define CRT0_CPACR_INIT 0x00F00000
|
||||
#endif
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Code section. */
|
||||
/*===========================================================================*/
|
||||
|
||||
#if !defined(__DOXYGEN__)
|
||||
|
||||
.syntax unified
|
||||
.cpu cortex-m3
|
||||
#if CRT0_INIT_FPU == TRUE
|
||||
.fpu fpv4-sp-d16
|
||||
#else
|
||||
.fpu softvfp
|
||||
#endif
|
||||
|
||||
.thumb
|
||||
.text
|
||||
|
||||
/*
|
||||
* Reset handler.
|
||||
*/
|
||||
.align 2
|
||||
.thumb_func
|
||||
.global Reset_Handler
|
||||
Reset_Handler:
|
||||
/* Interrupts are globally masked initially.*/
|
||||
cpsid i
|
||||
|
||||
/* PSP stack pointers initialization.*/
|
||||
ldr r0, =__process_stack_end__
|
||||
msr PSP, r0
|
||||
|
||||
#if CRT0_INIT_FPU == TRUE
|
||||
/* FPU FPCCR initialization.*/
|
||||
movw r0, #CRT0_FPCCR_INIT & 0xFFFF
|
||||
movt r0, #CRT0_FPCCR_INIT >> 16
|
||||
movw r1, #SCB_FPCCR & 0xFFFF
|
||||
movt r1, #SCB_FPCCR >> 16
|
||||
str r0, [r1]
|
||||
dsb
|
||||
isb
|
||||
|
||||
/* CPACR initialization.*/
|
||||
movw r0, #CRT0_CPACR_INIT & 0xFFFF
|
||||
movt r0, #CRT0_CPACR_INIT >> 16
|
||||
movw r1, #SCB_CPACR & 0xFFFF
|
||||
movt r1, #SCB_CPACR >> 16
|
||||
str r0, [r1]
|
||||
dsb
|
||||
isb
|
||||
|
||||
/* FPU FPSCR initially cleared.*/
|
||||
mov r0, #0
|
||||
vmsr FPSCR, r0
|
||||
|
||||
/* FPU FPDSCR initially cleared.*/
|
||||
movw r1, #SCB_FPDSCR & 0xFFFF
|
||||
movt r1, #SCB_FPDSCR >> 16
|
||||
str r0, [r1]
|
||||
|
||||
/* Enforcing FPCA bit in the CONTROL register.*/
|
||||
movs r0, #CRT0_CONTROL_INIT | CONTROL_FPCA
|
||||
|
||||
#else
|
||||
movs r0, #CRT0_CONTROL_INIT
|
||||
#endif
|
||||
|
||||
/* CONTROL register initialization as configured.*/
|
||||
msr CONTROL, r0
|
||||
isb
|
||||
|
||||
#if CRT0_INIT_CORE == TRUE
|
||||
/* Core initialization.*/
|
||||
bl __core_init
|
||||
#endif
|
||||
|
||||
/* Early initialization.*/
|
||||
bl __early_init
|
||||
|
||||
#if CRT0_INIT_STACKS == TRUE
|
||||
ldr r0, =CRT0_STACKS_FILL_PATTERN
|
||||
/* Main Stack initialization. Note, it assumes that the
|
||||
stack size is a multiple of 4 so the linker file must
|
||||
ensure this.*/
|
||||
ldr r1, =__main_stack_base__
|
||||
ldr r2, =__main_stack_end__
|
||||
msloop:
|
||||
cmp r1, r2
|
||||
itt lo
|
||||
strlo r0, [r1], #4
|
||||
blo msloop
|
||||
|
||||
/* Process Stack initialization. Note, it assumes that the
|
||||
stack size is a multiple of 4 so the linker file must
|
||||
ensure this.*/
|
||||
ldr r1, =__process_stack_base__
|
||||
ldr r2, =__process_stack_end__
|
||||
psloop:
|
||||
cmp r1, r2
|
||||
itt lo
|
||||
strlo r0, [r1], #4
|
||||
blo psloop
|
||||
#endif
|
||||
|
||||
#if CRT0_INIT_DATA == TRUE
|
||||
/* Data initialization. Note, it assumes that the DATA size
|
||||
is a multiple of 4 so the linker file must ensure this.*/
|
||||
ldr r1, =_textdata_start
|
||||
ldr r2, =_data_start
|
||||
ldr r3, =_data_end
|
||||
dloop:
|
||||
cmp r2, r3
|
||||
ittt lo
|
||||
ldrlo r0, [r1], #4
|
||||
strlo r0, [r2], #4
|
||||
blo dloop
|
||||
#endif
|
||||
|
||||
#if CRT0_INIT_BSS == TRUE
|
||||
/* BSS initialization. Note, it assumes that the DATA size
|
||||
is a multiple of 4 so the linker file must ensure this.*/
|
||||
movs r0, #0
|
||||
ldr r1, =_bss_start
|
||||
ldr r2, =_bss_end
|
||||
bloop:
|
||||
cmp r1, r2
|
||||
itt lo
|
||||
strlo r0, [r1], #4
|
||||
blo bloop
|
||||
#endif
|
||||
|
||||
#if CRT0_INIT_RAM_AREAS == TRUE
|
||||
/* RAM areas initialization.*/
|
||||
bl __init_ram_areas
|
||||
#endif
|
||||
|
||||
/* Late initialization..*/
|
||||
bl __late_init
|
||||
|
||||
#if CRT0_CALL_CONSTRUCTORS == TRUE
|
||||
/* Constructors invocation.*/
|
||||
ldr r4, =__init_array_start
|
||||
ldr r5, =__init_array_end
|
||||
initloop:
|
||||
cmp r4, r5
|
||||
bge endinitloop
|
||||
ldr r1, [r4], #4
|
||||
blx r1
|
||||
b initloop
|
||||
endinitloop:
|
||||
#endif
|
||||
|
||||
/* Main program invocation, r0 contains the returned value.*/
|
||||
bl main
|
||||
|
||||
#if CRT0_CALL_DESTRUCTORS == TRUE
|
||||
/* Destructors invocation.*/
|
||||
ldr r4, =__fini_array_start
|
||||
ldr r5, =__fini_array_end
|
||||
finiloop:
|
||||
cmp r4, r5
|
||||
bge endfiniloop
|
||||
ldr r1, [r4], #4
|
||||
blx r1
|
||||
b finiloop
|
||||
endfiniloop:
|
||||
#endif
|
||||
|
||||
/* Branching to the defined exit handler.*/
|
||||
b __default_exit
|
||||
|
||||
#endif /* !defined(__DOXYGEN__) */
|
||||
|
||||
/** @} */
|
||||
Loading…
Reference in New Issue