git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@4778 35acf78f-673a-0410-8e92-d51de3d6d3f4
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/*
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ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
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2011,2012 Giovanni Di Sirio.
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This file is part of ChibiOS/RT.
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ChibiOS/RT is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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ChibiOS/RT is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include "ch.h"
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#include "hal.h"
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#if HAL_USE_PAL || defined(__DOXYGEN__)
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/**
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* @brief PAL setup.
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* @details Digital I/O ports static configuration as defined in @p board.h.
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* This variable is used by the HAL when initializing the PAL driver.
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*/
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const PALConfig pal_default_config =
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{
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{VAL_GPIOA_MODER, VAL_GPIOA_OTYPER, VAL_GPIOA_OSPEEDR, VAL_GPIOA_PUPDR,
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VAL_GPIOA_ODR, VAL_GPIOA_AFRL, VAL_GPIOA_AFRH},
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{VAL_GPIOB_MODER, VAL_GPIOB_OTYPER, VAL_GPIOB_OSPEEDR, VAL_GPIOB_PUPDR,
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VAL_GPIOB_ODR, VAL_GPIOB_AFRL, VAL_GPIOB_AFRH},
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{VAL_GPIOC_MODER, VAL_GPIOC_OTYPER, VAL_GPIOC_OSPEEDR, VAL_GPIOC_PUPDR,
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VAL_GPIOC_ODR, VAL_GPIOC_AFRL, VAL_GPIOC_AFRH},
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{VAL_GPIOD_MODER, VAL_GPIOD_OTYPER, VAL_GPIOD_OSPEEDR, VAL_GPIOD_PUPDR,
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VAL_GPIOD_ODR, VAL_GPIOD_AFRL, VAL_GPIOD_AFRH},
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{VAL_GPIOE_MODER, VAL_GPIOE_OTYPER, VAL_GPIOE_OSPEEDR, VAL_GPIOE_PUPDR,
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VAL_GPIOE_ODR, VAL_GPIOE_AFRL, VAL_GPIOE_AFRH},
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{VAL_GPIOF_MODER, VAL_GPIOF_OTYPER, VAL_GPIOF_OSPEEDR, VAL_GPIOF_PUPDR,
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VAL_GPIOF_ODR, VAL_GPIOF_AFRL, VAL_GPIOF_AFRH}
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};
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#endif
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/**
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* @brief Early initialization code.
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* @details This initialization must be performed just after stack setup
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* and before any other initialization.
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*/
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void __early_init(void) {
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stm32_clock_init();
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}
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#if HAL_USE_MMC_SPI || defined(__DOXYGEN__)
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/**
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* @brief MMC_SPI card detection.
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*/
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bool_t mmc_lld_is_card_inserted(MMCDriver *mmcp) {
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(void)mmcp;
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/* TODO: Fill the implementation.*/
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return TRUE;
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}
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/**
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* @brief MMC_SPI card write protection detection.
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*/
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bool_t mmc_lld_is_write_protected(MMCDriver *mmcp) {
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(void)mmcp;
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/* TODO: Fill the implementation.*/
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return FALSE;
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}
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#endif
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/**
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* @brief Board-specific initialization code.
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* @todo Add your board-specific code, if any.
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*/
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void boardInit(void) {
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}
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@ -0,0 +1,161 @@
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/*
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ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
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2011,2012 Giovanni Di Sirio.
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This file is part of ChibiOS/RT.
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ChibiOS/RT is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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ChibiOS/RT is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef _BOARD_H_
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#define _BOARD_H_
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/*
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* Setup for STMicroelectronics STM32F4-Discovery board.
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*/
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/*
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* Board identifier.
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*/
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#define BOARD_ST_STM32F3_DISCOVERY
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#define BOARD_NAME "STMicroelectronics STM32F3-Discovery"
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/*
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* Board oscillators-related settings.
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* NOTE: LSE not fitted.
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*/
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#if !defined(STM32_LSECLK)
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#define STM32_LSECLK 0
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#endif
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#if !defined(STM32_HSECLK)
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#define STM32_HSECLK 8000000
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#endif
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#define STM32_HSE_BYPASS
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/*
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* MCU type as defined in the ST header file stm32f30x.h.
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*/
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#define STM32F30X
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/*
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* IO pins assignments.
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*/
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/*
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* I/O ports initial setup, this configuration is established soon after reset
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* in the initialization code.
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* Please refer to the STM32 Reference Manual for details.
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*/
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#define PIN_MODE_INPUT(n) (0U << ((n) * 2))
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#define PIN_MODE_OUTPUT(n) (1U << ((n) * 2))
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#define PIN_MODE_ALTERNATE(n) (2U << ((n) * 2))
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#define PIN_MODE_ANALOG(n) (3U << ((n) * 2))
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#define PIN_ODR_LOW(n) (0U << (n))
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#define PIN_ODR_HIGH(n) (1U << (n))
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#define PIN_OTYPE_PUSHPULL(n) (0U << (n))
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#define PIN_OTYPE_OPENDRAIN(n) (1U << (n))
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#define PIN_OSPEED_2M(n) (0U << ((n) * 2))
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#define PIN_OSPEED_10M(n) (1U << ((n) * 2))
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#define PIN_OSPEED_50M(n) (3U << ((n) * 2))
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#define PIN_PUPDR_FLOATING(n) (0U << ((n) * 2))
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#define PIN_PUPDR_PULLUP(n) (1U << ((n) * 2))
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#define PIN_PUPDR_PULLDOWN(n) (2U << ((n) * 2))
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#define PIN_AFIO_AF(n, v) ((v##U) << ((n % 8) * 4))
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/*
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* GPIOA setup:
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*
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*/
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#define VAL_GPIOA_MODER 0
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#define VAL_GPIOA_OTYPER 0
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#define VAL_GPIOA_OSPEEDR 0
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#define VAL_GPIOA_PUPDR 0
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#define VAL_GPIOA_ODR 0
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#define VAL_GPIOA_AFRL 0
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#define VAL_GPIOA_AFRH 0
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/*
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* GPIOB setup:
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*
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*/
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#define VAL_GPIOB_MODER 0
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#define VAL_GPIOB_OTYPER 0
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#define VAL_GPIOB_OSPEEDR 0
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#define VAL_GPIOB_PUPDR 0
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#define VAL_GPIOB_ODR 0
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#define VAL_GPIOB_AFRL 0
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#define VAL_GPIOB_AFRH 0
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/*
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* GPIOC setup:
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*
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*/
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#define VAL_GPIOC_MODER 0
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#define VAL_GPIOC_OTYPER 0
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#define VAL_GPIOC_OSPEEDR 0
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#define VAL_GPIOC_PUPDR 0
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#define VAL_GPIOC_ODR 0
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#define VAL_GPIOC_AFRL 0
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#define VAL_GPIOC_AFRH 0
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/*
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* GPIOD setup:
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*
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0 */
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#define VAL_GPIOD_MODER 0
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#define VAL_GPIOD_OTYPER 0
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#define VAL_GPIOD_OSPEEDR 0
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#define VAL_GPIOD_PUPDR 0
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#define VAL_GPIOD_ODR 0
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#define VAL_GPIOD_AFRL 0
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#define VAL_GPIOD_AFRH 0
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/*
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* GPIOE setup:
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*
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*/
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#define VAL_GPIOE_MODER 0
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#define VAL_GPIOE_OTYPER 0
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#define VAL_GPIOE_OSPEEDR 0
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#define VAL_GPIOE_PUPDR 0
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#define VAL_GPIOE_ODR 0
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#define VAL_GPIOE_AFRL 0
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#define VAL_GPIOE_AFRH 0
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/*
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* GPIOF setup:
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*
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*/
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#define VAL_GPIOF_MODER 0
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#define VAL_GPIOF_OTYPER 0
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#define VAL_GPIOF_OSPEEDR 0
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#define VAL_GPIOF_PUPDR 0
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#define VAL_GPIOF_ODR 0
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#define VAL_GPIOF_AFRL 0
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#define VAL_GPIOF_AFRH 0
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#if !defined(_FROM_ASM_)
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#ifdef __cplusplus
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extern "C" {
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#endif
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void boardInit(void);
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#ifdef __cplusplus
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}
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#endif
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#endif /* _FROM_ASM_ */
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#endif /* _BOARD_H_ */
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@ -0,0 +1,5 @@
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# List of all the board related files.
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BOARDSRC = ${CHIBIOS}/boards/ST_STM32F3_DISCOVERY/board.c
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# Required include directories
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BOARDINC = ${CHIBIOS}/boards/ST_STM32F3_DISCOVERY
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File diff suppressed because it is too large
Load Diff
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* @brief Enables the ADC subsystem.
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*/
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#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__)
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#define HAL_USE_ADC TRUE
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#define HAL_USE_ADC FALSE
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#endif
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/**
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* @brief Enables the PWM subsystem.
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*/
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#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__)
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#define HAL_USE_PWM TRUE
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#define HAL_USE_PWM FALSE
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#endif
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/**
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* @brief Enables the SERIAL subsystem.
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*/
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#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__)
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#define HAL_USE_SERIAL TRUE
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#define HAL_USE_SERIAL FALSE
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#endif
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/**
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* @brief Enables the SPI subsystem.
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*/
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#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__)
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#define HAL_USE_SPI TRUE
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#define HAL_USE_SPI FALSE
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#endif
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/**
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@ -38,3 +38,31 @@
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* HAL driver system settings.
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*/
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#define STM32_NO_INIT FALSE
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#define STM32_PVD_ENABLE FALSE
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#define STM32_PLS STM32_PLS_LEV0
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#define STM32_HSI_ENABLED TRUE
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#define STM32_LSI_ENABLED TRUE
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#define STM32_HSE_ENABLED TRUE
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#define STM32_LSE_ENABLED FALSE
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#define STM32_SW STM32_SW_PLL
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#define STM32_PLLSRC STM32_PLLSRC_HSE
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#define STM32_PREDIV_VALUE 1
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#define STM32_PLLMUL_VALUE 8
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#define STM32_HPRE STM32_HPRE_DIV1
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#define STM32_PPRE1 STM32_PPRE1_DIV2
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#define STM32_PPRE2 STM32_PPRE2_DIV1
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#define STM32_MCOSEL STM32_MCOSEL_NOCLOCK
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#define STM32_ADC12PRES STM32_ADC12PRES_DIV1
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#define STM32_ADC34PRES STM32_ADC34PRES_DIV1
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#define STM32_USART1SW STM32_USART1SW_PCLK
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#define STM32_USART2SW STM32_USART2SW_PCLK
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#define STM32_USART3SW STM32_USART3SW_PCLK
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#define STM32_UART4SW STM32_UART4SW_PCLK
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#define STM32_UART5SW STM32_UART5SW_PCLK
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#define STM32_I2C1SW STM32_I2C1SW_SYSCLK
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#define STM32_I2C2SW STM32_I2C2SW_SYSCLK
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#define STM32_TIM1SW STM32_TIM1SW_PCLK2
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#define STM32_TIM8SW STM32_TIM8SW_PCLK2
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#define STM32_RTCSEL STM32_RTCSEL_LSI
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#define STM32_USB_CLOCK_REQUIRED TRUE
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#define STM32_USBPRE STM32_USBPRE_DIV1P5
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|
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@ -47,6 +47,10 @@
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RCC_AHB1ENR_GPIOGEN | RCC_AHB1ENR_GPIOHEN | \
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RCC_AHB1ENR_GPIOIEN)
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#define AHB1_LPEN_MASK AHB1_EN_MASK
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#elif defined(STM32F30X)
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#define AHB_EN_MASK (RCC_AHBENR_GPIOAEN | RCC_AHBENR_GPIOBEN | \
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RCC_AHBENR_GPIOCEN | RCC_AHBENR_GPIODEN | \
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RCC_AHBENR_GPIOEEN | RCC_AHBENR_GPIOFEN)
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#elif defined(STM32F4XX)
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#define AHB1_EN_MASK (RCC_AHB1ENR_GPIOAEN | RCC_AHB1ENR_GPIOBEN | \
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RCC_AHB1ENR_GPIOCEN | RCC_AHB1ENR_GPIODEN | \
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|
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@ -59,6 +59,7 @@
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#define PAL_STM32_OTYPE_OPENDRAIN (1 << 2)
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#define PAL_STM32_OSPEED_MASK (3 << 3)
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/* TODO: F0 and F3 are different from F2/F4 here.*/
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#define PAL_STM32_OSPEED_LOWEST (0 << 3)
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#define PAL_STM32_OSPEED_MID1 (1 << 3)
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#define PAL_STM32_OSPEED_MID2 (2 << 3)
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@ -171,19 +171,20 @@ void stm32_clock_init(void) {
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; /* Waits until LSI is stable. */
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#endif
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/* Clock settings.*/
|
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RCC->CFGR = STM32_MCOSEL | STM32_PLLMUL | STM32_PLLXTPRE |
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STM32_PLLSRC | STM32_ADCPRE | STM32_PPRE |
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STM32_HPRE;
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RCC->CFGR3 = STM32_ADCSW | STM32_CECSW | STM32_I2C1SW |
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STM32_USART1SW;
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#if STM32_ACTIVATE_PLL
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/* PLL activation.*/
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RCC->CFGR |= STM32_PLLMUL | STM32_PLLXTPRE | STM32_PLLSRC;
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RCC->CR |= RCC_CR_PLLON;
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while (!(RCC->CR & RCC_CR_PLLRDY))
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; /* Waits until PLL is stable. */
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#endif
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/* Clock settings.*/
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RCC->CFGR = STM32_MCOSEL | STM32_PLLMUL | STM32_PLLXTPRE |
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STM32_PLLSRC | STM32_ADCPRE | STM32_PPRE | STM32_HPRE;
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RCC->CFGR3 = STM32_ADCSW | STM32_CECSW | STM32_I2C1SW | STM32_USART1SW;
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/* Flash setup and final clock selection. */
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FLASH->ACR = STM32_FLASHBITS;
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|
|
|
@ -101,7 +101,7 @@ void hal_lld_init(void) {
|
|||
|
||||
/* Reset of all peripherals.*/
|
||||
rccResetAPB1(0xFFFFFFFF);
|
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rccResetAPB2(!RCC_APB2RSTR_DBGMCURST);
|
||||
rccResetAPB2(0xFFFFFFFF);
|
||||
|
||||
/* SysTick initialization using the system clock.*/
|
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SysTick->LOAD = STM32_HCLK / CH_FREQUENCY - 1;
|
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|
@ -166,23 +166,22 @@ void stm32_clock_init(void) {
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|||
; /* Waits until LSI is stable. */
|
||||
#endif
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||||
|
||||
/* Clock settings.*/
|
||||
RCC->CFGR = STM32_MCOSEL | STM32_USBPRE | STM32_PLLMUL |
|
||||
STM32_PLLSRC | STM32_PPRE1 | STM32_PPRE2 |
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STM32_HPRE;
|
||||
RCC->CFGR2 = STM32_ADC34PRES | STM32_ADC12PRES | STM32_PREDIV;
|
||||
RCC->CFGR3 = STM32_UART5SW | STM32_UART4SW | STM32_USART3SW |
|
||||
STM32_USART2SW | STM32_TIM8SW | STM32_TIM1SW |
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||||
STM32_I2C2SW | STM32_I2C1SW | STM32_USART1SW;
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||||
|
||||
#if STM32_ACTIVATE_PLL
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||||
/* PLL activation.*/
|
||||
RCC->CFGR |= STM32_PLLMUL | STM32_PLLXTPRE | STM32_PLLSRC;
|
||||
RCC->CR |= RCC_CR_PLLON;
|
||||
while (!(RCC->CR & RCC_CR_PLLRDY))
|
||||
; /* Waits until PLL is stable. */
|
||||
#endif
|
||||
|
||||
/* Clock settings.*/
|
||||
RCC->CFGR = STM32_MCOSEL | STM32_USBPRE | STM32_PLLMUL |
|
||||
STM32_PLLSRC | STM32_PPRE1 | STM32_PPRE1 |
|
||||
STM32_HPRE;
|
||||
RCC->CFGR = STM32_ADC43PRES | STM32_ADC12PRES | STM32_PREDIV;
|
||||
RCC->CFGR3 = STM32_UART5SW | STM32_UART4SW | STM32_USART3SW |
|
||||
STM32_USART2SW | STM32_TIM8SW | STM32_TIM1SW |
|
||||
STM32_I2C2SW | STM32_I2C1SW | STM32_USART1SW;
|
||||
|
||||
/* Flash setup and final clock selection. */
|
||||
FLASH->ACR = STM32_FLASHBITS;
|
||||
|
||||
|
|
|
@ -459,49 +459,49 @@
|
|||
* @brief Disables the PWR/RCC initialization in the HAL.
|
||||
*/
|
||||
#if !defined(STM32_NO_INIT) || defined(__DOXYGEN__)
|
||||
#define STM32_NO_INIT FALSE
|
||||
#define STM32_NO_INIT FALSE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Enables or disables the programmable voltage detector.
|
||||
*/
|
||||
#if !defined(STM32_PVD_ENABLE) || defined(__DOXYGEN__)
|
||||
#define STM32_PVD_ENABLE FALSE
|
||||
#define STM32_PVD_ENABLE FALSE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Sets voltage level for programmable voltage detector.
|
||||
*/
|
||||
#if !defined(STM32_PLS) || defined(__DOXYGEN__)
|
||||
#define STM32_PLS STM32_PLS_LEV0
|
||||
#define STM32_PLS STM32_PLS_LEV0
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Enables or disables the HSI clock source.
|
||||
*/
|
||||
#if !defined(STM32_HSI_ENABLED) || defined(__DOXYGEN__)
|
||||
#define STM32_HSI_ENABLED TRUE
|
||||
#define STM32_HSI_ENABLED TRUE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Enables or disables the LSI clock source.
|
||||
*/
|
||||
#if !defined(STM32_LSI_ENABLED) || defined(__DOXYGEN__)
|
||||
#define STM32_LSI_ENABLED FALSE
|
||||
#define STM32_LSI_ENABLED TRUE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Enables or disables the HSE clock source.
|
||||
*/
|
||||
#if !defined(STM32_HSE_ENABLED) || defined(__DOXYGEN__)
|
||||
#define STM32_HSE_ENABLED TRUE
|
||||
#define STM32_HSE_ENABLED TRUE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Enables or disables the LSE clock source.
|
||||
*/
|
||||
#if !defined(STM32_LSE_ENABLED) || defined(__DOXYGEN__)
|
||||
#define STM32_LSE_ENABLED FALSE
|
||||
#define STM32_LSE_ENABLED FALSE
|
||||
#endif
|
||||
|
||||
/**
|
||||
|
@ -512,7 +512,7 @@
|
|||
* a 8MHz crystal using the PLL.
|
||||
*/
|
||||
#if !defined(STM32_SW) || defined(__DOXYGEN__)
|
||||
#define STM32_SW STM32_SW_PLL
|
||||
#define STM32_SW STM32_SW_PLL
|
||||
#endif
|
||||
|
||||
/**
|
||||
|
@ -523,7 +523,7 @@
|
|||
* a 8MHz crystal using the PLL.
|
||||
*/
|
||||
#if !defined(STM32_PLLSRC) || defined(__DOXYGEN__)
|
||||
#define STM32_PLLSRC STM32_PLLSRC_HSE
|
||||
#define STM32_PLLSRC STM32_PLLSRC_HSE
|
||||
#endif
|
||||
|
||||
/**
|
||||
|
@ -534,7 +534,7 @@
|
|||
* a 8MHz crystal using the PLL.
|
||||
*/
|
||||
#if !defined(STM32_PREDIV_VALUE) || defined(__DOXYGEN__)
|
||||
#define STM32_PREDIV_VALUE 1
|
||||
#define STM32_PREDIV_VALUE 1
|
||||
#endif
|
||||
|
||||
/**
|
||||
|
@ -544,7 +544,7 @@
|
|||
* a 8MHz crystal using the PLL.
|
||||
*/
|
||||
#if !defined(STM32_PLLMUL_VALUE) || defined(__DOXYGEN__)
|
||||
#define STM32_PLLMUL_VALUE 8
|
||||
#define STM32_PLLMUL_VALUE 8
|
||||
#endif
|
||||
|
||||
/**
|
||||
|
@ -553,126 +553,126 @@
|
|||
* a 8MHz crystal using the PLL.
|
||||
*/
|
||||
#if !defined(STM32_HPRE) || defined(__DOXYGEN__)
|
||||
#define STM32_HPRE STM32_HPRE_DIV1
|
||||
#define STM32_HPRE STM32_HPRE_DIV1
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief APB1 prescaler value.
|
||||
*/
|
||||
#if !defined(STM32_PPRE1) || defined(__DOXYGEN__)
|
||||
#define STM32_PPRE1 STM32_PPRE1_DIV1
|
||||
#define STM32_PPRE1 STM32_PPRE1_DIV2
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief APB2 prescaler value.
|
||||
*/
|
||||
#if !defined(STM32_PPRE2) || defined(__DOXYGEN__)
|
||||
#define STM32_PPRE2 STM32_PPRE2_DIV1
|
||||
#define STM32_PPRE2 STM32_PPRE2_DIV1
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief MCO pin setting.
|
||||
*/
|
||||
#if !defined(STM32_MCOSEL) || defined(__DOXYGEN__)
|
||||
#define STM32_MCOSEL STM32_MCOSEL_NOCLOCK
|
||||
#define STM32_MCOSEL STM32_MCOSEL_NOCLOCK
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief ADC12 prescaler value.
|
||||
*/
|
||||
#if !defined(STM32_ADC12PRES) || defined(__DOXYGEN__)
|
||||
#define STM32_ADC12PRES STM32_ADC12PRES_DIV1
|
||||
#define STM32_ADC12PRES STM32_ADC12PRES_DIV1
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief ADC34 prescaler value.
|
||||
*/
|
||||
#if !defined(STM32_ADC34PRES) || defined(__DOXYGEN__)
|
||||
#define STM32_ADC34PRES STM32_ADC34PRES_DIV1
|
||||
#define STM32_ADC34PRES STM32_ADC34PRES_DIV1
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief USART1 clock source.
|
||||
*/
|
||||
#if !defined(STM32_USART1SW) || defined(__DOXYGEN__)
|
||||
#define STM32_USART1SW STM32_USART1SW_PCLK
|
||||
#define STM32_USART1SW STM32_USART1SW_PCLK
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief USART2 clock source.
|
||||
*/
|
||||
#if !defined(STM32_USART2SW) || defined(__DOXYGEN__)
|
||||
#define STM32_USART2SW STM32_USART2SW_PCLK
|
||||
#define STM32_USART2SW STM32_USART2SW_PCLK
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief USART3 clock source.
|
||||
*/
|
||||
#if !defined(STM32_USART3SW) || defined(__DOXYGEN__)
|
||||
#define STM32_USART3SW STM32_USART3SW_PCLK
|
||||
#define STM32_USART3SW STM32_USART3SW_PCLK
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief UART4 clock source.
|
||||
*/
|
||||
#if !defined(STM32_UART4SW) || defined(__DOXYGEN__)
|
||||
#define STM32_UART4SW STM32_UART4SW_PCLK
|
||||
#define STM32_UART4SW STM32_UART4SW_PCLK
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief UART5 clock source.
|
||||
*/
|
||||
#if !defined(STM32_UART5SW) || defined(__DOXYGEN__)
|
||||
#define STM32_UART5SW STM32_UART5SW_PCLK
|
||||
#define STM32_UART5SW STM32_UART5SW_PCLK
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief I2C1 clock source.
|
||||
*/
|
||||
#if !defined(STM32_I2C1SW) || defined(__DOXYGEN__)
|
||||
#define STM32_I2C1SW STM32_I2C1SW_SYSCLK
|
||||
#define STM32_I2C1SW STM32_I2C1SW_SYSCLK
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief I2C2 clock source.
|
||||
*/
|
||||
#if !defined(STM32_I2C2SW) || defined(__DOXYGEN__)
|
||||
#define STM32_I2C2SW STM32_I2C2SW_SYSCLK
|
||||
#define STM32_I2C2SW STM32_I2C2SW_SYSCLK
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief TIM1 clock source.
|
||||
*/
|
||||
#if !defined(STM32_TIM1SW) || defined(__DOXYGEN__)
|
||||
#define STM32_TIM1SW STM32_TIM1SW_PCLK2
|
||||
#define STM32_TIM1SW STM32_TIM1SW_PCLK2
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief TIM8 clock source.
|
||||
*/
|
||||
#if !defined(STM32_TIM8SW) || defined(__DOXYGEN__)
|
||||
#define STM32_TIM8SW STM32_TIM8SW_PCLK2
|
||||
#define STM32_TIM8SW STM32_TIM8SW_PCLK2
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief RTC clock source.
|
||||
*/
|
||||
#if !defined(STM32_RTCSEL) || defined(__DOXYGEN__)
|
||||
#define STM32_RTCSEL STM32_RTCSEL_LSI
|
||||
#define STM32_RTCSEL STM32_RTCSEL_LSI
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief USB clock setting.
|
||||
*/
|
||||
#if !defined(STM32_USB_CLOCK_REQUIRED) || defined(__DOXYGEN__)
|
||||
#define STM32_USB_CLOCK_REQUIRED TRUE
|
||||
#define STM32_USB_CLOCK_REQUIRED TRUE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief USB prescaler initialization.
|
||||
*/
|
||||
#if !defined(STM32_USBPRE) || defined(__DOXYGEN__)
|
||||
#define STM32_USBPRE STM32_USBPRE_DIV1P5
|
||||
#define STM32_USBPRE STM32_USBPRE_DIV1P5
|
||||
#endif
|
||||
/** @} */
|
||||
|
||||
|
@ -683,7 +683,7 @@
|
|||
/*
|
||||
* Configuration-related checks.
|
||||
*/
|
||||
#if !defined(STM32F3xx_MCUCONF)
|
||||
#if !defined(STM32F30x_MCUCONF)
|
||||
#error "Using a wrong mcuconf.h file, STM32F3xx_MCUCONF not defined"
|
||||
#endif
|
||||
|
||||
|
@ -1245,18 +1245,51 @@
|
|||
/* Driver data structures and types. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @brief Type representing a system clock frequency.
|
||||
*/
|
||||
typedef uint32_t halclock_t;
|
||||
|
||||
/**
|
||||
* @brief Type of the realtime free counter value.
|
||||
*/
|
||||
typedef uint32_t halrtcnt_t;
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver macros. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @brief Returns the current value of the system free running counter.
|
||||
* @note This service is implemented by returning the content of the
|
||||
* DWT_CYCCNT register.
|
||||
*
|
||||
* @return The value of the system free running counter of
|
||||
* type halrtcnt_t.
|
||||
*
|
||||
* @notapi
|
||||
*/
|
||||
#define hal_lld_get_counter_value() DWT_CYCCNT
|
||||
|
||||
/**
|
||||
* @brief Realtime counter frequency.
|
||||
* @note The DWT_CYCCNT register is incremented directly by the system
|
||||
* clock so this function returns STM32_HCLK.
|
||||
*
|
||||
* @return The realtime counter frequency of type halclock_t.
|
||||
*
|
||||
* @notapi
|
||||
*/
|
||||
#define hal_lld_get_counter_frequency() STM32_HCLK
|
||||
|
||||
/*===========================================================================*/
|
||||
/* External declarations. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/* STM32 ISR, DMA and RCC helpers.*/
|
||||
/*#include "stm32_isr.h"
|
||||
#include "stm32_dma.h"
|
||||
#include "stm32_rcc.h"*/
|
||||
#include "stm32_dma.h"*/
|
||||
#include "stm32_rcc.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
|
|
|
@ -0,0 +1,572 @@
|
|||
/*
|
||||
ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
|
||||
2011,2012 Giovanni Di Sirio.
|
||||
|
||||
This file is part of ChibiOS/RT.
|
||||
|
||||
ChibiOS/RT is free software; you can redistribute it and/or modify
|
||||
it under the terms of the GNU General Public License as published by
|
||||
the Free Software Foundation; either version 3 of the License, or
|
||||
(at your option) any later version.
|
||||
|
||||
ChibiOS/RT is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file STM32F3xx/stm32_rcc.h
|
||||
* @brief RCC helper driver header.
|
||||
* @note This file requires definitions from the ST header file
|
||||
* @p stm32f30x.h.
|
||||
*
|
||||
* @addtogroup STM32F30x_RCC
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifndef _STM32_RCC_
|
||||
#define _STM32_RCC_
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver constants. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver pre-compile time settings. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Derived constants and error checks. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver data structures and types. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver macros. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @name Generic RCC operations
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @brief Enables the clock of one or more peripheral on the APB1 bus.
|
||||
*
|
||||
* @param[in] mask APB1 peripherals mask
|
||||
* @param[in] lp low power enable flag
|
||||
*
|
||||
* @api
|
||||
*/
|
||||
#define rccEnableAPB1(mask, lp) { \
|
||||
RCC->APB1ENR |= (mask); \
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disables the clock of one or more peripheral on the APB1 bus.
|
||||
*
|
||||
* @param[in] mask APB1 peripherals mask
|
||||
* @param[in] lp low power enable flag
|
||||
*
|
||||
* @api
|
||||
*/
|
||||
#define rccDisableAPB1(mask, lp) { \
|
||||
RCC->APB1ENR &= ~(mask); \
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Resets one or more peripheral on the APB1 bus.
|
||||
*
|
||||
* @param[in] mask APB1 peripherals mask
|
||||
*
|
||||
* @api
|
||||
*/
|
||||
#define rccResetAPB1(mask) { \
|
||||
RCC->APB1RSTR |= (mask); \
|
||||
RCC->APB1RSTR = 0; \
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables the clock of one or more peripheral on the APB2 bus.
|
||||
*
|
||||
* @param[in] mask APB2 peripherals mask
|
||||
* @param[in] lp low power enable flag
|
||||
*
|
||||
* @api
|
||||
*/
|
||||
#define rccEnableAPB2(mask, lp) { \
|
||||
RCC->APB2ENR |= (mask); \
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disables the clock of one or more peripheral on the APB2 bus.
|
||||
*
|
||||
* @param[in] mask APB2 peripherals mask
|
||||
* @param[in] lp low power enable flag
|
||||
*
|
||||
* @api
|
||||
*/
|
||||
#define rccDisableAPB2(mask, lp) { \
|
||||
RCC->APB2ENR &= ~(mask); \
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Resets one or more peripheral on the APB2 bus.
|
||||
*
|
||||
* @param[in] mask APB2 peripherals mask
|
||||
*
|
||||
* @api
|
||||
*/
|
||||
#define rccResetAPB2(mask) { \
|
||||
RCC->APB2RSTR |= (mask); \
|
||||
RCC->APB2RSTR = 0; \
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables the clock of one or more peripheral on the AHB bus.
|
||||
*
|
||||
* @param[in] mask AHB peripherals mask
|
||||
* @param[in] lp low power enable flag
|
||||
*
|
||||
* @api
|
||||
*/
|
||||
#define rccEnableAHB(mask, lp) { \
|
||||
RCC->AHBENR |= (mask); \
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disables the clock of one or more peripheral on the AHB bus.
|
||||
*
|
||||
* @param[in] mask AHB peripherals mask
|
||||
* @param[in] lp low power enable flag
|
||||
*
|
||||
* @api
|
||||
*/
|
||||
#define rccDisableAHB(mask, lp) { \
|
||||
RCC->AHBENR &= ~(mask); \
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Resets one or more peripheral on the AHB bus.
|
||||
*
|
||||
* @param[in] mask AHB peripherals mask
|
||||
*
|
||||
* @api
|
||||
*/
|
||||
#define rccResetAHB(mask) { \
|
||||
RCC->AHBRSTR |= (mask); \
|
||||
RCC->AHBRSTR = 0; \
|
||||
}
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @name ADC peripherals specific RCC operations
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @brief Enables the ADC1 peripheral clock.
|
||||
*
|
||||
* @param[in] lp low power enable flag
|
||||
*
|
||||
* @api
|
||||
*/
|
||||
#define rccEnableADC1(lp) rccEnableAPB2(RCC_APB2ENR_ADC1EN, lp)
|
||||
|
||||
/**
|
||||
* @brief Disables the ADC1 peripheral clock.
|
||||
*
|
||||
* @param[in] lp low power enable flag
|
||||
*
|
||||
* @api
|
||||
*/
|
||||
#define rccDisableADC1(lp) rccDisableAPB2(RCC_APB2ENR_ADC1EN, lp)
|
||||
|
||||
/**
|
||||
* @brief Resets the ADC1 peripheral.
|
||||
*
|
||||
* @api
|
||||
*/
|
||||
#define rccResetADC1() rccResetAPB2(RCC_APB2RSTR_ADC1RST)
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @name DMA peripheral specific RCC operations
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @brief Enables the DMA1 peripheral clock.
|
||||
*
|
||||
* @param[in] lp low power enable flag
|
||||
*
|
||||
* @api
|
||||
*/
|
||||
#define rccEnableDMA1(lp) rccEnableAHB(RCC_AHBENR_DMA1EN, lp)
|
||||
|
||||
/**
|
||||
* @brief Disables the DMA1 peripheral clock.
|
||||
*
|
||||
* @param[in] lp low power enable flag
|
||||
*
|
||||
* @api
|
||||
*/
|
||||
#define rccDisableDMA1(lp) rccDisableAHB(RCC_AHBENR_DMA1EN, lp)
|
||||
|
||||
/**
|
||||
* @brief Resets the DMA1 peripheral.
|
||||
*
|
||||
* @api
|
||||
*/
|
||||
#define rccResetDMA1() rccResetAHB(RCC_AHBRSTR_DMA1RST)
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @name PWR interface specific RCC operations
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @brief Enables the PWR interface clock.
|
||||
* @note The @p lp parameter is ignored in this family.
|
||||
*
|
||||
* @param[in] lp low power enable flag
|
||||
*
|
||||
* @api
|
||||
*/
|
||||
#define rccEnablePWRInterface(lp) rccEnableAPB1(RCC_APB1ENR_PWREN, lp)
|
||||
|
||||
/**
|
||||
* @brief Disables PWR interface clock.
|
||||
* @note The @p lp parameter is ignored in this family.
|
||||
*
|
||||
* @param[in] lp low power enable flag
|
||||
*
|
||||
* @api
|
||||
*/
|
||||
#define rccDisablePWRInterface(lp) rccDisableAPB1(RCC_APB1ENR_PWREN, lp)
|
||||
|
||||
/**
|
||||
* @brief Resets the PWR interface.
|
||||
*
|
||||
* @api
|
||||
*/
|
||||
#define rccResetPWRInterface() rccResetAPB1(RCC_APB1RSTR_PWRRST)
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @name I2C peripherals specific RCC operations
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @brief Enables the I2C1 peripheral clock.
|
||||
*
|
||||
* @param[in] lp low power enable flag
|
||||
*
|
||||
* @api
|
||||
*/
|
||||
#define rccEnableI2C1(lp) rccEnableAPB1(RCC_APB1ENR_I2C1EN, lp)
|
||||
|
||||
/**
|
||||
* @brief Disables the I2C1 peripheral clock.
|
||||
*
|
||||
* @param[in] lp low power enable flag
|
||||
*
|
||||
* @api
|
||||
*/
|
||||
#define rccDisableI2C1(lp) rccDisableAPB1(RCC_APB1ENR_I2C1EN, lp)
|
||||
|
||||
/**
|
||||
* @brief Resets the I2C1 peripheral.
|
||||
*
|
||||
* @api
|
||||
*/
|
||||
#define rccResetI2C1() rccResetAPB1(RCC_APB1RSTR_I2C1RST)
|
||||
|
||||
/**
|
||||
* @brief Enables the I2C2 peripheral clock.
|
||||
*
|
||||
* @param[in] lp low power enable flag
|
||||
*
|
||||
* @api
|
||||
*/
|
||||
#define rccEnableI2C2(lp) rccEnableAPB1(RCC_APB1ENR_I2C2EN, lp)
|
||||
|
||||
/**
|
||||
* @brief Disables the I2C2 peripheral clock.
|
||||
*
|
||||
* @param[in] lp low power enable flag
|
||||
*
|
||||
* @api
|
||||
*/
|
||||
#define rccDisableI2C2(lp) rccDisableAPB1(RCC_APB1ENR_I2C2EN, lp)
|
||||
|
||||
/**
|
||||
* @brief Resets the I2C2 peripheral.
|
||||
*
|
||||
* @api
|
||||
*/
|
||||
#define rccResetI2C2() rccResetAPB1(RCC_APB1RSTR_I2C2RST)
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @name SPI peripherals specific RCC operations
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @brief Enables the SPI1 peripheral clock.
|
||||
*
|
||||
* @param[in] lp low power enable flag
|
||||
*
|
||||
* @api
|
||||
*/
|
||||
#define rccEnableSPI1(lp) rccEnableAPB2(RCC_APB2ENR_SPI1EN, lp)
|
||||
|
||||
/**
|
||||
* @brief Disables the SPI1 peripheral clock.
|
||||
*
|
||||
* @param[in] lp low power enable flag
|
||||
*
|
||||
* @api
|
||||
*/
|
||||
#define rccDisableSPI1(lp) rccDisableAPB2(RCC_APB2ENR_SPI1EN, lp)
|
||||
|
||||
/**
|
||||
* @brief Resets the SPI1 peripheral.
|
||||
*
|
||||
* @api
|
||||
*/
|
||||
#define rccResetSPI1() rccResetAPB2(RCC_APB2RSTR_SPI1RST)
|
||||
|
||||
/**
|
||||
* @brief Enables the SPI2 peripheral clock.
|
||||
*
|
||||
* @param[in] lp low power enable flag
|
||||
*
|
||||
* @api
|
||||
*/
|
||||
#define rccEnableSPI2(lp) rccEnableAPB1(RCC_APB1ENR_SPI2EN, lp)
|
||||
|
||||
/**
|
||||
* @brief Disables the SPI2 peripheral clock.
|
||||
*
|
||||
* @param[in] lp low power enable flag
|
||||
*
|
||||
* @api
|
||||
*/
|
||||
#define rccDisableSPI2(lp) rccDisableAPB1(RCC_APB1ENR_SPI2EN, lp)
|
||||
|
||||
/**
|
||||
* @brief Resets the SPI2 peripheral.
|
||||
*
|
||||
* @api
|
||||
*/
|
||||
#define rccResetSPI2() rccResetAPB1(RCC_APB1RSTR_SPI2RST)
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @name TIM peripherals specific RCC operations
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @brief Enables the TIM2 peripheral clock.
|
||||
*
|
||||
* @param[in] lp low power enable flag
|
||||
*
|
||||
* @api
|
||||
*/
|
||||
#define rccEnableTIM2(lp) rccEnableAPB1(RCC_APB1ENR_TIM2EN, lp)
|
||||
|
||||
/**
|
||||
* @brief Disables the TIM2 peripheral clock.
|
||||
*
|
||||
* @param[in] lp low power enable flag
|
||||
*
|
||||
* @api
|
||||
*/
|
||||
#define rccDisableTIM2(lp) rccDisableAPB1(RCC_APB1ENR_TIM2EN, lp)
|
||||
|
||||
/**
|
||||
* @brief Resets the TIM2 peripheral.
|
||||
*
|
||||
* @api
|
||||
*/
|
||||
#define rccResetTIM2() rccResetAPB1(RCC_APB1RSTR_TIM2RST)
|
||||
|
||||
/**
|
||||
* @brief Enables the TIM3 peripheral clock.
|
||||
*
|
||||
* @param[in] lp low power enable flag
|
||||
*
|
||||
* @api
|
||||
*/
|
||||
#define rccEnableTIM3(lp) rccEnableAPB1(RCC_APB1ENR_TIM3EN, lp)
|
||||
|
||||
/**
|
||||
* @brief Disables the TIM3 peripheral clock.
|
||||
*
|
||||
* @param[in] lp low power enable flag
|
||||
*
|
||||
* @api
|
||||
*/
|
||||
#define rccDisableTIM3(lp) rccDisableAPB1(RCC_APB1ENR_TIM3EN, lp)
|
||||
|
||||
/**
|
||||
* @brief Resets the TIM3 peripheral.
|
||||
*
|
||||
* @api
|
||||
*/
|
||||
#define rccResetTIM3() rccResetAPB1(RCC_APB1RSTR_TIM3RST)
|
||||
|
||||
/**
|
||||
* @brief Enables the TIM4 peripheral clock.
|
||||
*
|
||||
* @param[in] lp low power enable flag
|
||||
*
|
||||
* @api
|
||||
*/
|
||||
#define rccEnableTIM4(lp) rccEnableAPB1(RCC_APB1ENR_TIM4EN, lp)
|
||||
|
||||
/**
|
||||
* @brief Disables the TIM4 peripheral clock.
|
||||
*
|
||||
* @param[in] lp low power enable flag
|
||||
*
|
||||
* @api
|
||||
*/
|
||||
#define rccDisableTIM4(lp) rccDisableAPB1(RCC_APB1ENR_TIM4EN, lp)
|
||||
|
||||
/**
|
||||
* @brief Resets the TIM4 peripheral.
|
||||
*
|
||||
* @api
|
||||
*/
|
||||
#define rccResetTIM4() rccResetAPB1(RCC_APB1RSTR_TIM4RST)
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @name USART/UART peripherals specific RCC operations
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @brief Enables the USART1 peripheral clock.
|
||||
*
|
||||
* @param[in] lp low power enable flag
|
||||
*
|
||||
* @api
|
||||
*/
|
||||
#define rccEnableUSART1(lp) rccEnableAPB2(RCC_APB2ENR_USART1EN, lp)
|
||||
|
||||
/**
|
||||
* @brief Disables the USART1 peripheral clock.
|
||||
*
|
||||
* @param[in] lp low power enable flag
|
||||
*
|
||||
* @api
|
||||
*/
|
||||
#define rccDisableUSART1(lp) rccDisableAPB2(RCC_APB2ENR_USART1EN, lp)
|
||||
|
||||
/**
|
||||
* @brief Resets the USART1 peripheral.
|
||||
*
|
||||
* @api
|
||||
*/
|
||||
#define rccResetUSART1() rccResetAPB2(RCC_APB2RSTR_USART1RST)
|
||||
|
||||
/**
|
||||
* @brief Enables the USART2 peripheral clock.
|
||||
*
|
||||
* @param[in] lp low power enable flag
|
||||
*
|
||||
* @api
|
||||
*/
|
||||
#define rccEnableUSART2(lp) rccEnableAPB1(RCC_APB1ENR_USART2EN, lp)
|
||||
|
||||
/**
|
||||
* @brief Disables the USART2 peripheral clock.
|
||||
*
|
||||
* @param[in] lp low power enable flag
|
||||
*
|
||||
* @api
|
||||
*/
|
||||
#define rccDisableUSART2(lp) rccDisableAPB1(RCC_APB1ENR_USART2EN, lp)
|
||||
|
||||
/**
|
||||
* @brief Resets the USART2 peripheral.
|
||||
*
|
||||
* @api
|
||||
*/
|
||||
#define rccResetUSART2() rccResetAPB1(RCC_APB1RSTR_USART2RST)
|
||||
|
||||
/**
|
||||
* @brief Enables the USART3 peripheral clock.
|
||||
*
|
||||
* @param[in] lp low power enable flag
|
||||
*
|
||||
* @api
|
||||
*/
|
||||
#define rccEnableUSART3(lp) rccEnableAPB1(RCC_APB1ENR_USART3EN, lp)
|
||||
|
||||
/**
|
||||
* @brief Disables the USART3 peripheral clock.
|
||||
*
|
||||
* @param[in] lp low power enable flag
|
||||
*
|
||||
* @api
|
||||
*/
|
||||
#define rccDisableUSART3(lp) rccDisableAPB1(RCC_APB1ENR_USART3EN, lp)
|
||||
|
||||
/**
|
||||
* @brief Resets the USART3 peripheral.
|
||||
*
|
||||
* @api
|
||||
*/
|
||||
#define rccResetUSART3() rccResetAPB1(RCC_APB1RSTR_USART3RST)
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @name USB peripheral specific RCC operations
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @brief Enables the USB peripheral clock.
|
||||
*
|
||||
* @param[in] lp low power enable flag
|
||||
*
|
||||
* @api
|
||||
*/
|
||||
#define rccEnableUSB(lp) rccEnableAPB1(RCC_APB1ENR_USBEN, lp)
|
||||
|
||||
/**
|
||||
* @brief Disables the USB peripheral clock.
|
||||
*
|
||||
* @param[in] lp low power enable flag
|
||||
*
|
||||
* @api
|
||||
*/
|
||||
#define rccDisableUSB(lp) rccDisableAPB1(RCC_APB1ENR_USBEN, lp)
|
||||
|
||||
/**
|
||||
* @brief Resets the USB peripheral.
|
||||
*
|
||||
* @api
|
||||
*/
|
||||
#define rccResetUSB() rccResetAPB1(RCC_APB1RSTR_USBRST)
|
||||
/** @} */
|
||||
|
||||
/*===========================================================================*/
|
||||
/* External declarations. */
|
||||
/*===========================================================================*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _STM32_RCC_ */
|
||||
|
||||
/** @} */
|
|
@ -554,7 +554,8 @@ typedef struct
|
|||
/**
|
||||
* @brief General Purpose I/O
|
||||
*/
|
||||
|
||||
/* CHIBIOS FIX */
|
||||
#if 0
|
||||
typedef struct
|
||||
{
|
||||
__IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
|
||||
|
@ -572,6 +573,7 @@ typedef struct
|
|||
__IO uint16_t BRR; /*!< GPIO bit reset register, Address offset: 0x28 */
|
||||
uint16_t RESERVED3; /*!< Reserved, 0x2A */
|
||||
}GPIO_TypeDef;
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Operational Amplifier (OPAMP)
|
||||
|
|
|
@ -26,6 +26,8 @@
|
|||
* @{
|
||||
*/
|
||||
|
||||
/* TODO: LSEBYP like in F3.*/
|
||||
|
||||
#include "ch.h"
|
||||
#include "hal.h"
|
||||
|
||||
|
|
Loading…
Reference in New Issue