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ChibiOS
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Reorganization of F4 port, not finished yet. 

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@12026 110e8d01-0319-4d1e-a829-52ad28d1bb01
This commit is contained in:
Giovanni Di Sirio 2018-05-12 12:29:40 +00:00
parent d6b969dac4
commit ca256de846
5 changed files with 4639 additions and 125 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

95
os/hal/ports/STM32/STM32F4xx/hal_lld.c
View File

@ -234,15 +234,9 @@ void stm32_clock_init(void) {
#endif /* STM32_ACTIVATE_PLL */
#if STM32_ACTIVATE_PLLI2S
#if defined(STM32F413xx)
/* PLLI2S activation.*/
RCC->PLLI2SCFGR = STM32_PLLI2SR | STM32_PLLI2SN | STM32_PLLI2SP |
STM32_I2SSRC | STM32_PLLI2SQ | STM32_PLLI2SM;
#else
/* PLLI2S activation.*/
RCC->PLLI2SCFGR = STM32_PLLI2SR | STM32_PLLI2SN | STM32_PLLI2SP |
STM32_PLLI2SQ | STM32_PLLI2SM;
#endif
STM32_PLLI2SSRC | STM32_PLLI2SQ | STM32_PLLI2SM;
RCC->CR |= RCC_CR_PLLI2SON;
/* Waiting for PLL lock.*/
@ -261,73 +255,38 @@ void stm32_clock_init(void) {
;
#endif /* STM32_ACTIVATE_PLLSAI */
#if defined(STM32F413xx)
/* Other clock-related settings (dividers, MCO etc).*/
RCC->CFGR = STM32_MCO2PRE | STM32_MCO2SEL | STM32_MCO1PRE | STM32_MCO1SEL |
STM32_RTCPRE | STM32_PPRE2 | STM32_PPRE1 |
STM32_HPRE;
#else
/* Other clock-related settings (dividers, MCO etc).*/
RCC->CFGR = STM32_MCO2PRE | STM32_MCO2SEL | STM32_MCO1PRE | STM32_MCO1SEL |
STM32_I2SSRC | STM32_RTCPRE | STM32_PPRE2 | STM32_PPRE1 |
STM32_HPRE;
#if STM32_HAS_RCC_DCKCFGR
/* DCKCFGR register initialization, note, must take care of the _OFF
pseudo settings.*/
{
uint32_t dckcfgr = 0;
#if STM32_SAI2SEL != STM32_SAI2SEL_OFF
dckcfgr |= STM32_SAI2SEL;
#endif
#if STM32_SAI1SEL != STM32_SAI1SEL_OFF
dckcfgr |= STM32_SAI1SEL;
#endif
#if STM32_PLLSAIDIVR != STM32_PLLSAIDIVR_OFF
dckcfgr |= STM32_PLLSAIDIVR;
#endif
#if defined(STM32F469xx) || defined(STM32F479xx)
/* Special case, in those devices STM32_CK48MSEL is located in the
DCKCFGR register.*/
dckcfgr |= STM32_CK48MSEL;
#endif
RCC->DCKCFGR = dckcfgr |
STM32_TIMPRE | STM32_PLLSAIDIVR |
STM32_PLLSAIDIVQ | STM32_PLLI2SDIVQ;
}
#endif
#if defined(STM32F446xx)
/* DCKCFGR register initialization, note, must take care of the _OFF
pseudo settings.*/
{
uint32_t dckcfgr = 0;
#if STM32_SAI2SEL != STM32_SAI2SEL_OFF
dckcfgr |= STM32_SAI2SEL;
#endif
#if STM32_SAI1SEL != STM32_SAI1SEL_OFF
dckcfgr |= STM32_SAI1SEL;
#endif
#if STM32_PLLSAIDIVR != STM32_PLLSAIDIVR_OFF
dckcfgr |= STM32_PLLSAIDIVR;
#endif
#if STM32_TIMPRE == STM32_TIMPRE_HCLK
dckcfgr |= STM32_TIMPRE_HCLK;
#endif
RCC->DCKCFGR = dckcfgr | STM32_PLLI2SDIVQ | STM32_PLLSAIDIVQ;
}
RCC->DCKCFGR2 = STM32_CK48MSEL;
#elif defined(STM32F469xx) || defined(STM32F479xx)
/* DCKCFGR register initialization, note, must take care of the _OFF
pseudo settings.*/
{
uint32_t dckcfgr = 0;
#if STM32_SAI2SEL != STM32_SAI2SEL_OFF
dckcfgr |= STM32_SAI2SEL;
#endif
#if STM32_SAI1SEL != STM32_SAI1SEL_OFF
dckcfgr |= STM32_SAI1SEL;
#endif
#if STM32_PLLSAIDIVR != STM32_PLLSAIDIVR_OFF
dckcfgr |= STM32_PLLSAIDIVR;
#endif
RCC->DCKCFGR = dckcfgr | STM32_PLLI2SDIVQ | STM32_PLLSAIDIVQ |
STM32_CK48MSEL;
}
#elif defined(STM32F413xx)
/* DCKCFGR register initialization. */
{
uint32_t dckcfgr = 0;
#if STM32_SAI2SEL != STM32_SAI2SEL_OFF
dckcfgr |= STM32_SAI2SEL;
#endif
#if STM32_SAI1SEL != STM32_SAI1SEL_OFF
dckcfgr |= STM32_SAI1SEL;
#endif
#if STM32_PLLSAIDIVR != STM32_PLLSAIDIVR_OFF
dckcfgr |= STM32_PLLSAIDIVR;
#endif
#if STM32_TIMPRE == STM32_TIMPRE_HCLK
dckcfgr |= STM32_TIMPRE_HCLK;
#endif
RCC->DCKCFGR = dckcfgr | STM32_PLLI2SDIVQ | STM32_PLLSAIDIVQ;
}
#if STM32_HAS_RCC_DCKCFGR2
/* DCKCFGR2 register initialization.*/
RCC->DCKCFGR2 = STM32_CK48MSEL;
#endif

153
os/hal/ports/STM32/STM32F4xx/hal_lld.h
View File

@ -448,8 +448,9 @@
#define STM32_PLLI2SP_DIV6 (2 << 16) /**< PLLI2S clock divided by 6. */
#define STM32_PLLI2SP_DIV8 (3 << 16) /**< PLLI2S clock divided by 8. */
#define STM32_PLLI2SSRC_MASK (1 << 22) /**< PLLI2SSRC mask. */
#define STM32_PLLI2SSRC_CKIN (0 << 22) /**< PLLI2SSRC is CK_IN. */
#define STM32_PLLI2SSRC_I2SCKIN (1 << 22) /**< PLLI2SSRC is I2S_CKIN. */
#define STM32_PLLI2SSRC_PLLSRC (0 << 22) /**< PLLI2SSRC is selected PLL
source. */
#define STM32_PLLI2SSRC_CKIN (1 << 22) /**< PLLI2SSRC is I2S_CKIN. */
#define STM32_PLLI2SQ_MASK (15 << 24) /**< PLLI2SQ mask. */
#define STM32_PLLI2SR_MASK (7 << 28) /**< PLLI2SR mask. */
/** @} */
@ -484,9 +485,13 @@
* @name RCC_DCKCFGR register bits definitions
* @{
*/
#if !defined(STM32F413xx) || defined(_DOXYGEN__)
#define STM32_PLLI2SDIVQ_MASK (31 << 0) /**< PLLI2SDIVQ mask. */
#define STM32_PLLSAIDIVQ_MASK (31 << 8) /**< PLLSAIDIVQ mask. */
#else
#define STM32_PLLI2SDIVR_MASK (31 << 0)
#define STM32_PLLSAIDIVR_MASK (31 << 8)
#endif
#define STM32_PLLSAIDIVR_MASK (3 << 16) /**< PLLSAIDIVR mask. */
#define STM32_PLLSAIDIVR_DIV2 (0 << 16) /**< LCD_CLK is R divided by 2. */
@ -760,12 +765,31 @@
#endif /* !defined(STM32F4XX) */
/**
* @brief I2S clock source.
*/
* @brief I2S clock source (post-PLL).
* @note Not all devices have this setting, it is alternative to
* @p STM32_PLLI2SSRC.
*/
#if !defined(STM32_I2SSRC) || defined(__DOXYGEN__)
#define STM32_I2SSRC STM32_I2SSRC_CKIN
#endif
/**
* @brief I2S clock source (pre-PLL).
* @note Not all devices have this setting, it is alternative to
* @p STM32_I2SSRC.
*/
#if !defined(STM32_PLLI2SSRC) || defined(__DOXYGEN__)
#define STM32_PLLI2SSRC STM32_PLLI2SSRC_CKIN
#endif
/**
* @brief I2S external clock value, zero if not present.
* @note Not all devices have this setting.
*/
#if !defined(STM32_I2SCKIN_VALUE) || defined(__DOXYGEN__)
#define STM32_I2SCKIN_VALUE 0
#endif
/**
* @brief PLLI2SN multiplier value.
* @note The allowed values are 192..432, except for
@ -814,10 +838,11 @@
#endif
/**
* @brief STM32_PLLI2SDIVQ divider value (SAI clock divider).
* @brief PLLI2SDIVQ divider value (SAI clock divider).
* @note The allowed values are 1..32.
*/
#if !defined(STM32_PLLI2SDIVQ) || defined(__DOXYGEN__)
#define STM32_PLLI2SDIVQ 0
#if !defined(STM32_PLLI2SDIVQ_VALUE) || defined(__DOXYGEN__)
#define STM32_PLLI2SDIVQ_VALUE 1
#endif
/**
@ -882,14 +907,16 @@
#endif
/**
* @brief PLLSAIDIVR divider value (LCD clock divider).
* @brief PLLSAIDIVQ divider value (LCD clock divider).
* @note The allowed values are 1..32.
*/
#if !defined(STM32_PLLSAIDIVQ) || defined(__DOXYGEN__)
#define STM32_PLLSAIDIVQ 0
#if !defined(STM32_PLLSAIDIVQ_VALUE) || defined(__DOXYGEN__)
#define STM32_PLLSAIDIVQ_VALUE 1
#endif
/**
* @brief SAI1SEL value (SAI1 clock source).
* @todo Add check.
*/
#if !defined(STM32_SAI1SEL) || defined(__DOXYGEN__)
#define STM32_SAI1SEL STM32_SAI1SEL_OFF
@ -897,6 +924,7 @@
/**
* @brief SAI2SEL value (SAI2 clock source).
* @todo Add check.
*/
#if !defined(STM32_SAI2SEL) || defined(__DOXYGEN__)
#define STM32_SAI2SEL STM32_SAI2SEL_OFF
@ -1405,6 +1433,17 @@
#endif /* !STM32_LSE_ENABLED */
/**
* @brief Clock frequency feeding PLLs.
*/
#if (STM32_PLLSRC == STM32_PLLSRC_HSE) || defined(__DOXYGEN__)
#define STM32_PLLSRCCLK STM32_HSECLK
#elif STM32_PLLSRC == STM32_PLLSRC_HSI
#define STM32_PLLSRCCLK STM32_HSICLK
#else
#error "invalid STM32_PLLSRC value specified"
#endif
/**
* @brief STM32_PLLM field.
*/
@ -1418,13 +1457,7 @@
/**
* @brief PLL input clock frequency.
*/
#if (STM32_PLLSRC == STM32_PLLSRC_HSE) || defined(__DOXYGEN__)
#define STM32_PLLCLKIN (STM32_HSECLK / STM32_PLLM_VALUE)
#elif STM32_PLLSRC == STM32_PLLSRC_HSI
#define STM32_PLLCLKIN (STM32_HSICLK / STM32_PLLM_VALUE)
#else
#error "invalid STM32_PLLSRC value specified"
#endif
#define STM32_PLLCLKIN (STM32_PLLSRCCLK / STM32_PLLM_VALUE)
/*
* PLLs input frequency range check.
@ -1574,7 +1607,7 @@
#endif
#define STM32_OVERDRIVE_REQUIRED FALSE
#elif defined(STM32F410xx) || defined(STM32F411xx) || \
#elif defined(STM32F410xx) || defined(STM32F411xx) || \
defined(STM32F412xx) || defined(STM32F413xx)
#if STM32_SYSCLK <= 64000000
#define STM32_VOS STM32_VOS_SCALE3
@ -1673,13 +1706,13 @@
* PLLI2S enable check.
*/
#if (STM32_HAS_RCC_PLLI2S && \
STM32_CLOCK48_REQUIRED && \
(STM32_HAS_RCC_CK48MSEL && \
STM32_RCC_CK48MSEL_USES_I2S && \
(STM32_CK48MSEL == STM32_CK48MSEL_PLLALT)) || \
(STM32_I2SSRC == STM32_I2SSRC_PLLI2S) || \
(STM32_SAI1SEL == STM32_SAI1SEL_PLLI2S) || \
(STM32_SAI2SEL == STM32_SAI2SEL_PLLI2S)) || \
(STM32_CLOCK48_REQUIRED && \
(STM32_HAS_RCC_CK48MSEL && \
STM32_RCC_CK48MSEL_USES_I2S && \
(STM32_CK48MSEL == STM32_CK48MSEL_PLLALT)) || \
(STM32_I2SSRC == STM32_I2SSRC_PLLI2S) || \
(STM32_SAI1SEL == STM32_SAI1SEL_PLLI2S) || \
(STM32_SAI2SEL == STM32_SAI2SEL_PLLI2S))) || \
defined(__DOXYGEN__)
/**
@ -1703,21 +1736,12 @@
/**
* @brief STM32_PLLI2SN field.
*/
#if defined(STM32F446xx) || defined(STM32F413xx) || defined(__DOXYGEN__)
#if ((STM32_PLLI2SN_VALUE >= 50) && (STM32_PLLI2SN_VALUE <= 432)) || \
#if ((STM32_PLLI2SN_VALUE >= 50) && (STM32_PLLI2SN_VALUE <= 432)) || \
defined(__DOXYGEN__)
#define STM32_PLLI2SN (STM32_PLLI2SN_VALUE << 6)
#else
#error "invalid STM32_PLLI2SN_VALUE value specified"
#endif
#else /* !(defined(STM32F446xx) || defined(STM32F413xx)) */
#if ((STM32_PLLI2SN_VALUE >= 192) && (STM32_PLLI2SN_VALUE <= 432)) || \
defined(__DOXYGEN__)
#define STM32_PLLI2SN (STM32_PLLI2SN_VALUE << 6)
#else
#error "invalid STM32_PLLI2SN_VALUE value specified"
#endif
#endif /* !(defined(STM32F446xx) || defined(STM32F413xx)) */
/**
* @brief STM32_PLLI2SP field.
@ -1744,6 +1768,16 @@
#error "invalid STM32_PLLI2SQ_VALUE value specified"
#endif
/**
* @brief STM32_PLLI2SDIVQ field.
*/
#if ((STM32_PLLI2SDIVQ_VALUE >= 1) && (STM32_PLLI2SDIVQ_VALUE <= 32)) || \
defined(__DOXYGEN__)
#define STM32_PLLI2SDIVQ ((STM32_PLLI2SQ_VALUE - 1) << 0)
#else
#error "invalid STM32_PLLI2SDIVQ_VALUE value specified"
#endif
/**
* @brief STM32_PLLI2SR field.
*/
@ -1757,23 +1791,17 @@
/**
* @brief PLLI2S input clock frequency.
*/
#if defined(STM32F446xx) || defined(STM32F413xx)
#if (STM32_PLLSRC == STM32_PLLSRC_HSE) || defined(__DOXYGEN__)
#define STM32_PLLI2SCLKIN (STM32_HSECLK / STM32_PLLI2SM_VALUE)
#elif STM32_PLLSRC == STM32_PLLSRC_HSI
#define STM32_PLLI2SCLKIN (STM32_HSICLK / STM32_PLLI2SM_VALUE)
#if STM32_HAS_RCC_I2SPLLSRC || defined(__DOXYGEN__)
#if (STM32_PLLI2SSRC == STM32_PLLI2SSRC_PLLSRC) || defined(__DOXYGEN__)
#define STM32_PLLI2SCLKIN (STM32_PLLSRCCLK / STM32_PLLI2SM_VALUE)
#elif STM32_PLLI2SSRC == STM32_PLLI2SSRC_I2SCKIN
#define STM32_PLLI2SCLKIN (STM32_I2SCKIN_VALUE / STM32_PLLI2SM_VALUE)
#else
#error "invalid STM32_PLLSRC value specified"
#error "invalid STM32_PLLI2SSRC value specified"
#endif
#else /* !(defined(STM32F446xx) || defined(STM32F413xx)) */
#if (STM32_PLLSRC == STM32_PLLSRC_HSE) || defined(__DOXYGEN__)
#define STM32_PLLI2SCLKIN (STM32_HSECLK / STM32_PLLM_VALUE)
#elif STM32_PLLSRC == STM32_PLLSRC_HSI
#define STM32_PLLI2SCLKIN (STM32_HSICLK / STM32_PLLM_VALUE)
#else
#error "invalid STM32_PLLSRC value specified"
#define STM32_PLLI2SCLKIN (STM32_PLLSRCCLK / STM32_PLLM_VALUE)
#endif
#endif /* !(defined(STM32F446xx) || defined(STM32F413xx)) */
/**
* @brief PLLI2S VCO frequency.
@ -1807,13 +1835,14 @@
* PLLSAI enable check.
*/
#if (STM32_HAS_RCC_PLLSAI && \
STM32_CLOCK48_REQUIRED && \
(STM32_HAS_RCC_CK48MSEL && \
!STM32_RCC_CK48MSEL_USES_I2S && \
(STM32_CK48MSEL == STM32_CK48MSEL_PLLALT)) || \
(STM32_I2SSRC == STM32_I2SSRC_PLLI2S) || \
(STM32_SAI1SEL == STM32_SAI1SEL_PLLSAI) || \
(STM32_SAI2SEL == STM32_SAI2SEL_PLLSAI)) || \
(STM32_CLOCK48_REQUIRED && \
(STM32_HAS_RCC_CK48MSEL && \
!STM32_RCC_CK48MSEL_USES_I2S && \
(STM32_CK48MSEL == STM32_CK48MSEL_PLLALT)) || \
(STM32_I2SSRC == STM32_I2SSRC_PLLI2S) || \
(STM32_SAI1SEL == STM32_SAI1SEL_PLLSAI) || \
(STM32_SAI2SEL == STM32_SAI2SEL_PLLSAI))) || \
(STM32_PLLSAIDIVR != STM32_PLLSAIDIVR_OFF) || \
defined(__DOXYGEN__)
/**
* @brief PLLSAI activation flag.
@ -1826,7 +1855,7 @@
/**
* @brief STM32_PLLSAIM field.
*/
#if ((STM32_PLLSAIM_VALUE >= 2) && (STM32_PLLSAIM_VALUE <= 63)) || \
#if ((STM32_PLLSAIM_VALUE >= 2) && (STM32_PLLSAIM_VALUE <= 63)) || \
defined(__DOXYGEN__)
#define STM32_PLLSAIM (STM32_PLLSAIM_VALUE << 0)
#else
@ -1853,6 +1882,16 @@
#error "invalid STM32_PLLSAIQ_VALUE value specified"
#endif
/**
* @brief STM32_PLLSAIDIVQ_VALUE field.
*/
#if ((STM32_PLLSAIDIVQ_VALUE >= 1) && (STM32_PLLSAIDIVQ_VALUE <= 32)) || \
defined(__DOXYGEN__)
#define STM32_PLLSAIDIVQ ((STM32_PLLSAIDIVQ_VALUE - 1) << 8)
#else
#error "invalid STM32_PLLSAIDIVQ_VALUE value specified"
#endif
/**
* @brief STM32_PLLSAIR field.
*/

2249
os/hal/ports/STM32/STM32F4xx/hal_lld_type1.h Normal file
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File diff suppressed because it is too large Load Diff

2249
os/hal/ports/STM32/STM32F4xx/hal_lld_type2.h Normal file
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File diff suppressed because it is too large Load Diff

18
os/hal/ports/STM32/STM32F4xx/stm32_registry.h
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@ -92,6 +92,8 @@
/* Clock tree attributes.*/
#define STM32_HAS_RCC_PLLSAI TRUE
#define STM32_HAS_RCC_PLLI2S TRUE
#define STM32_HAS_RCC_DCKCFGR TRU§E
#define STM32_HAS_RCC_DCKCFGR2 FALSE
#define STM32_HAS_RCC_I2SSRC TRUE
#define STM32_HAS_RCC_I2SPLLSRC FALSE
#define STM32_HAS_RCC_CK48MSEL TRUE
@ -471,6 +473,8 @@
/* Clock tree attributes.*/
#define STM32_HAS_RCC_PLLSAI TRUE
#define STM32_HAS_RCC_PLLI2S TRUE
#define STM32_HAS_RCC_DCKCFGR TRUE
#define STM32_HAS_RCC_DCKCFGR2 TRUE
#define STM32_HAS_RCC_I2SSRC FALSE
#define STM32_HAS_RCC_I2SPLLSRC FALSE
#define STM32_HAS_RCC_CK48MSEL TRUE
@ -825,6 +829,8 @@
/* Clock tree attributes.*/
#define STM32_HAS_RCC_PLLSAI TRUE
#define STM32_HAS_RCC_PLLI2S TRUE
#define STM32_HAS_RCC_DCKCFGR TRUE
#define STM32_HAS_RCC_DCKCFGR2 FALSE
#define STM32_HAS_RCC_CK48MSEL_I2S FALSE
#define STM32_HAS_RCC_CK48MSEL_SAI FALSE
#define STM32_HAS_RCC_I2SSRC TRUE
@ -1202,6 +1208,8 @@
/* Clock tree attributes.*/
#define STM32_HAS_RCC_PLLSAI FALSE
#define STM32_HAS_RCC_PLLI2S TRUE
#define STM32_HAS_RCC_DCKCFGR TRUE
#define STM32_HAS_RCC_DCKCFGR2 TRUE
#define STM32_HAS_RCC_I2SSRC FALSE
#define STM32_HAS_RCC_I2SPLLSRC TRUE
#define STM32_HAS_RCC_CK48MSEL TRUE
@ -1583,6 +1591,8 @@
/* Clock tree attributes.*/
#define STM32_HAS_RCC_PLLSAI FALSE
#define STM32_HAS_RCC_PLLI2S TRUE
#define STM32_HAS_RCC_DCKCFGR TRUE
#define STM32_HAS_RCC_DCKCFGR2 TRUE
#define STM32_HAS_RCC_I2SSRC FALSE
#define STM32_HAS_RCC_I2SPLLSRC TRUE
#define STM32_HAS_RCC_CK48MSEL TRUE
@ -1915,6 +1925,8 @@
/* Clock tree attributes.*/
#define STM32_HAS_RCC_PLLSAI FALSE
#define STM32_HAS_RCC_PLLI2S TRUE
#define STM32_HAS_RCC_DCKCFGR TRUE
#define STM32_HAS_RCC_DCKCFGR2 FALSE
#define STM32_HAS_RCC_I2SSRC TRUE
#define STM32_HAS_RCC_I2SPLLSRC FALSE
#define STM32_HAS_RCC_CK48MSEL FALSE
@ -2221,6 +2233,8 @@
/* Clock tree attributes.*/
#define STM32_HAS_RCC_PLLSAI FALSE
#define STM32_HAS_RCC_PLLI2S FALSE
#define STM32_HAS_RCC_DCKCFGR TRUE
#define STM32_HAS_RCC_DCKCFGR2 TRUE
#define STM32_HAS_RCC_CK48MSEL_I2S FALSE
#define STM32_HAS_RCC_CK48MSEL_SAI FALSE
#define STM32_HAS_RCC_I2SSRC FALSE
@ -2499,6 +2513,8 @@
/* Clock tree attributes.*/
#define STM32_HAS_RCC_PLLSAI FALSE
#define STM32_HAS_RCC_PLLI2S TRUE
#define STM32_HAS_RCC_DCKCFGR FALSE
#define STM32_HAS_RCC_DCKCFGR2 FALSE
#define STM32_HAS_RCC_CK48MSEL_I2S FALSE
#define STM32_HAS_RCC_CK48MSEL_SAI FALSE
#define STM32_HAS_RCC_I2SSRC TRUE
@ -2852,6 +2868,8 @@
/* Clock tree attributes.*/
#define STM32_HAS_RCC_PLLSAI FALSE
#define STM32_HAS_RCC_PLLI2S FALSE
#define STM32_HAS_RCC_DCKCFGR FALSE
#define STM32_HAS_RCC_DCKCFGR2 FALSE
#define STM32_HAS_RCC_I2SSRC FALSE
#define STM32_HAS_RCC_I2SPLLSRC FALSE
#define STM32_HAS_RCC_CK48MSEL FALSE