git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1811 35acf78f-673a-0410-8e92-d51de3d6d3f4
This commit is contained in:
gdisirio
parent
e475309b5c
commit
cb53a3d67a
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@ -28,17 +28,32 @@
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#ifndef _CHCORE_H_
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#define _CHCORE_H_
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/*
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* Port-related configuration parameters.
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/*===========================================================================*/
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/* Port constants. */
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/*===========================================================================*/
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/**
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* @brief Port implementing a exception mode context switching.
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* @details This macro can be used to differentiate this port from the other
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* Cortex-Mx port which defines @p CORTEX_PORT_MODE_EXOSWITCH.
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*/
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#define CORTEX_PORT_MODE_ENDOSWITCH
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/*===========================================================================*/
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/* Port configurable parameters. */
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/*===========================================================================*/
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/**
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* @brief Enables the use of the WFI ins.
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*/
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#ifndef ENABLE_WFI_IDLE
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#define ENABLE_WFI_IDLE 0
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#ifndef CORTEX_ENABLE_WFI_IDLE
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#define CORTEX_ENABLE_WFI_IDLE FALSE
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#endif
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/*===========================================================================*/
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/* Port exported info. */
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/*===========================================================================*/
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/**
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* @brief Name of the implemented architecture.
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*/
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@ -309,7 +324,7 @@ struct context {
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* modes.
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* @note Implemented as an inlined @p WFI instruction.
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*/
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#if ENABLE_WFI_IDLE || defined(__DOXYGEN__)
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#if CORTEX_ENABLE_WFI_IDLE || defined(__DOXYGEN__)
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#define port_wait_for_interrupt() { \
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asm volatile ("wfi"); \
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}
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@ -31,13 +31,6 @@
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#ifndef _CMPARAMS_H_
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#define _CMPARAMS_H_
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/*===========================================================================*/
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/* Constants parameters. */
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/*===========================================================================*/
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#define CORTEX_M0 0 /**< @brief Cortex-M0 variant. */
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#define CORTEX_M3 3 /**< @brief Cortex-M3 variant. */
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/**
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* @brief Cortex core model.
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*/
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@ -55,27 +48,9 @@
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/**
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* @brief Number of bits in priority masks.
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* @details The available number of priority levels is equal to
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* (1 << @p CORTEX_PRIORITY_BITS).
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*/
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#define CORTEX_PRIORITY_BITS 2
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/**
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* @brief Priority to priority mask conversion macro.
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*/
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#define CORTEX_PRIORITY(n) ((n) << (8 - CORTEX_PRIORITY_BITS))
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/*===========================================================================*/
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/* Configurable parameters. */
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/*===========================================================================*/
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/**
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* @brief SYSTICK handler priority.
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*/
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#ifndef CORTEX_PRIORITY_SYSTICK
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#define CORTEX_PRIORITY_SYSTICK CORTEX_PRIORITY(2)
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#endif
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#endif /* _CMPARAMS_H_ */
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/** @} */
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@ -1,4 +1,4 @@
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# List of the ChibiOS/RT Cortex-M0 LPC11xx port files.
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# List of the ChibiOS/RT Cortex-M0 LPC111x port files.
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PORTSRC = ${CHIBIOS}/os/ports/GCC/ARMCMx/chcore.c \
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${CHIBIOS}/os/ports/GCC/ARMCMx/nvic.c
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# ${CHIBIOS}/os/ports/GCC/ARMCMx/cmsis/core_cm0.c
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@ -0,0 +1,56 @@
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/*
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ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio.
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This file is part of ChibiOS/RT.
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ChibiOS/RT is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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ChibiOS/RT is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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/**
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* @file ARMCMx/STM32F10x/cmparams.h
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* @brief ARM Cortex-M3 STM32F10x specific parameters.
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*
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* @defgroup ARMCMx_STM32F10x STM32F10x specific parameters
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* @ingroup ARMCMx
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* @details This file contains the Cortex-M3 specific parameters for the
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* STM32F10x platform.
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* @{
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*/
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#ifndef _CMPARAMS_H_
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#define _CMPARAMS_H_
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/**
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* @brief Cortex core model.
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*/
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#define CORTEX_MODEL CORTEX_M3
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/**
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* @brief Systick unit presence.
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*/
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#define CORTEX_HAS_ST TRUE
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/**
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* @brief Memory Protection unit presence.
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*/
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#define CORTEX_HAS_MPU FALSE
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/**
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* @brief Number of bits in priority masks.
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*/
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#define CORTEX_PRIORITY_BITS 4
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#endif /* _CMPARAMS_H_ */
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/** @} */
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@ -0,0 +1,10 @@
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# List of the ChibiOS/RT Cortex-M3 STM32 port files.
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PORTSRC = ${CHIBIOS}/os/ports/GCC/ARMCMx/chcore.c \
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${CHIBIOS}/os/ports/GCC/ARMCMx/nvic.c \
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${CHIBIOS}/os/ports/GCC/ARMCMx/cmsis/core_cm3.c
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PORTASM = ${CHIBIOS}/os/ports/GCC/ARMCMx/crt0.s
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PORTINC = ${CHIBIOS}/os/ports/GCC/ARMCMx \
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${CHIBIOS}/os/ports/GCC/ARMCMx/STM32F10x \
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${CHIBIOS}/os/ports/GCC/ARMCMx/cmsis
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@ -0,0 +1,363 @@
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/*
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ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio.
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This file is part of ChibiOS/RT.
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ChibiOS/RT is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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ChibiOS/RT is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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.syntax unified
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.thumb
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.section vectors
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_vectors:
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.word __ram_end__
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.word ResetHandler
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.word NMIVector
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.word HardFaultVector
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.word MemManageVector
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.word BusFaultVector
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.word UsageFaultVector
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.word Vector1C
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.word Vector20
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.word Vector24
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.word Vector28
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.word SVCallVector
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.word DebugMonitorVector
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.word Vector34
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.word PendSVVector
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.word SysTickVector
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.word Vector40
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.word Vector44
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.word Vector48
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.word Vector4C
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.word Vector50
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.word Vector54
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.word Vector58
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.word Vector5C
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.word Vector60
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.word Vector64
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.word Vector68
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.word Vector6C
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.word Vector70
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.word Vector74
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.word Vector78
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.word Vector7C
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.word Vector80
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.word Vector84
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.word Vector88
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.word Vector8C
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.word Vector90
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.word Vector94
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.word Vector98
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.word Vector9C
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.word VectorA0
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.word VectorA4
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.word VectorA8
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.word VectorAC
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.word VectorB0
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.word VectorB4
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.word VectorB8
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.word VectorBC
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.word VectorC0
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.word VectorC4
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.word VectorC8
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.word VectorCC
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.word VectorD0
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.word VectorD4
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.word VectorD8
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.word VectorDC
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.word VectorE0
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.word VectorE4
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.word VectorE8
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#if defined(STM32F10X_HD) || defined(STM32F10X_CL)
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.word VectorEC
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.word VectorF0
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.word VectorF4
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.word VectorF8
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.word VectorFC
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.word Vector100
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.word Vector104
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.word Vector108
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.word Vector10C
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.word Vector110
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.word Vector114
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.word Vector118
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.word Vector11C
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.word Vector120
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.word Vector124
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.word Vector128
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.word Vector12C
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#endif
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#if defined(STM32F10X_CL)
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.word Vector130
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.word Vector134
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.word Vector138
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.word Vector13C
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.word Vector140
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.word Vector144
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.word Vector148
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.word Vector14C
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#endif
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.weak NMIVector
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NMIVector:
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.weak HardFaultVector
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HardFaultVector:
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.weak MemManageVector
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MemManageVector:
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.weak BusFaultVector
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BusFaultVector:
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.weak UsageFaultVector
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UsageFaultVector:
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.weak Vector1C
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Vector1C:
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.weak Vector20
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Vector20:
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.weak Vector24
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Vector24:
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.weak Vector28
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Vector28:
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.weak SVCallVector
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SVCallVector:
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.weak DebugMonitorVector
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DebugMonitorVector:
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.weak Vector34
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Vector34:
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.weak PendSVVector
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PendSVVector:
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.weak SysTickVector
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SysTickVector:
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.weak Vector40
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Vector40:
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.weak Vector44
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Vector44:
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.weak Vector48
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Vector48:
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.weak Vector4C
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Vector4C:
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.weak Vector50
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Vector50:
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.weak Vector54
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Vector54:
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.weak Vector58
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Vector58:
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.weak Vector5C
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Vector5C:
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.weak Vector60
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Vector60:
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.weak Vector64
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Vector64:
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.weak Vector68
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Vector68:
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.weak Vector6C
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Vector6C:
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.weak Vector70
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Vector70:
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.weak Vector74
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Vector74:
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.weak Vector78
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Vector78:
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.weak Vector7C
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Vector7C:
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.weak Vector80
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Vector80:
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.weak Vector84
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Vector84:
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.weak Vector88
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Vector88:
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.weak Vector8C
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Vector8C:
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.weak Vector90
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Vector90:
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.weak Vector94
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Vector94:
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.weak Vector98
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Vector98:
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.weak Vector9C
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Vector9C:
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.weak VectorA0
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VectorA0:
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.weak VectorA4
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VectorA4:
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.weak VectorA8
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VectorA8:
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.weak VectorAC
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VectorAC:
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.weak VectorB0
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VectorB0:
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.weak VectorB4
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VectorB4:
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.weak VectorB8
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VectorB8:
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.weak VectorBC
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VectorBC:
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.weak VectorC0
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VectorC0:
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.weak VectorC4
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VectorC4:
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|
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.weak VectorC8
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VectorC8:
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.weak VectorCC
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VectorCC:
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.weak VectorD0
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VectorD0:
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.weak VectorD4
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VectorD4:
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|
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.weak VectorD8
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||||
VectorD8:
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|
||||
.weak VectorDC
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||||
VectorDC:
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||||
|
||||
.weak VectorE0
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VectorE0:
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||||
|
||||
.weak VectorE4
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||||
VectorE4:
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||||
|
||||
.weak VectorE8
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||||
VectorE8:
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||||
|
||||
#if defined(STM32F10X_HD) || defined(STM32F10X_CL)
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.weak VectorEC
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||||
VectorEC:
|
||||
|
||||
.weak VectorF0
|
||||
VectorF0:
|
||||
|
||||
.weak VectorF4
|
||||
VectorF4:
|
||||
|
||||
.weak VectorF8
|
||||
VectorF8:
|
||||
|
||||
.weak VectorFC
|
||||
VectorFC:
|
||||
|
||||
.weak Vector100
|
||||
Vector100:
|
||||
|
||||
.weak Vector104
|
||||
Vector104:
|
||||
|
||||
.weak Vector108
|
||||
Vector108:
|
||||
|
||||
.weak Vector10C
|
||||
Vector10C:
|
||||
|
||||
.weak Vector110
|
||||
Vector110:
|
||||
|
||||
.weak Vector114
|
||||
Vector114:
|
||||
|
||||
.weak Vector118
|
||||
Vector118:
|
||||
|
||||
.weak Vector11C
|
||||
Vector11C:
|
||||
|
||||
.weak Vector120
|
||||
Vector120:
|
||||
|
||||
.weak Vector124
|
||||
Vector124:
|
||||
|
||||
.weak Vector128
|
||||
Vector128:
|
||||
|
||||
.weak Vector12C
|
||||
Vector12C:
|
||||
#endif
|
||||
#if defined(STM32F10X_CL)
|
||||
.weak Vector130
|
||||
Vector130:
|
||||
|
||||
.weak Vector134
|
||||
Vector134:
|
||||
|
||||
.weak Vector138
|
||||
Vector138:
|
||||
|
||||
.weak Vector13C
|
||||
Vector13C:
|
||||
|
||||
.weak Vector140
|
||||
Vector140:
|
||||
|
||||
.weak Vector144
|
||||
Vector144:
|
||||
|
||||
.weak Vector148
|
||||
Vector148:
|
||||
|
||||
.weak Vector14C
|
||||
Vector14C:
|
||||
#endif
|
||||
|
||||
here: b here
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|
|
@ -28,43 +28,141 @@
|
|||
#ifndef _CHCORE_H_
|
||||
#define _CHCORE_H_
|
||||
|
||||
/*
|
||||
* Port-related configuration parameters.
|
||||
*/
|
||||
/*===========================================================================*/
|
||||
/* Port constants. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @brief Enables the use of the WFI ins.
|
||||
* @brief Port implementing a process mode context switching.
|
||||
* @details This macro can be used to differentiate this port from the other
|
||||
* Cortex-Mx port which defines @p CORTEX_PORT_MODE_ENDOSWITCH.
|
||||
*/
|
||||
#ifndef ENABLE_WFI_IDLE
|
||||
#define ENABLE_WFI_IDLE 0
|
||||
#endif
|
||||
#define CORTEX_PORT_MODE_EXOSWITCH
|
||||
|
||||
/**
|
||||
* @brief Name of the implemented architecture.
|
||||
*/
|
||||
#define CH_ARCHITECTURE_NAME "ARM"
|
||||
#define CORTEX_M0 0 /**< @brief Cortex-M0 variant. */
|
||||
#define CORTEX_M1 1 /**< @brief Cortex-M1 variant. */
|
||||
#define CORTEX_M3 3 /**< @brief Cortex-M3 variant. */
|
||||
#define CORTEX_M4 4 /**< @brief Cortex-M4 variant. */
|
||||
|
||||
/* Inclusion of the Cortex-Mx implementation specific parameters.*/
|
||||
#include "cmparams.h"
|
||||
|
||||
/* Generating model-dependent info.*/
|
||||
#if (CORTEX_MODEL == CORTEX_M3) || defined(__DOXYGEN__)
|
||||
/* Cortex model check, only M0 and M3 right now.*/
|
||||
#if (CORTEX_MODEL == CORTEX_M0) || (CORTEX_MODEL == CORTEX_M3)
|
||||
#else
|
||||
#error "unknown or unsupported Cortex-M model"
|
||||
#endif
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Port derived parameters. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @brief Priority masking support.
|
||||
*/
|
||||
#if (CORTEX_MODEL == CORTEX_M3) || (CORTEX_MODEL == CORTEX_M4) || \
|
||||
defined(__DOXYGEN__)
|
||||
#define CORTEX_SUPPORT_BASEPRI TRUE
|
||||
#else
|
||||
#define CORTEX_SUPPORT_BASEPRI FALSE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Total priority levels.
|
||||
*/
|
||||
#define CORTEX_PRIORITY_LEVELS (1 << CORTEX_PRIORITY_BITS)
|
||||
|
||||
/**
|
||||
* @brief Minimum priority level.
|
||||
* @details This minimum priority level is calculated from the number of
|
||||
* priority bits supported by the specific Cortex-Mx implementation.
|
||||
*/
|
||||
#define CORTEX_MINIMUM_PRIORITY (CORTEX_PRIORITY_LEVELS - 1)
|
||||
|
||||
/**
|
||||
* @brief Maximum priority level.
|
||||
* @details The maximum allowed priority level is always zero.
|
||||
*/
|
||||
#define CORTEX_MAXIMUM_PRIORITY 0
|
||||
|
||||
#if
|
||||
/*===========================================================================*/
|
||||
/* Port macros. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @brief Priority level verification macro.
|
||||
*/
|
||||
#define CORTEX_IS_VALID_PRIORITY(n) \
|
||||
(((n) >= 0) && ((n) < CORTEX_PRIORITY_LEVELS))
|
||||
|
||||
/**
|
||||
* @brief Priority level to priority mask conversion macro.
|
||||
*/
|
||||
#define CORTEX_PRIORITY_MASK(n) ((n) << (8 - CORTEX_PRIORITY_BITS))
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Port configurable parameters. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @brief Enables the use of the WFI instruction in the idle thread loop.
|
||||
*/
|
||||
#ifndef CORTEX_ENABLE_WFI_IDLE
|
||||
#define CORTEX_ENABLE_WFI_IDLE FALSE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief SYSTICK handler priority.
|
||||
* @note The default is calculated as the priority level in the middle
|
||||
* of the priority range.
|
||||
*/
|
||||
#ifndef CORTEX_PRIORITY_SYSTICK
|
||||
#define CORTEX_PRIORITY_SYSTICK (CORTEX_PRIORITY_LEVELS >> 1)
|
||||
#else
|
||||
/* If it is externally redefined then better perform a validity check on it.*/
|
||||
#if !CORTEX_IS_VALID_PRIORITY(CORTEX_PRIORITY_SYSTICK)
|
||||
#error "invalid priority level specified for CORTEX_PRIORITY_SYSTICK"
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Port exported info. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @brief Name of the implemented architecture.
|
||||
*/
|
||||
#define CH_ARCHITECTURE_NAME "ARM"
|
||||
|
||||
#if defined(__DOXYGEN__)
|
||||
/**
|
||||
* @brief Macro defining the ARM Cortex-M3 architecture.
|
||||
*/
|
||||
#define CH_ARCHITECTURE_ARMCM3
|
||||
#define CH_ARCHITECTURE_ARMCMx
|
||||
|
||||
/**
|
||||
* @brief Name of the architecture variant (optional).
|
||||
*/
|
||||
#define CH_CORE_VARIANT_NAME "Cortex-Mx"
|
||||
#elif CORTEX_MODEL == CORTEX_M4
|
||||
#define CH_ARCHITECTURE_ARMCM4
|
||||
#define CH_CORE_VARIANT_NAME "Cortex-M4"
|
||||
#elif CORTEX_MODEL == CORTEX_M3
|
||||
#define CH_ARCHITECTURE_ARMCM3
|
||||
#define CH_CORE_VARIANT_NAME "Cortex-M3"
|
||||
#elif CORTEX_MODEL == CORTEX_M1
|
||||
#define CH_ARCHITECTURE_ARMCM1
|
||||
#define CH_CORE_VARIANT_NAME "Cortex-M1"
|
||||
#elif CORTEX_MODEL == CORTEX_M0
|
||||
#define CH_ARCHITECTURE_ARMCM0
|
||||
#define CH_CORE_VARIANT_NAME "Cortex-M0"
|
||||
#else
|
||||
#error "unknown or unsupported Cortex-M model"
|
||||
#endif
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Port implementation part. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @brief 32 bits stack and memory alignment enforcement.
|
||||
*/
|
||||
|
|
@ -302,7 +400,7 @@ struct context {
|
|||
* modes.
|
||||
* @note Implemented as an inlined @p WFI instruction.
|
||||
*/
|
||||
#if ENABLE_WFI_IDLE || defined(__DOXYGEN__)
|
||||
#if CORTEX_ENABLE_WFI_IDLE || defined(__DOXYGEN__)
|
||||
#define port_wait_for_interrupt() asm volatile ("wfi")
|
||||
#else
|
||||
#define port_wait_for_interrupt()
|
||||
|
|
|
|||
Loading…
Reference in New Issue