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Added eMIOS global prescaler setting to SPC563Mxx and SPC564Axx devices HAL. 

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@5867 35acf78f-673a-0410-8e92-d51de3d6d3f4
This commit is contained in:
gdisirio 2013-06-22 07:51:40 +00:00
parent 83da11cab0
commit cb5dc82791
11 changed files with 45 additions and 0 deletions
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1
demos/PPC-SPC563M-GCC/mcuconf.h
View File

@ -45,6 +45,7 @@
BIUCR_IPFEN | \
BIUCR_PFLIM_ON_MISS | \
BIUCR_BFEN)
#define SPC5_EMIOS_GPRE_VALUE 20
/*
* EDMA driver settings.

1
demos/PPC-SPC564A-GCC/mcuconf.h
View File

@ -45,6 +45,7 @@
BIUCR_IPFEN | \
BIUCR_PFLIM_ON_MISS | \
BIUCR_BFEN)
#define SPC5_EMIOS_GPRE_VALUE 20
/*
* EDMA driver settings.

3
os/hal/platforms/SPC563Mxx/hal_lld.c
View File

@ -95,6 +95,9 @@ void hal_lld_init(void) {
INTC.CPR.R = 0;
INTC.IACKR.R = (uint32_t)_vectors;
/* eMIOS initialization.*/
EMIOS.MCR.R = (1U << 26) | SPC5_EMIOS_GPRE; /* GPREN and GPRE. */
/* EDMA initialization.*/
edmaInit();
}

16
os/hal/platforms/SPC563Mxx/hal_lld.h
View File

@ -169,6 +169,13 @@
BIUCR_BFEN)
#endif
/**
* @brief eMIOS global prescaler value.
*/
#if !defined(SPC5_EMIOS_GPRE_VALUE) || defined(__DOXYGEN__)
#define SPC5_EMIOS_GPRE_VALUE 20
#endif
/*===========================================================================*/
/* Derived constants and error checks. */
/*===========================================================================*/
@ -193,6 +200,10 @@
#error "invalid SPC5_CLK_RFD value specified"
#endif
#if (SPC5_EMIOS_GPRE_VALUE < 1) || (SPC5_EMIOS_GPRE_VALUE > 256)
#error "invalid SPC5_EMIOS_GPRE_VALUE value specified"
#endif
/**
* @brief PLL input divider.
*/
@ -239,6 +250,11 @@
#define SPC5_FLASH_WS (BIUCR_APC_3 | BIUCR_RWSC_3 | BIUCR_WWSC_1)
#endif
/**
* @brief eMIOS global prescaler setting.
*/
#define SPC5_EMIOS_GPRE (SPC5_EMIOS_GPRE_VALUE << 8)
/*===========================================================================*/
/* Driver data structures and types. */
/*===========================================================================*/

3
os/hal/platforms/SPC564Axx/hal_lld.c
View File

@ -107,6 +107,9 @@ void hal_lld_init(void) {
INTC.CPR.R = 0;
INTC.IACKR.R = (uint32_t)_vectors;
/* eMIOS initialization.*/
EMIOS.MCR.R = (1U << 26) | SPC5_EMIOS_GPRE; /* GPREN and GPRE. */
/* EDMA initialization.*/
edmaInit();
}

16
os/hal/platforms/SPC564Axx/hal_lld.h
View File

@ -169,6 +169,13 @@
BIUCR_BFEN)
#endif
/**
* @brief eMIOS global prescaler value.
*/
#if !defined(SPC5_EMIOS_GPRE_VALUE) || defined(__DOXYGEN__)
#define SPC5_EMIOS_GPRE_VALUE 20
#endif
/*===========================================================================*/
/* Derived constants and error checks. */
/*===========================================================================*/
@ -193,6 +200,10 @@
#error "invalid SPC5_CLK_RFD value specified"
#endif
#if (SPC5_EMIOS_GPRE_VALUE < 1) || (SPC5_EMIOS_GPRE_VALUE > 256)
#error "invalid SPC5_EMIOS_GPRE_VALUE value specified"
#endif
/**
* @brief PLL input divider.
*/
@ -250,6 +261,11 @@
#define SPC5_RAM_WS 0x40000000
#endif
/**
* @brief eMIOS global prescaler setting.
*/
#define SPC5_EMIOS_GPRE (SPC5_EMIOS_GPRE_VALUE << 8)
/*===========================================================================*/
/* Driver data structures and types. */
/*===========================================================================*/

1
testhal/SPC563Mxx/ADC/mcuconf.h
View File

@ -45,6 +45,7 @@
BIUCR_IPFEN | \
BIUCR_PFLIM_ON_MISS | \
BIUCR_BFEN)
#define SPC5_EMIOS_GPRE_VALUE 20
/*
* EDMA driver settings.

1
testhal/SPC563Mxx/ICU-PWM/mcuconf.h
View File

@ -43,6 +43,7 @@
BIUCR_IPFEN | \
BIUCR_PFLIM_ON_MISS | \
BIUCR_BFEN)
#define SPC5_EMIOS_GPRE_VALUE 20
/*
* ADC driver settings.

1
testhal/SPC563Mxx/SPI/mcuconf.h
View File

@ -45,6 +45,7 @@
BIUCR_IPFEN | \
BIUCR_PFLIM_ON_MISS | \
BIUCR_BFEN)
#define SPC5_EMIOS_GPRE_VALUE 20
/*
* EDMA driver settings.

1
testhal/SPC564Axx/ICU-PWM/mcuconf.h
View File

@ -43,6 +43,7 @@
BIUCR_IPFEN | \
BIUCR_PFLIM_ON_MISS | \
BIUCR_BFEN)
#define SPC5_EMIOS_GPRE_VALUE 20
/*
* ADC driver settings.

1
testhal/SPC564Axx/SPI/mcuconf.h
View File

@ -45,6 +45,7 @@
BIUCR_IPFEN | \
BIUCR_PFLIM_ON_MISS | \
BIUCR_BFEN)
#define SPC5_EMIOS_GPRE_VALUE 20
/*
* EDMA driver settings.