From cc40423a944b378fc923c3aa8aa0074e750683a2 Mon Sep 17 00:00:00 2001 From: Giovanni Di Sirio Date: Sat, 5 Aug 2023 09:22:30 +0000 Subject: [PATCH] More H5 stuff. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@16362 27425a3e-05d8-49a3-a47f-9c15f0e5edd8 --- os/hal/ports/STM32/LLD/RCCv1/stm32_pll1.inc | 381 +++++++++++ os/hal/ports/STM32/LLD/RCCv1/stm32_pll2.inc | 381 +++++++++++ os/hal/ports/STM32/LLD/RCCv1/stm32_pll3.inc | 381 +++++++++++ os/hal/ports/STM32/STM32H5xx/stm32_isr.c | 125 ++-- os/hal/ports/STM32/STM32H5xx/stm32_isr.h | 304 ++++----- os/hal/ports/STM32/STM32H5xx/stm32_registry.h | 641 ++---------------- 6 files changed, 1384 insertions(+), 829 deletions(-) create mode 100644 os/hal/ports/STM32/LLD/RCCv1/stm32_pll1.inc create mode 100644 os/hal/ports/STM32/LLD/RCCv1/stm32_pll2.inc create mode 100644 os/hal/ports/STM32/LLD/RCCv1/stm32_pll3.inc diff --git a/os/hal/ports/STM32/LLD/RCCv1/stm32_pll1.inc b/os/hal/ports/STM32/LLD/RCCv1/stm32_pll1.inc new file mode 100644 index 000000000..3a3923853 --- /dev/null +++ b/os/hal/ports/STM32/LLD/RCCv1/stm32_pll1.inc @@ -0,0 +1,381 @@ +/* + ChibiOS - Copyright (C) 2006..2023 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file RCCv1/stm32_pll1.inc + * @brief Shared PLL1 handler. + * + * @addtogroup STM32_PLL1_HANDLER + * @{ + */ + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/* Checks on registry.*/ +#if !defined(STM32_RCC_HAS_PLL1) +#error "STM32_RCC_HAS_PLL1 not defined in stm32_registry.h" +#endif + +#if STM32_RCC_HAS_PLL1 && !defined(STM32_RCC_PLL1_HAS_P) +#error "STM32_RCC_PLL1_HAS_P not defined in stm32_registry.h" +#endif + +#if STM32_RCC_HAS_PLL1 && !defined(STM32_RCC_PLL1_HAS_Q) +#error "STM32_RCC_PLL1_HAS_Q not defined in stm32_registry.h" +#endif + +#if STM32_RCC_HAS_PLL1 && !defined(STM32_RCC_PLL1_HAS_R) +#error "STM32_RCC_PLL1_HAS_R not defined in stm32_registry.h" +#endif + +#if STM32_RCC_HAS_PLL1 + +/* Checks on configurations.*/ +#if !defined(STM32_PLL1SRC) +#error "STM32_PLL1SRC not defined in mcuconf.h" +#endif + +#if !defined(STM32_PLL1M_VALUE) +#error "STM32_PLL1M_VALUE not defined in mcuconf.h" +#endif + +#if !defined(STM32_PLL1N_VALUE) +#error "STM32_PLL1N_VALUE not defined in mcuconf.h" +#endif + +#if !defined(STM32_PLL1PDIV_VALUE) +#error "STM32_PLL1PDIV_VALUE not defined in mcuconf.h" +#endif + +#if STM32_RCC_PLL1_HAS_P && !defined(STM32_PLL1P_VALUE) +#error "STM32_PLL1P_VALUE not defined in mcuconf.h" +#endif + +#if STM32_RCC_PLL1_HAS_Q && !defined(STM32_PLL1Q_VALUE) +#error "STM32_PLL1Q_VALUE not defined in mcuconf.h" +#endif + +#if STM32_RCC_PLL1_HAS_R && !defined(STM32_PLL1R_VALUE) +#error "STM32_PLL1R_VALUE not defined in mcuconf.h" +#endif + +/* Check on limits.*/ +#if !defined(STM32_PLL1IN_MAX) +#error "STM32_PLL1IN_MAX not defined in hal_lld.h" +#endif + +#if !defined(STM32_PLL1IN_MIN) +#error "STM32_PLL1IN_MIN not defined in hal_lld.h" +#endif + +#if !defined(STM32_PLL1VCO_MAX) +#error "STM32_PLL1VCO_MAX not defined in hal_lld.h" +#endif + +#if !defined(STM32_PLL1VCO_MIN) +#error "STM32_PLL1VCO_MIN not defined in hal_lld.h" +#endif + +#if !defined(STM32_PLL1P_MAX) +#error "STM32_PLL1P_MAX not defined in hal_lld.h" +#endif + +#if !defined(STM32_PLL1P_MIN) +#error "STM32_PLL1P_MIN not defined in hal_lld.h" +#endif + +#if !defined(STM32_PLL1Q_MAX) +#error "STM32_PLL1Q_MAX not defined in hal_lld.h" +#endif + +#if !defined(STM32_PLL1Q_MIN) +#error "STM32_PLL1Q_MIN not defined in hal_lld.h" +#endif + +#if !defined(STM32_PLL1R_MAX) +#error "STM32_PLL1R_MAX not defined in hal_lld.h" +#endif + +#if !defined(STM32_PLL1R_MIN) +#error "STM32_PLL1R_MIN not defined in hal_lld.h" +#endif + +/* Input checks.*/ +#if !defined(STM32_ACTIVATE_PLL1) +#error "STM32_ACTIVATE_PLL1 not defined in hal_lld.h" +#endif + +#if STM32_RCC_PLL1_HAS_P && !defined(STM32_PLL1PEN) +#error "STM32_PLL1PEN not defined in hal_lld.h" +#endif + +#if STM32_RCC_PLL1_HAS_Q && !defined(STM32_PLL1QEN) +#error "STM32_PLL1QEN not defined in hal_lld.h" +#endif + +#if STM32_RCC_PLL1_HAS_R && !defined(STM32_PLL1REN) +#error "STM32_PLL1REN not defined in hal_lld.h" +#endif + +#if STM32_ACTIVATE_PLL1 && (STM32_PLL1CLKIN == 0) +#error "PLL1 activation required but no PLL1 clock selected" +#endif + +#if (STM32_PLL1CLKIN != 0) && \ + ((STM32_PLL1CLKIN < STM32_PLL1IN_MIN) || (STM32_PLL1CLKIN > STM32_PLL1IN_MAX)) +#error "STM32_PLL1CLKIN outside acceptable range (STM32_PLL1IN_MIN...STM32_PLL1IN_MAX)" +#endif + +/** + * @brief STM32_PLL1M field. + */ +#if ((STM32_PLL1M_VALUE >= 1) && (STM32_PLL1M_VALUE <= 16)) || \ + defined(__DOXYGEN__) +#define STM32_PLL1M ((STM32_PLL1M_VALUE - 1U) << RCC_PLL1CFGR_PLL1M_Pos) + +#else +#error "invalid STM32_PLL1M_VALUE value specified" +#endif + +/** + * @brief STM32_PLL1N field. + */ +#if ((STM32_PLL1N_VALUE >= 8) && (STM32_PLL1N_VALUE <= 127)) || \ + defined(__DOXYGEN__) +#define STM32_PLL1N (STM32_PLL1N_VALUE << RCC_PLL1CFGR_PLL1N_Pos) + +#else +#error "invalid STM32_PLL1N_VALUE value specified" +#endif + +/** + * @brief PLL1 VCO frequency. + */ +#define STM32_PLL1VCO (STM32_PLL1CLKIN * STM32_PLL1N_VALUE) + +/* + * PLL1 VCO frequency range check. + */ +#if STM32_ACTIVATE_PLL1 && \ + ((STM32_PLL1VCO < STM32_PLL1VCO_MIN) || (STM32_PLL1VCO > STM32_PLL1VCO_MAX)) +#error "STM32_PLL1VCO outside acceptable range (STM32_PLL1VCO_MIN...STM32_PLL1VCO_MAX)" +#endif + +/*---------------------------------------------------------------------------*/ +/* P output, if present. */ +/*---------------------------------------------------------------------------*/ +#if STM32_RCC_PLL1_HAS_P || defined(__DOXYGEN__) +/** + * @brief STM32_PLL1P field. + */ +#if (STM32_PLL1P_VALUE == 7) || defined(__DOXYGEN__) +#define STM32_PLL1P (0U << RCC_PLL1CFGR_PLL1P_Pos) + +#elif STM32_PLL1P_VALUE == 17 +#define STM32_PLL1P (1U << RCC_PLL1CFGR_PLL1P_Pos) + +#else +#error "invalid STM32_PLL1P_VALUE value specified" +#endif + +/* PDIV is not present on all devices.*/ +#if defined(RCC_PLL1CFGR_PLL1PDIV_Pos) || defined(__DOXYGEN__) +/** + * @brief STM32_PLL1PDIV field. + */ +#if (STM32_PLL1PDIV_VALUE == 0) || \ + ((STM32_PLL1PDIV_VALUE >= 2) && (STM32_PLL1PDIV_VALUE <= 31)) || \ + defined(__DOXYGEN__) +#define STM32_PLL1PDIV (STM32_PLL1PDIV_VALUE << RCC_PLL1CFGR_PLL1PDIV_Pos) +#else +#error "invalid STM32_PLL1PDIV_VALUE value specified" +#endif + +/** + * @brief PLL1 P output clock frequency. + */ +#if (STM32_PLL1PDIV_VALUE == 0) || defined(__DOXYGEN__) +#define STM32_PLL1_P_CLKOUT (STM32_PLL1VCO / STM32_PLL1P_VALUE) +#else +#define STM32_PLL1_P_CLKOUT (STM32_PLL1VCO / STM32_PLL1PDIV_VALUE) +#endif + +#else +#define STM32_PLL1_P_CLKOUT (STM32_PLL1VCO / STM32_PLL1P_VALUE) +#define STM32_PLL1PDIV 0U +#endif + +/* + * PLL1-P output frequency range check. + */ +#if STM32_ACTIVATE_PLL1 && \ + ((STM32_PLL1_P_CLKOUT < STM32_PLL1P_MIN) || (STM32_PLL1_P_CLKOUT > STM32_PLL1P_MAX)) +#error "STM32_PLL1_P_CLKOUT outside acceptable range (STM32_PLL1P_MIN...STM32_PLL1P_MAX)" +#endif + +#else /* !STM32_RCC_PLL1_HAS_P */ +#define STM32_PLL1P 0U +#define STM32_PLL1PDIV 0U +#endif /* !STM32_RCC_PLL1_HAS_P */ + +/*---------------------------------------------------------------------------*/ +/* Q output, if present. */ +/*---------------------------------------------------------------------------*/ +#if STM32_RCC_PLL1_HAS_Q || defined(__DOXYGEN__) +/** + * @brief STM32_PLL1Q field. + */ +#if (STM32_PLL1Q_VALUE == 2) || defined(__DOXYGEN__) +#define STM32_PLL1Q (0U << RCC_PLL1CFGR_PLL1Q_Pos) + +#elif STM32_PLL1Q_VALUE == 4 +#define STM32_PLL1Q (1U << RCC_PLL1CFGR_PLL1Q_Pos) + +#elif STM32_PLL1Q_VALUE == 6 +#define STM32_PLL1Q (2U << RCC_PLL1CFGR_PLL1Q_Pos) + +#elif STM32_PLL1Q_VALUE == 8 +#define STM32_PLL1Q (3U << RCC_PLL1CFGR_PLL1Q_Pos) + +#else +#error "invalid STM32_PLL1Q_VALUE value specified" +#endif + +/** + * @brief PLL1 Q output clock frequency. + */ +#define STM32_PLL1_Q_CLKOUT (STM32_PLL1VCO / STM32_PLL1Q_VALUE) + +/* + * PLL1-Q output frequency range check. + */ +#if STM32_ACTIVATE_PLL1 && \ + ((STM32_PLL1_Q_CLKOUT < STM32_PLL1Q_MIN) || (STM32_PLL1_Q_CLKOUT > STM32_PLL1Q_MAX)) +#error "STM32_PLL1_Q_CLKOUT outside acceptable range (STM32_PLL1Q_MIN...STM32_PLL1Q_MAX)" +#endif + +#else /* !STM32_RCC_PLL1_HAS_Q */ +#define STM32_PLL1Q 0U +#endif /* !STM32_RCC_PLL1_HAS_Q */ + +/*---------------------------------------------------------------------------*/ +/* R output, if present. */ +/*---------------------------------------------------------------------------*/ +#if STM32_RCC_PLL1_HAS_R || defined(__DOXYGEN__) +/** + * @brief STM32_PLL1R field. + */ +#if (STM32_PLL1R_VALUE == 2) || defined(__DOXYGEN__) +#define STM32_PLL1R (0U << RCC_PLL1CFGR_PLL1R_Pos) + +#elif STM32_PLL1R_VALUE == 4 +#define STM32_PLL1R (1U << RCC_PLL1CFGR_PLL1R_Pos) + +#elif STM32_PLL1R_VALUE == 6 +#define STM32_PLL1R (2U << RCC_PLL1CFGR_PLL1R_Pos) + +#elif STM32_PLL1R_VALUE == 8 +#define STM32_PLL1R (3U << RCC_PLL1CFGR_PLL1R_Pos) + +#else +#error "invalid STM32_PLL1R_VALUE value specified" +#endif + +/** + * @brief PLL1 R output clock frequency. + */ +#define STM32_PLL1_R_CLKOUT (STM32_PLL1VCO / STM32_PLL1R_VALUE) + +/* + * PLL1-R output frequency range check. + */ +#if STM32_ACTIVATE_PLL1 && \ + ((STM32_PLL1_R_CLKOUT < STM32_PLL1R_MIN) || (STM32_PLL1_R_CLKOUT > STM32_PLL1R_MAX)) +#error "STM32_PLL1_R_CLKOUT outside acceptable range (STM32_PLL1R_MIN...STM32_PLL1R_MAX)" +#endif + +#else /* !STM32_RCC_PLL1_HAS_R */ +#define STM32_PLL1R 0U +#endif /* !STM32_RCC_PLL1_HAS_R */ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +__STATIC_INLINE bool pll1_not_locked(void) { + + return (bool)((RCC->CR & RCC_CR_PLL1RDY) == 0U); +} + +__STATIC_INLINE void pll1_wait_lock(void) { + + while (pll1_not_locked()) { + /* Waiting for PLL1 lock.*/ + } +} + +#endif /* STM32_RCC_HAS_PLL1 */ + +__STATIC_INLINE void pll1_init(void) { + +#if STM32_RCC_HAS_PLL1 +#if STM32_ACTIVATE_PLL1 + /* PLL1 activation.*/ + RCC->PLL1CFGR = STM32_PLL1PDIV | STM32_PLL1R | + STM32_PLL1REN | STM32_PLL1Q | + STM32_PLL1QEN | STM32_PLL1P | + STM32_PLL1PEN | STM32_PLL1N | + STM32_PLL1M | STM32_PLL1SRC; + RCC->CR |= RCC_CR_PLL1ON; + + pll1_wait_lock(); +#endif +#endif +} + +__STATIC_INLINE void pll1_deinit(void) { + +#if STM32_RCC_HAS_PLL1 +#if STM32_ACTIVATE_PLL1 + /* PLL1 de-activation.*/ + RCC->CR &= ~RCC_CR_PLL1ON; +#endif +#endif +} + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** @} */ diff --git a/os/hal/ports/STM32/LLD/RCCv1/stm32_pll2.inc b/os/hal/ports/STM32/LLD/RCCv1/stm32_pll2.inc new file mode 100644 index 000000000..999897f54 --- /dev/null +++ b/os/hal/ports/STM32/LLD/RCCv1/stm32_pll2.inc @@ -0,0 +1,381 @@ +/* + ChibiOS - Copyright (C) 2006..2023 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file RCCv1/stm32_pll2.inc + * @brief Shared PLL2 handler. + * + * @addtogroup STM32_PLL2_HANDLER + * @{ + */ + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/* Checks on registry.*/ +#if !defined(STM32_RCC_HAS_PLL2) +#error "STM32_RCC_HAS_PLL2 not defined in stm32_registry.h" +#endif + +#if STM32_RCC_HAS_PLL2 && !defined(STM32_RCC_PLL2_HAS_P) +#error "STM32_RCC_PLL2_HAS_P not defined in stm32_registry.h" +#endif + +#if STM32_RCC_HAS_PLL2 && !defined(STM32_RCC_PLL2_HAS_Q) +#error "STM32_RCC_PLL2_HAS_Q not defined in stm32_registry.h" +#endif + +#if STM32_RCC_HAS_PLL2 && !defined(STM32_RCC_PLL2_HAS_R) +#error "STM32_RCC_PLL2_HAS_R not defined in stm32_registry.h" +#endif + +#if STM32_RCC_HAS_PLL2 + +/* Checks on configurations.*/ +#if !defined(STM32_PLL2SRC) +#error "STM32_PLL2SRC not defined in mcuconf.h" +#endif + +#if !defined(STM32_PLL2M_VALUE) +#error "STM32_PLL2M_VALUE not defined in mcuconf.h" +#endif + +#if !defined(STM32_PLL2N_VALUE) +#error "STM32_PLL2N_VALUE not defined in mcuconf.h" +#endif + +#if !defined(STM32_PLL2PDIV_VALUE) +#error "STM32_PLL2PDIV_VALUE not defined in mcuconf.h" +#endif + +#if STM32_RCC_PLL2_HAS_P && !defined(STM32_PLL2P_VALUE) +#error "STM32_PLL2P_VALUE not defined in mcuconf.h" +#endif + +#if STM32_RCC_PLL2_HAS_Q && !defined(STM32_PLL2Q_VALUE) +#error "STM32_PLL2Q_VALUE not defined in mcuconf.h" +#endif + +#if STM32_RCC_PLL2_HAS_R && !defined(STM32_PLL2R_VALUE) +#error "STM32_PLL2R_VALUE not defined in mcuconf.h" +#endif + +/* Check on limits.*/ +#if !defined(STM32_PLL2IN_MAX) +#error "STM32_PLL2IN_MAX not defined in hal_lld.h" +#endif + +#if !defined(STM32_PLL2IN_MIN) +#error "STM32_PLL2IN_MIN not defined in hal_lld.h" +#endif + +#if !defined(STM32_PLL2VCO_MAX) +#error "STM32_PLL2VCO_MAX not defined in hal_lld.h" +#endif + +#if !defined(STM32_PLL2VCO_MIN) +#error "STM32_PLL2VCO_MIN not defined in hal_lld.h" +#endif + +#if !defined(STM32_PLL2P_MAX) +#error "STM32_PLL2P_MAX not defined in hal_lld.h" +#endif + +#if !defined(STM32_PLL2P_MIN) +#error "STM32_PLL2P_MIN not defined in hal_lld.h" +#endif + +#if !defined(STM32_PLL2Q_MAX) +#error "STM32_PLL2Q_MAX not defined in hal_lld.h" +#endif + +#if !defined(STM32_PLL2Q_MIN) +#error "STM32_PLL2Q_MIN not defined in hal_lld.h" +#endif + +#if !defined(STM32_PLL2R_MAX) +#error "STM32_PLL2R_MAX not defined in hal_lld.h" +#endif + +#if !defined(STM32_PLL2R_MIN) +#error "STM32_PLL2R_MIN not defined in hal_lld.h" +#endif + +/* Input checks.*/ +#if !defined(STM32_ACTIVATE_PLL2) +#error "STM32_ACTIVATE_PLL2 not defined in hal_lld.h" +#endif + +#if STM32_RCC_PLL2_HAS_P && !defined(STM32_PLL2PEN) +#error "STM32_PLL2PEN not defined in hal_lld.h" +#endif + +#if STM32_RCC_PLL2_HAS_Q && !defined(STM32_PLL2QEN) +#error "STM32_PLL2QEN not defined in hal_lld.h" +#endif + +#if STM32_RCC_PLL2_HAS_R && !defined(STM32_PLL2REN) +#error "STM32_PLL2REN not defined in hal_lld.h" +#endif + +#if STM32_ACTIVATE_PLL2 && (STM32_PLL2CLKIN == 0) +#error "PLL2 activation required but no PLL2 clock selected" +#endif + +#if (STM32_PLL2CLKIN != 0) && \ + ((STM32_PLL2CLKIN < STM32_PLL2IN_MIN) || (STM32_PLL2CLKIN > STM32_PLL2IN_MAX)) +#error "STM32_PLL2CLKIN outside acceptable range (STM32_PLL2IN_MIN...STM32_PLL2IN_MAX)" +#endif + +/** + * @brief STM32_PLL2M field. + */ +#if ((STM32_PLL2M_VALUE >= 1) && (STM32_PLL2M_VALUE <= 16)) || \ + defined(__DOXYGEN__) +#define STM32_PLL2M ((STM32_PLL2M_VALUE - 1U) << RCC_PLL2CFGR_PLL2M_Pos) + +#else +#error "invalid STM32_PLL2M_VALUE value specified" +#endif + +/** + * @brief STM32_PLL2N field. + */ +#if ((STM32_PLL2N_VALUE >= 8) && (STM32_PLL2N_VALUE <= 127)) || \ + defined(__DOXYGEN__) +#define STM32_PLL2N (STM32_PLL2N_VALUE << RCC_PLL2CFGR_PLL2N_Pos) + +#else +#error "invalid STM32_PLL2N_VALUE value specified" +#endif + +/** + * @brief PLL2 VCO frequency. + */ +#define STM32_PLL2VCO (STM32_PLL2CLKIN * STM32_PLL2N_VALUE) + +/* + * PLL2 VCO frequency range check. + */ +#if STM32_ACTIVATE_PLL2 && \ + ((STM32_PLL2VCO < STM32_PLL2VCO_MIN) || (STM32_PLL2VCO > STM32_PLL2VCO_MAX)) +#error "STM32_PLL2VCO outside acceptable range (STM32_PLL2VCO_MIN...STM32_PLL2VCO_MAX)" +#endif + +/*---------------------------------------------------------------------------*/ +/* P output, if present. */ +/*---------------------------------------------------------------------------*/ +#if STM32_RCC_PLL2_HAS_P || defined(__DOXYGEN__) +/** + * @brief STM32_PLL2P field. + */ +#if (STM32_PLL2P_VALUE == 7) || defined(__DOXYGEN__) +#define STM32_PLL2P (0U << RCC_PLL2CFGR_PLL2P_Pos) + +#elif STM32_PLL2P_VALUE == 17 +#define STM32_PLL2P (1U << RCC_PLL2CFGR_PLL2P_Pos) + +#else +#error "invalid STM32_PLL2P_VALUE value specified" +#endif + +/* PDIV is not present on all devices.*/ +#if defined(RCC_PLL2CFGR_PLL2PDIV_Pos) || defined(__DOXYGEN__) +/** + * @brief STM32_PLL2PDIV field. + */ +#if (STM32_PLL2PDIV_VALUE == 0) || \ + ((STM32_PLL2PDIV_VALUE >= 2) && (STM32_PLL2PDIV_VALUE <= 31)) || \ + defined(__DOXYGEN__) +#define STM32_PLL2PDIV (STM32_PLL2PDIV_VALUE << RCC_PLL2CFGR_PLL2PDIV_Pos) +#else +#error "invalid STM32_PLL2PDIV_VALUE value specified" +#endif + +/** + * @brief PLL2 P output clock frequency. + */ +#if (STM32_PLL2PDIV_VALUE == 0) || defined(__DOXYGEN__) +#define STM32_PLL2_P_CLKOUT (STM32_PLL2VCO / STM32_PLL2P_VALUE) +#else +#define STM32_PLL2_P_CLKOUT (STM32_PLL2VCO / STM32_PLL2PDIV_VALUE) +#endif + +#else +#define STM32_PLL2_P_CLKOUT (STM32_PLL2VCO / STM32_PLL2P_VALUE) +#define STM32_PLL2PDIV 0U +#endif + +/* + * PLL2-P output frequency range check. + */ +#if STM32_ACTIVATE_PLL2 && \ + ((STM32_PLL2_P_CLKOUT < STM32_PLL2P_MIN) || (STM32_PLL2_P_CLKOUT > STM32_PLL2P_MAX)) +#error "STM32_PLL2_P_CLKOUT outside acceptable range (STM32_PLL2P_MIN...STM32_PLL2P_MAX)" +#endif + +#else /* !STM32_RCC_PLL2_HAS_P */ +#define STM32_PLL2P 0U +#define STM32_PLL2PDIV 0U +#endif /* !STM32_RCC_PLL2_HAS_P */ + +/*---------------------------------------------------------------------------*/ +/* Q output, if present. */ +/*---------------------------------------------------------------------------*/ +#if STM32_RCC_PLL2_HAS_Q || defined(__DOXYGEN__) +/** + * @brief STM32_PLL2Q field. + */ +#if (STM32_PLL2Q_VALUE == 2) || defined(__DOXYGEN__) +#define STM32_PLL2Q (0U << RCC_PLL2CFGR_PLL2Q_Pos) + +#elif STM32_PLL2Q_VALUE == 4 +#define STM32_PLL2Q (1U << RCC_PLL2CFGR_PLL2Q_Pos) + +#elif STM32_PLL2Q_VALUE == 6 +#define STM32_PLL2Q (2U << RCC_PLL2CFGR_PLL2Q_Pos) + +#elif STM32_PLL2Q_VALUE == 8 +#define STM32_PLL2Q (3U << RCC_PLL2CFGR_PLL2Q_Pos) + +#else +#error "invalid STM32_PLL2Q_VALUE value specified" +#endif + +/** + * @brief PLL2 Q output clock frequency. + */ +#define STM32_PLL2_Q_CLKOUT (STM32_PLL2VCO / STM32_PLL2Q_VALUE) + +/* + * PLL2-Q output frequency range check. + */ +#if STM32_ACTIVATE_PLL2 && \ + ((STM32_PLL2_Q_CLKOUT < STM32_PLL2Q_MIN) || (STM32_PLL2_Q_CLKOUT > STM32_PLL2Q_MAX)) +#error "STM32_PLL2_Q_CLKOUT outside acceptable range (STM32_PLL2Q_MIN...STM32_PLL2Q_MAX)" +#endif + +#else /* !STM32_RCC_PLL2_HAS_Q */ +#define STM32_PLL2Q 0U +#endif /* !STM32_RCC_PLL2_HAS_Q */ + +/*---------------------------------------------------------------------------*/ +/* R output, if present. */ +/*---------------------------------------------------------------------------*/ +#if STM32_RCC_PLL2_HAS_R || defined(__DOXYGEN__) +/** + * @brief STM32_PLL2R field. + */ +#if (STM32_PLL2R_VALUE == 2) || defined(__DOXYGEN__) +#define STM32_PLL2R (0U << RCC_PLL2CFGR_PLL2R_Pos) + +#elif STM32_PLL2R_VALUE == 4 +#define STM32_PLL2R (1U << RCC_PLL2CFGR_PLL2R_Pos) + +#elif STM32_PLL2R_VALUE == 6 +#define STM32_PLL2R (2U << RCC_PLL2CFGR_PLL2R_Pos) + +#elif STM32_PLL2R_VALUE == 8 +#define STM32_PLL2R (3U << RCC_PLL2CFGR_PLL2R_Pos) + +#else +#error "invalid STM32_PLL2R_VALUE value specified" +#endif + +/** + * @brief PLL2 R output clock frequency. + */ +#define STM32_PLL2_R_CLKOUT (STM32_PLL2VCO / STM32_PLL2R_VALUE) + +/* + * PLL2-R output frequency range check. + */ +#if STM32_ACTIVATE_PLL2 && \ + ((STM32_PLL2_R_CLKOUT < STM32_PLL2R_MIN) || (STM32_PLL2_R_CLKOUT > STM32_PLL2R_MAX)) +#error "STM32_PLL2_R_CLKOUT outside acceptable range (STM32_PLL2R_MIN...STM32_PLL2R_MAX)" +#endif + +#else /* !STM32_RCC_PLL2_HAS_R */ +#define STM32_PLL2R 0U +#endif /* !STM32_RCC_PLL2_HAS_R */ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +__STATIC_INLINE bool pll2_not_locked(void) { + + return (bool)((RCC->CR & RCC_CR_PLL2RDY) == 0U); +} + +__STATIC_INLINE void pll2_wait_lock(void) { + + while (pll2_not_locked()) { + /* Waiting for PLL2 lock.*/ + } +} + +#endif /* STM32_RCC_HAS_PLL2 */ + +__STATIC_INLINE void pll2_init(void) { + +#if STM32_RCC_HAS_PLL2 +#if STM32_ACTIVATE_PLL2 + /* PLL2 activation.*/ + RCC->PLL2CFGR = STM32_PLL2PDIV | STM32_PLL2R | + STM32_PLL2REN | STM32_PLL2Q | + STM32_PLL2QEN | STM32_PLL2P | + STM32_PLL2PEN | STM32_PLL2N | + STM32_PLL2M | STM32_PLL2SRC; + RCC->CR |= RCC_CR_PLL2ON; + + pll2_wait_lock(); +#endif +#endif +} + +__STATIC_INLINE void pll2_deinit(void) { + +#if STM32_RCC_HAS_PLL2 +#if STM32_ACTIVATE_PLL2 + /* PLL2 de-activation.*/ + RCC->CR &= ~RCC_CR_PLL2ON; +#endif +#endif +} + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** @} */ diff --git a/os/hal/ports/STM32/LLD/RCCv1/stm32_pll3.inc b/os/hal/ports/STM32/LLD/RCCv1/stm32_pll3.inc new file mode 100644 index 000000000..43fc24f09 --- /dev/null +++ b/os/hal/ports/STM32/LLD/RCCv1/stm32_pll3.inc @@ -0,0 +1,381 @@ +/* + ChibiOS - Copyright (C) 2006..2023 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file RCCv1/stm32_pll3.inc + * @brief Shared PLL3 handler. + * + * @addtogroup STM32_PLL3_HANDLER + * @{ + */ + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/* Checks on registry.*/ +#if !defined(STM32_RCC_HAS_PLL3) +#error "STM32_RCC_HAS_PLL3 not defined in stm32_registry.h" +#endif + +#if STM32_RCC_HAS_PLL3 && !defined(STM32_RCC_PLL3_HAS_P) +#error "STM32_RCC_PLL3_HAS_P not defined in stm32_registry.h" +#endif + +#if STM32_RCC_HAS_PLL3 && !defined(STM32_RCC_PLL3_HAS_Q) +#error "STM32_RCC_PLL3_HAS_Q not defined in stm32_registry.h" +#endif + +#if STM32_RCC_HAS_PLL3 && !defined(STM32_RCC_PLL3_HAS_R) +#error "STM32_RCC_PLL3_HAS_R not defined in stm32_registry.h" +#endif + +#if STM32_RCC_HAS_PLL3 + +/* Checks on configurations.*/ +#if !defined(STM32_PLL3SRC) +#error "STM32_PLL3SRC not defined in mcuconf.h" +#endif + +#if !defined(STM32_PLL3M_VALUE) +#error "STM32_PLL3M_VALUE not defined in mcuconf.h" +#endif + +#if !defined(STM32_PLL3N_VALUE) +#error "STM32_PLL3N_VALUE not defined in mcuconf.h" +#endif + +#if !defined(STM32_PLL3PDIV_VALUE) +#error "STM32_PLL3PDIV_VALUE not defined in mcuconf.h" +#endif + +#if STM32_RCC_PLL3_HAS_P && !defined(STM32_PLL3P_VALUE) +#error "STM32_PLL3P_VALUE not defined in mcuconf.h" +#endif + +#if STM32_RCC_PLL3_HAS_Q && !defined(STM32_PLL3Q_VALUE) +#error "STM32_PLL3Q_VALUE not defined in mcuconf.h" +#endif + +#if STM32_RCC_PLL3_HAS_R && !defined(STM32_PLL3R_VALUE) +#error "STM32_PLL3R_VALUE not defined in mcuconf.h" +#endif + +/* Check on limits.*/ +#if !defined(STM32_PLL3IN_MAX) +#error "STM32_PLL3IN_MAX not defined in hal_lld.h" +#endif + +#if !defined(STM32_PLL3IN_MIN) +#error "STM32_PLL3IN_MIN not defined in hal_lld.h" +#endif + +#if !defined(STM32_PLL3VCO_MAX) +#error "STM32_PLL3VCO_MAX not defined in hal_lld.h" +#endif + +#if !defined(STM32_PLL3VCO_MIN) +#error "STM32_PLL3VCO_MIN not defined in hal_lld.h" +#endif + +#if !defined(STM32_PLL3P_MAX) +#error "STM32_PLL3P_MAX not defined in hal_lld.h" +#endif + +#if !defined(STM32_PLL3P_MIN) +#error "STM32_PLL3P_MIN not defined in hal_lld.h" +#endif + +#if !defined(STM32_PLL3Q_MAX) +#error "STM32_PLL3Q_MAX not defined in hal_lld.h" +#endif + +#if !defined(STM32_PLL3Q_MIN) +#error "STM32_PLL3Q_MIN not defined in hal_lld.h" +#endif + +#if !defined(STM32_PLL3R_MAX) +#error "STM32_PLL3R_MAX not defined in hal_lld.h" +#endif + +#if !defined(STM32_PLL3R_MIN) +#error "STM32_PLL3R_MIN not defined in hal_lld.h" +#endif + +/* Input checks.*/ +#if !defined(STM32_ACTIVATE_PLL3) +#error "STM32_ACTIVATE_PLL3 not defined in hal_lld.h" +#endif + +#if STM32_RCC_PLL3_HAS_P && !defined(STM32_PLL3PEN) +#error "STM32_PLL3PEN not defined in hal_lld.h" +#endif + +#if STM32_RCC_PLL3_HAS_Q && !defined(STM32_PLL3QEN) +#error "STM32_PLL3QEN not defined in hal_lld.h" +#endif + +#if STM32_RCC_PLL3_HAS_R && !defined(STM32_PLL3REN) +#error "STM32_PLL3REN not defined in hal_lld.h" +#endif + +#if STM32_ACTIVATE_PLL3 && (STM32_PLL3CLKIN == 0) +#error "PLL3 activation required but no PLL3 clock selected" +#endif + +#if (STM32_PLL3CLKIN != 0) && \ + ((STM32_PLL3CLKIN < STM32_PLL3IN_MIN) || (STM32_PLL3CLKIN > STM32_PLL3IN_MAX)) +#error "STM32_PLL3CLKIN outside acceptable range (STM32_PLL3IN_MIN...STM32_PLL3IN_MAX)" +#endif + +/** + * @brief STM32_PLL3M field. + */ +#if ((STM32_PLL3M_VALUE >= 1) && (STM32_PLL3M_VALUE <= 16)) || \ + defined(__DOXYGEN__) +#define STM32_PLL3M ((STM32_PLL3M_VALUE - 1U) << RCC_PLL3CFGR_PLL3M_Pos) + +#else +#error "invalid STM32_PLL3M_VALUE value specified" +#endif + +/** + * @brief STM32_PLL3N field. + */ +#if ((STM32_PLL3N_VALUE >= 8) && (STM32_PLL3N_VALUE <= 127)) || \ + defined(__DOXYGEN__) +#define STM32_PLL3N (STM32_PLL3N_VALUE << RCC_PLL3CFGR_PLL3N_Pos) + +#else +#error "invalid STM32_PLL3N_VALUE value specified" +#endif + +/** + * @brief PLL3 VCO frequency. + */ +#define STM32_PLL3VCO (STM32_PLL3CLKIN * STM32_PLL3N_VALUE) + +/* + * PLL3 VCO frequency range check. + */ +#if STM32_ACTIVATE_PLL3 && \ + ((STM32_PLL3VCO < STM32_PLL3VCO_MIN) || (STM32_PLL3VCO > STM32_PLL3VCO_MAX)) +#error "STM32_PLL3VCO outside acceptable range (STM32_PLL3VCO_MIN...STM32_PLL3VCO_MAX)" +#endif + +/*---------------------------------------------------------------------------*/ +/* P output, if present. */ +/*---------------------------------------------------------------------------*/ +#if STM32_RCC_PLL3_HAS_P || defined(__DOXYGEN__) +/** + * @brief STM32_PLL3P field. + */ +#if (STM32_PLL3P_VALUE == 7) || defined(__DOXYGEN__) +#define STM32_PLL3P (0U << RCC_PLL3CFGR_PLL3P_Pos) + +#elif STM32_PLL3P_VALUE == 17 +#define STM32_PLL3P (1U << RCC_PLL3CFGR_PLL3P_Pos) + +#else +#error "invalid STM32_PLL3P_VALUE value specified" +#endif + +/* PDIV is not present on all devices.*/ +#if defined(RCC_PLL3CFGR_PLL3PDIV_Pos) || defined(__DOXYGEN__) +/** + * @brief STM32_PLL3PDIV field. + */ +#if (STM32_PLL3PDIV_VALUE == 0) || \ + ((STM32_PLL3PDIV_VALUE >= 2) && (STM32_PLL3PDIV_VALUE <= 31)) || \ + defined(__DOXYGEN__) +#define STM32_PLL3PDIV (STM32_PLL3PDIV_VALUE << RCC_PLL3CFGR_PLL3PDIV_Pos) +#else +#error "invalid STM32_PLL3PDIV_VALUE value specified" +#endif + +/** + * @brief PLL3 P output clock frequency. + */ +#if (STM32_PLL3PDIV_VALUE == 0) || defined(__DOXYGEN__) +#define STM32_PLL3_P_CLKOUT (STM32_PLL3VCO / STM32_PLL3P_VALUE) +#else +#define STM32_PLL3_P_CLKOUT (STM32_PLL3VCO / STM32_PLL3PDIV_VALUE) +#endif + +#else +#define STM32_PLL3_P_CLKOUT (STM32_PLL3VCO / STM32_PLL3P_VALUE) +#define STM32_PLL3PDIV 0U +#endif + +/* + * PLL3-P output frequency range check. + */ +#if STM32_ACTIVATE_PLL3 && \ + ((STM32_PLL3_P_CLKOUT < STM32_PLL3P_MIN) || (STM32_PLL3_P_CLKOUT > STM32_PLL3P_MAX)) +#error "STM32_PLL3_P_CLKOUT outside acceptable range (STM32_PLL3P_MIN...STM32_PLL3P_MAX)" +#endif + +#else /* !STM32_RCC_PLL3_HAS_P */ +#define STM32_PLL3P 0U +#define STM32_PLL3PDIV 0U +#endif /* !STM32_RCC_PLL3_HAS_P */ + +/*---------------------------------------------------------------------------*/ +/* Q output, if present. */ +/*---------------------------------------------------------------------------*/ +#if STM32_RCC_PLL3_HAS_Q || defined(__DOXYGEN__) +/** + * @brief STM32_PLL3Q field. + */ +#if (STM32_PLL3Q_VALUE == 2) || defined(__DOXYGEN__) +#define STM32_PLL3Q (0U << RCC_PLL3CFGR_PLL3Q_Pos) + +#elif STM32_PLL3Q_VALUE == 4 +#define STM32_PLL3Q (1U << RCC_PLL3CFGR_PLL3Q_Pos) + +#elif STM32_PLL3Q_VALUE == 6 +#define STM32_PLL3Q (2U << RCC_PLL3CFGR_PLL3Q_Pos) + +#elif STM32_PLL3Q_VALUE == 8 +#define STM32_PLL3Q (3U << RCC_PLL3CFGR_PLL3Q_Pos) + +#else +#error "invalid STM32_PLL3Q_VALUE value specified" +#endif + +/** + * @brief PLL3 Q output clock frequency. + */ +#define STM32_PLL3_Q_CLKOUT (STM32_PLL3VCO / STM32_PLL3Q_VALUE) + +/* + * PLL3-Q output frequency range check. + */ +#if STM32_ACTIVATE_PLL3 && \ + ((STM32_PLL3_Q_CLKOUT < STM32_PLL3Q_MIN) || (STM32_PLL3_Q_CLKOUT > STM32_PLL3Q_MAX)) +#error "STM32_PLL3_Q_CLKOUT outside acceptable range (STM32_PLL3Q_MIN...STM32_PLL3Q_MAX)" +#endif + +#else /* !STM32_RCC_PLL3_HAS_Q */ +#define STM32_PLL3Q 0U +#endif /* !STM32_RCC_PLL3_HAS_Q */ + +/*---------------------------------------------------------------------------*/ +/* R output, if present. */ +/*---------------------------------------------------------------------------*/ +#if STM32_RCC_PLL3_HAS_R || defined(__DOXYGEN__) +/** + * @brief STM32_PLL3R field. + */ +#if (STM32_PLL3R_VALUE == 2) || defined(__DOXYGEN__) +#define STM32_PLL3R (0U << RCC_PLL3CFGR_PLL3R_Pos) + +#elif STM32_PLL3R_VALUE == 4 +#define STM32_PLL3R (1U << RCC_PLL3CFGR_PLL3R_Pos) + +#elif STM32_PLL3R_VALUE == 6 +#define STM32_PLL3R (2U << RCC_PLL3CFGR_PLL3R_Pos) + +#elif STM32_PLL3R_VALUE == 8 +#define STM32_PLL3R (3U << RCC_PLL3CFGR_PLL3R_Pos) + +#else +#error "invalid STM32_PLL3R_VALUE value specified" +#endif + +/** + * @brief PLL3 R output clock frequency. + */ +#define STM32_PLL3_R_CLKOUT (STM32_PLL3VCO / STM32_PLL3R_VALUE) + +/* + * PLL3-R output frequency range check. + */ +#if STM32_ACTIVATE_PLL3 && \ + ((STM32_PLL3_R_CLKOUT < STM32_PLL3R_MIN) || (STM32_PLL3_R_CLKOUT > STM32_PLL3R_MAX)) +#error "STM32_PLL3_R_CLKOUT outside acceptable range (STM32_PLL3R_MIN...STM32_PLL3R_MAX)" +#endif + +#else /* !STM32_RCC_PLL3_HAS_R */ +#define STM32_PLL3R 0U +#endif /* !STM32_RCC_PLL3_HAS_R */ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +__STATIC_INLINE bool pll3_not_locked(void) { + + return (bool)((RCC->CR & RCC_CR_PLL3RDY) == 0U); +} + +__STATIC_INLINE void pll3_wait_lock(void) { + + while (pll3_not_locked()) { + /* Waiting for PLL3 lock.*/ + } +} + +#endif /* STM32_RCC_HAS_PLL3 */ + +__STATIC_INLINE void pll3_init(void) { + +#if STM32_RCC_HAS_PLL3 +#if STM32_ACTIVATE_PLL3 + /* PLL3 activation.*/ + RCC->PLL3CFGR = STM32_PLL3PDIV | STM32_PLL3R | + STM32_PLL3REN | STM32_PLL3Q | + STM32_PLL3QEN | STM32_PLL3P | + STM32_PLL3PEN | STM32_PLL3N | + STM32_PLL3M | STM32_PLL3SRC; + RCC->CR |= RCC_CR_PLL3ON; + + pll3_wait_lock(); +#endif +#endif +} + +__STATIC_INLINE void pll3_deinit(void) { + +#if STM32_RCC_HAS_PLL3 +#if STM32_ACTIVATE_PLL3 + /* PLL3 de-activation.*/ + RCC->CR &= ~RCC_CR_PLL3ON; +#endif +#endif +} + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** @} */ diff --git a/os/hal/ports/STM32/STM32H5xx/stm32_isr.c b/os/hal/ports/STM32/STM32H5xx/stm32_isr.c index 53c0de59e..73b7c752d 100644 --- a/os/hal/ports/STM32/STM32H5xx/stm32_isr.c +++ b/os/hal/ports/STM32/STM32H5xx/stm32_isr.c @@ -1,5 +1,5 @@ /* - ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + ChibiOS - Copyright (C) 2006..2023 Giovanni Di Sirio Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. @@ -15,10 +15,10 @@ */ /** - * @file STM32G4xx/stm32_isr.c - * @brief STM32G4xx ISR handler code. + * @file STM32H5xx/stm32_isr.c + * @brief STM32H5xx ISR handler code. * - * @addtogroup STM32G4xx_ISR + * @addtogroup STM32H5xx_ISR * @{ */ @@ -56,29 +56,33 @@ #include "stm32_exti2.inc" #include "stm32_exti3.inc" #include "stm32_exti4.inc" -#include "stm32_exti5_9.inc" -#include "stm32_exti10_15.inc" -#include "stm32_exti16-40_41.inc" -#include "stm32_exti17.inc" -#include "stm32_exti18.inc" -#include "stm32_exti19.inc" -#include "stm32_exti20.inc" -#include "stm32_exti21_22-29.inc" -#include "stm32_exti30_32.inc" -#include "stm32_exti33.inc" - -#include "stm32_fdcan1.inc" -#include "stm32_fdcan2.inc" -#include "stm32_fdcan3.inc" +#include "stm32_exti5.inc" +#include "stm32_exti6.inc" +#include "stm32_exti7.inc" +#include "stm32_exti8.inc" +#include "stm32_exti9.inc" +#include "stm32_exti10.inc" +#include "stm32_exti11.inc" +#include "stm32_exti12.inc" +#include "stm32_exti13.inc" +#include "stm32_exti14.inc" +#include "stm32_exti15.inc" #include "stm32_usart1.inc" #include "stm32_usart2.inc" #include "stm32_usart3.inc" #include "stm32_uart4.inc" #include "stm32_uart5.inc" +#include "stm32_usart6.inc" +#include "stm32_uart7.inc" +#include "stm32_uart8.inc" +#include "stm32_uart9.inc" +#include "stm32_usart10.inc" +//#include "stm32_usart11.inc" +//#include "stm32_uart12.inc" #include "stm32_lpuart1.inc" -#include "stm32_tim1_15_16_17.inc" +#include "stm32_tim1.inc" #include "stm32_tim2.inc" #include "stm32_tim3.inc" #include "stm32_tim4.inc" @@ -86,7 +90,12 @@ #include "stm32_tim6.inc" #include "stm32_tim7.inc" #include "stm32_tim8.inc" -#include "stm32_tim20.inc" +#include "stm32_tim12.inc" +#include "stm32_tim13.inc" +#include "stm32_tim14.inc" +#include "stm32_tim15.inc" +#include "stm32_tim16.inc" +#include "stm32_tim17.inc" /*===========================================================================*/ /* Driver exported functions. */ @@ -104,21 +113,19 @@ void irqInit(void) { exti2_irq_init(); exti3_irq_init(); exti4_irq_init(); - exti5_9_irq_init(); - exti10_15_irq_init(); - exti16_exti40_exti41_irq_init(); - exti17_irq_init(); - exti18_irq_init(); - exti19_irq_init(); - exti21_exti22_exti29_irq_init(); - exti30_32_irq_init(); - exti33_irq_init(); + exti5_irq_init(); + exti6_irq_init(); + exti7_irq_init(); + exti8_irq_init(); + exti9_irq_init(); + exti10_irq_init(); + exti11_irq_init(); + exti12_irq_init(); + exti13_irq_init(); + exti14_irq_init(); + exti15_irq_init(); - fdcan1_irq_init(); - fdcan2_irq_init(); - fdcan3_irq_init(); - - tim1_tim15_tim16_tim17_irq_init(); + tim1_irq_init(); tim2_irq_init(); tim3_irq_init(); tim4_irq_init(); @@ -126,13 +133,23 @@ void irqInit(void) { tim6_irq_init(); tim7_irq_init(); tim8_irq_init(); - tim20_irq_init(); + tim12_irq_init(); + tim13_irq_init(); + tim14_irq_init(); + tim15_irq_init(); + tim16_irq_init(); + tim17_irq_init(); usart1_irq_init(); usart2_irq_init(); usart3_irq_init(); uart4_irq_init(); uart5_irq_init(); + usart6_irq_init(); + uart7_irq_init(); + uart8_irq_init(); + uart9_irq_init(); + usart10_irq_init(); lpuart1_irq_init(); } @@ -148,21 +165,19 @@ void irqDeinit(void) { exti2_irq_deinit(); exti3_irq_deinit(); exti4_irq_deinit(); - exti5_9_irq_deinit(); - exti10_15_irq_deinit(); - exti16_exti40_exti41_irq_deinit(); - exti17_irq_deinit(); - exti18_irq_deinit(); - exti19_irq_deinit(); - exti21_exti22_exti29_irq_deinit(); - exti30_32_irq_deinit(); - exti33_irq_deinit(); + exti5_irq_deinit(); + exti6_irq_deinit(); + exti7_irq_deinit(); + exti8_irq_deinit(); + exti9_irq_deinit(); + exti10_irq_deinit(); + exti11_irq_deinit(); + exti12_irq_deinit(); + exti13_irq_deinit(); + exti14_irq_deinit(); + exti15_irq_deinit(); - fdcan1_irq_deinit(); - fdcan2_irq_deinit(); - fdcan3_irq_deinit(); - - tim1_tim15_tim16_tim17_irq_deinit(); + tim1_irq_deinit(); tim2_irq_deinit(); tim3_irq_deinit(); tim4_irq_deinit(); @@ -170,13 +185,23 @@ void irqDeinit(void) { tim6_irq_deinit(); tim7_irq_deinit(); tim8_irq_deinit(); - tim20_irq_deinit(); + tim12_irq_deinit(); + tim13_irq_deinit(); + tim14_irq_deinit(); + tim15_irq_deinit(); + tim16_irq_deinit(); + tim17_irq_deinit(); usart1_irq_deinit(); usart2_irq_deinit(); usart3_irq_deinit(); uart4_irq_deinit(); uart5_irq_deinit(); + usart6_irq_deinit(); + uart7_irq_deinit(); + uart8_irq_deinit(); + uart9_irq_deinit(); + usart10_irq_deinit(); lpuart1_irq_deinit(); } diff --git a/os/hal/ports/STM32/STM32H5xx/stm32_isr.h b/os/hal/ports/STM32/STM32H5xx/stm32_isr.h index d1dfdd066..cdbcde0a6 100644 --- a/os/hal/ports/STM32/STM32H5xx/stm32_isr.h +++ b/os/hal/ports/STM32/STM32H5xx/stm32_isr.h @@ -1,5 +1,5 @@ /* - ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + ChibiOS - Copyright (C) 2006..2023 Giovanni Di Sirio Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. @@ -15,10 +15,10 @@ */ /** - * @file STM32G4xx/stm32_isr.h - * @brief STM32G4xx ISR handler header. + * @file STM32H5xx/stm32_isr.h + * @brief STM32H5xx ISR handler header. * - * @addtogroup STM32G4xx_ISR + * @addtogroup STM32H5xx_ISR * @{ */ @@ -41,16 +41,25 @@ #define STM32_TIM6_SUPPRESS_ISR #define STM32_TIM7_SUPPRESS_ISR #define STM32_TIM8_SUPPRESS_ISR +#define STM32_TIM12_SUPPRESS_ISR +#define STM32_TIM13_SUPPRESS_ISR +#define STM32_TIM14_SUPPRESS_ISR #define STM32_TIM15_SUPPRESS_ISR #define STM32_TIM16_SUPPRESS_ISR #define STM32_TIM17_SUPPRESS_ISR -#define STM32_TIM20_SUPPRESS_ISR #define STM32_USART1_SUPPRESS_ISR #define STM32_USART2_SUPPRESS_ISR #define STM32_USART3_SUPPRESS_ISR #define STM32_UART4_SUPPRESS_ISR #define STM32_UART5_SUPPRESS_ISR +#define STM32_USART6_SUPPRESS_ISR +#define STM32_UART7_SUPPRESS_ISR +#define STM32_UART8_SUPPRESS_ISR +#define STM32_UART9_SUPPRESS_ISR +#define STM32_USART10_SUPPRESS_ISR +#define STM32_USART11_SUPPRESS_ISR +#define STM32_UART12_SUPPRESS_ISR #define STM32_LPUART1_SUPPRESS_ISR /** @} */ @@ -61,207 +70,130 @@ /* * ADC unit. */ -#define STM32_ADC1_HANDLER Vector88 -#define STM32_ADC2_HANDLER Vector88 -#define STM32_ADC3_HANDLER VectorFC -#define STM32_ADC4_HANDLER Vector134 -#define STM32_ADC5_HANDLER Vector138 +#define STM32_ADC1_HANDLER VectorD4 -#define STM32_ADC1_NUMBER 18 -#define STM32_ADC2_NUMBER 18 -#define STM32_ADC3_NUMBER 47 -#define STM32_ADC4_NUMBER 61 -#define STM32_ADC5_NUMBER 62 - -/* - * DMA unit. - */ -#define STM32_DMA1_CH1_HANDLER Vector6C -#define STM32_DMA1_CH2_HANDLER Vector70 -#define STM32_DMA1_CH3_HANDLER Vector74 -#define STM32_DMA1_CH4_HANDLER Vector78 -#define STM32_DMA1_CH5_HANDLER Vector7C -#define STM32_DMA1_CH6_HANDLER Vector80 -#if !defined(STM32G431xx) && !defined(STM32G441xx) -#define STM32_DMA1_CH7_HANDLER Vector84 -#define STM32_DMA1_CH8_HANDLER Vector1C0 -#endif -#define STM32_DMA2_CH1_HANDLER Vector120 -#define STM32_DMA2_CH2_HANDLER Vector124 -#define STM32_DMA2_CH3_HANDLER Vector128 -#define STM32_DMA2_CH4_HANDLER Vector12C -#define STM32_DMA2_CH5_HANDLER Vector130 -#define STM32_DMA2_CH6_HANDLER Vector1C4 -#if !defined(STM32G431xx) && !defined(STM32G441xx) -#define STM32_DMA2_CH7_HANDLER Vector1C8 -#define STM32_DMA2_CH8_HANDLER Vector1CC -#endif - -#define STM32_DMA1_CH1_NUMBER 11 -#define STM32_DMA1_CH2_NUMBER 12 -#define STM32_DMA1_CH3_NUMBER 13 -#define STM32_DMA1_CH4_NUMBER 14 -#define STM32_DMA1_CH5_NUMBER 15 -#define STM32_DMA1_CH6_NUMBER 16 -#if !defined(STM32G431xx) && !defined(STM32G441xx) -#define STM32_DMA1_CH7_NUMBER 17 -#define STM32_DMA1_CH8_NUMBER 96 -#endif -#define STM32_DMA2_CH1_NUMBER 56 -#define STM32_DMA2_CH2_NUMBER 57 -#define STM32_DMA2_CH3_NUMBER 58 -#define STM32_DMA2_CH4_NUMBER 59 -#define STM32_DMA2_CH5_NUMBER 60 -#define STM32_DMA2_CH6_NUMBER 97 -#if !defined(STM32G431xx) && !defined(STM32G441xx) -#define STM32_DMA2_CH7_NUMBER 98 -#define STM32_DMA2_CH8_NUMBER 99 -#endif +#define STM32_ADC1_NUMBER 37 /* * EXTI unit. */ -#define STM32_EXTI0_HANDLER Vector58 -#define STM32_EXTI1_HANDLER Vector5C -#define STM32_EXTI2_HANDLER Vector60 -#define STM32_EXTI3_HANDLER Vector64 -#define STM32_EXTI4_HANDLER Vector68 -#define STM32_EXTI5_9_HANDLER Vector9C -#define STM32_EXTI10_15_HANDLER VectorE0 -#define STM32_EXTI164041_HANDLER Vector44 /* PVD PVM */ -#define STM32_EXTI17_HANDLER VectorE4 /* RTC ALARM */ -#define STM32_EXTI18_HANDLER VectorE8 /* USB WAKEUP */ -#define STM32_EXTI19_HANDLER Vector48 /* RTC TAMP CSS */ -#define STM32_EXTI20_HANDLER Vector4C /* RTC WAKEUP */ -#define STM32_EXTI212229_HANDLER Vector140 /* COMP1..3 */ -#define STM32_EXTI30_32_HANDLER Vector144 /* COMP4..6 */ -#define STM32_EXTI33_HANDLER Vector148 /* COMP7 */ +#define STM32_EXTI0_HANDLER Vector6C +#define STM32_EXTI1_HANDLER Vector70 +#define STM32_EXTI2_HANDLER Vector74 +#define STM32_EXTI3_HANDLER Vector78 +#define STM32_EXTI4_HANDLER Vector7C +#define STM32_EXTI5_HANDLER Vector80 +#define STM32_EXTI6_HANDLER Vector84 +#define STM32_EXTI7_HANDLER Vector88 +#define STM32_EXTI8_HANDLER Vector8C +#define STM32_EXTI9_HANDLER Vector90 +#define STM32_EXTI10_HANDLER Vector94 +#define STM32_EXTI11_HANDLER Vector98 +#define STM32_EXTI12_HANDLER Vector9C +#define STM32_EXTI13_HANDLER VectorA0 +#define STM32_EXTI14_HANDLER VectorA4 +#define STM32_EXTI15_HANDLER VectorA8 -#define STM32_EXTI0_NUMBER 6 -#define STM32_EXTI1_NUMBER 7 -#define STM32_EXTI2_NUMBER 8 -#define STM32_EXTI3_NUMBER 9 -#define STM32_EXTI4_NUMBER 10 -#define STM32_EXTI5_9_NUMBER 23 -#define STM32_EXTI10_15_NUMBER 40 -#define STM32_EXTI164041_NUMBER 1 -#define STM32_EXTI17_NUMBER 41 -#define STM32_EXTI18_NUMBER 42 -#define STM32_EXTI19_NUMBER 2 -#define STM32_EXTI20_NUMBER 3 -#define STM32_EXTI212229_NUMBER 64 -#define STM32_EXTI30_32_NUMBER 65 -#define STM32_EXTI33_NUMBER 66 - -/* - * FDCAN units. - */ -#define STM32_FDCAN1_IT0_HANDLER Vector94 -#define STM32_FDCAN1_IT1_HANDLER Vector98 -#define STM32_FDCAN2_IT0_HANDLER Vector198 -#define STM32_FDCAN2_IT1_HANDLER Vector19C -#define STM32_FDCAN3_IT0_HANDLER Vector1A0 -#define STM32_FDCAN3_IT1_HANDLER Vector1A4 - -#define STM32_FDCAN1_IT0_NUMBER 21 -#define STM32_FDCAN1_IT1_NUMBER 22 -#define STM32_FDCAN2_IT0_NUMBER 86 -#define STM32_FDCAN2_IT1_NUMBER 87 -#define STM32_FDCAN3_IT0_NUMBER 88 -#define STM32_FDCAN3_IT1_NUMBER 89 - -/* - * I2C units. - */ -#define STM32_I2C1_EVENT_HANDLER VectorBC -#define STM32_I2C1_ERROR_HANDLER VectorC0 -#define STM32_I2C2_EVENT_HANDLER VectorC4 -#define STM32_I2C2_ERROR_HANDLER VectorC8 -#define STM32_I2C3_EVENT_HANDLER Vector1B0 -#define STM32_I2C3_ERROR_HANDLER Vector1B4 -#define STM32_I2C4_EVENT_HANDLER Vector188 -#define STM32_I2C4_ERROR_HANDLER Vector18C - -#define STM32_I2C1_EVENT_NUMBER 31 -#define STM32_I2C1_ERROR_NUMBER 32 -#define STM32_I2C2_EVENT_NUMBER 33 -#define STM32_I2C2_ERROR_NUMBER 34 -#define STM32_I2C3_EVENT_NUMBER 92 -#define STM32_I2C3_ERROR_NUMBER 93 -#define STM32_I2C4_EVENT_NUMBER 82 -#define STM32_I2C4_ERROR_NUMBER 83 - -/* - * QUADSPI unit. - */ -#define STM32_QUADSPI1_HANDLER Vector1BC -#define STM32_QUADSPI1_NUMBER 95 +#define STM32_EXTI0_NUMBER 11 +#define STM32_EXTI1_NUMBER 12 +#define STM32_EXTI2_NUMBER 13 +#define STM32_EXTI3_NUMBER 14 +#define STM32_EXTI4_NUMBER 15 +#define STM32_EXTI5_NUMBER 16 +#define STM32_EXTI6_NUMBER 17 +#define STM32_EXTI7_NUMBER 18 +#define STM32_EXTI8_NUMBER 19 +#define STM32_EXTI9_NUMBER 20 +#define STM32_EXTI10_NUMBER 21 +#define STM32_EXTI11_NUMBER 22 +#define STM32_EXTI12_NUMBER 23 +#define STM32_EXTI13_NUMBER 24 +#define STM32_EXTI14_NUMBER 25 +#define STM32_EXTI15_NUMBER 26 /* * TIM units. */ -#define STM32_TIM1_BRK_TIM15_HANDLER VectorA0 -#define STM32_TIM1_UP_TIM16_HANDLER VectorA4 -#define STM32_TIM1_TRGCO_TIM17_HANDLER VectorA8 -#define STM32_TIM1_CC_HANDLER VectorAC -#define STM32_TIM2_HANDLER VectorB0 -#define STM32_TIM3_HANDLER VectorB4 -#define STM32_TIM4_HANDLER VectorB8 -#define STM32_TIM5_HANDLER Vector108 -#define STM32_TIM6_HANDLER Vector118 -#define STM32_TIM7_HANDLER Vector11C -#define STM32_TIM8_BRK_HANDLER VectorEC -#define STM32_TIM8_UP_HANDLER VectorF0 -#define STM32_TIM8_TRGCO_HANDLER VectorF4 -#define STM32_TIM8_CC_HANDLER VectorF8 -#define STM32_TIM20_BRK_HANDLER Vector174 -#define STM32_TIM20_UP_HANDLER Vector178 -#define STM32_TIM20_TRGCO_HANDLER Vector17C -#define STM32_TIM20_CC_HANDLER Vector180 +#define STM32_TIM1_BRK_TERR_IERR_HANDLER VectorE4 +#define STM32_TIM1_UP_HANDLER VectorE8 +#define STM32_TIM1_TRGCO_DIR_IDX_HANDLER VectorEC +#define STM32_TIM1_CC_HANDLER VectorF0 +#define STM32_TIM2_HANDLER VectorF4 +#define STM32_TIM3_HANDLER VectorF8 +#define STM32_TIM4_HANDLER VectorFC +#define STM32_TIM5_HANDLER Vector100 +#define STM32_TIM6_HANDLER Vector104 +#define STM32_TIM7_HANDLER Vector108 +#define STM32_TIM8_BRK_TERR_IERR_HANDLER Vector144 +#define STM32_TIM8_UP_HANDLER Vector148 +#define STM32_TIM8_TRGCO_DIR_IDX_HANDLER Vector14C +#define STM32_TIM8_CC_HANDLER Vector150 +#define STM32_TIM12_HANDLER Vector208 +#define STM32_TIM13_HANDLER Vector20C +#define STM32_TIM14_HANDLER Vector210 +#define STM32_TIM15_HANDLER Vector15C +#define STM32_TIM16_HANDLER Vector160 +#define STM32_TIM17_HANDLER Vector164 -#define STM32_TIM1_BRK_TIM15_NUMBER 24 -#define STM32_TIM1_UP_TIM16_NUMBER 25 -#define STM32_TIM1_TRGCO_TIM17_NUMBER 26 -#define STM32_TIM1_CC_NUMBER 27 -#define STM32_TIM2_NUMBER 28 -#define STM32_TIM3_NUMBER 29 -#define STM32_TIM4_NUMBER 30 -#define STM32_TIM5_NUMBER 50 -#define STM32_TIM6_NUMBER 54 -#define STM32_TIM7_NUMBER 55 -#define STM32_TIM8_BRK_NUMBER 43 -#define STM32_TIM8_UP_NUMBER 44 -#define STM32_TIM8_TRGCO_NUMBER 45 -#define STM32_TIM8_CC_NUMBER 46 -#define STM32_TIM20_BRK_NUMBER 77 -#define STM32_TIM20_UP_NUMBER 78 -#define STM32_TIM20_TRGCO_NUMBER 79 -#define STM32_TIM20_CC_NUMBER 80 +#define STM32_TIM1_BRK_TERR_IERR_NUMBER 41 +#define STM32_TIM1_UP_TIM16_NUMBER 42 +#define STM32_TIM1_TRGCO_DIR_IDX_NUMBER 43 +#define STM32_TIM1_CC_NUMBER 44 +#define STM32_TIM2_NUMBER 45 +#define STM32_TIM3_NUMBER 46 +#define STM32_TIM4_NUMBER 47 +#define STM32_TIM5_NUMBER 48 +#define STM32_TIM6_NUMBER 49 +#define STM32_TIM7_NUMBER 50 +#define STM32_TIM8_BRK_TERR_IERR_NUMBER 65 +#define STM32_TIM8_UP_NUMBER 66 +#define STM32_TIM8_TRGCO_DIR_IDX_NUMBER 67 +#define STM32_TIM8_CC_NUMBER 68 +#define STM32_TIM12_NUMBER 120 +#define STM32_TIM13_NUMBER 121 +#define STM32_TIM14_NUMBER 122 +#define STM32_TIM15_NUMBER 71 +#define STM32_TIM16_NUMBER 72 +#define STM32_TIM17_NUMBER 73 /* * USART/UART units. */ -#define STM32_USART1_HANDLER VectorD4 -#define STM32_USART2_HANDLER VectorD8 -#define STM32_USART3_HANDLER VectorDC -#define STM32_UART4_HANDLER Vector110 -#define STM32_UART5_HANDLER Vector114 -#define STM32_LPUART1_HANDLER Vector1AC +#define STM32_USART1_HANDLER Vector128 +#define STM32_USART2_HANDLER Vector12C +#define STM32_USART3_HANDLER Vector130 +#define STM32_UART4_HANDLER Vector134 +#define STM32_UART5_HANDLER Vector138 +#define STM32_USART6_HANDLER Vector17C +#define STM32_UART7_HANDLER VectorB0 +#define STM32_UART8_HANDLER VectorB4 +#define STM32_UART9_HANDLER VectorB8 +#define STM32_USART10_HANDLER Vector180 +#define STM32_USART11_HANDLER Vector184 +#define STM32_UART12_HANDLER VectorBC +#define STM32_LPUART1_HANDLER Vector13C -#define STM32_USART1_NUMBER 37 -#define STM32_USART2_NUMBER 38 -#define STM32_USART3_NUMBER 39 -#define STM32_UART4_NUMBER 52 -#define STM32_UART5_NUMBER 53 -#define STM32_LPUART1_NUMBER 91 +#define STM32_USART1_NUMBER 58 +#define STM32_USART2_NUMBER 59 +#define STM32_USART3_NUMBER 60 +#define STM32_UART4_NUMBER 61 +#define STM32_UART5_NUMBER 62 +#define STM32_USART6_NUMBER 85 +#define STM32_UART7_NUMBER 98 +#define STM32_UART8_NUMBER 99 +#define STM32_UART9_NUMBER 100 +#define STM32_USART10_NUMBER 86 +#define STM32_USART11_NUMBER 87 +#define STM32_UART12_NUMBER 101 +#define STM32_LPUART1_NUMBER 63 /* * USB units. */ -#define STM32_USB1_HP_HANDLER Vector8C -#define STM32_USB1_LP_HANDLER Vector90 -#define STM32_USB1_HP_NUMBER 19 -#define STM32_USB1_LP_NUMBER 20 +#define STM32_USB1_HP_HANDLER Vector168 +#define STM32_USB1_LP_HANDLER Vector168 +#define STM32_USB1_HP_NUMBER 74 +#define STM32_USB1_LP_NUMBER 74 /** @} */ /*===========================================================================*/ diff --git a/os/hal/ports/STM32/STM32H5xx/stm32_registry.h b/os/hal/ports/STM32/STM32H5xx/stm32_registry.h index ca6faa460..81e2c8e7b 100644 --- a/os/hal/ports/STM32/STM32H5xx/stm32_registry.h +++ b/os/hal/ports/STM32/STM32H5xx/stm32_registry.h @@ -1,5 +1,5 @@ /* - ChibiOS - Copyright (C) 2006..2019 Giovanni Di Sirio + ChibiOS - Copyright (C) 2006..2023 Giovanni Di Sirio Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. @@ -15,8 +15,8 @@ */ /** - * @file STM32G4xx/stm32_registry.h - * @brief STM32G4xx capabilities registry. + * @file STM32H5xx/stm32_registry.h + * @brief STM32H5xx capabilities registry. * * @addtogroup HAL * @{ @@ -30,7 +30,7 @@ /*===========================================================================*/ /** - * @name STM32G4xx capabilities + * @name STM32H5xx capabilities * @{ */ @@ -41,61 +41,6 @@ /* DAC attributes.*/ #define STM32_DAC_HAS_MCR TRUE -/* RNG attributes.*/ -#define STM32_HAS_RNG1 TRUE - -/* RTC attributes.*/ -#define STM32_HAS_RTC TRUE -#define STM32_RTC_HAS_PERIODIC_WAKEUPS TRUE -#define STM32_RTC_NUM_ALARMS 2 -#define STM32_RTC_STORAGE_SIZE 128 -#define STM32_RTC_TAMP_STAMP_HANDLER Vector48 -#define STM32_RTC_WKUP_HANDLER Vector4C -#define STM32_RTC_ALARM_HANDLER VectorE4 -#define STM32_RTC_TAMP_STAMP_NUMBER 2 -#define STM32_RTC_WKUP_NUMBER 3 -#define STM32_RTC_ALARM_NUMBER 41 -#define STM32_RTC_ALARM_EXTI 17 -#define STM32_RTC_TAMP_STAMP_EXTI 19 -#define STM32_RTC_WKUP_EXTI 20 -#define STM32_RTC_IRQ_ENABLE() do { \ - nvicEnableVector(STM32_RTC_TAMP_STAMP_NUMBER, STM32_IRQ_EXTI19_PRIORITY); \ - nvicEnableVector(STM32_RTC_WKUP_NUMBER, STM32_IRQ_EXTI20_PRIORITY); \ - nvicEnableVector(STM32_RTC_ALARM_NUMBER, STM32_IRQ_EXTI18_PRIORITY); \ -} while (false) - - /* Enabling RTC-related EXTI lines.*/ -#define STM32_RTC_ENABLE_ALL_EXTI() do { \ - extiEnableGroup1(EXTI_MASK1(STM32_RTC_ALARM_EXTI) | \ - EXTI_MASK1(STM32_RTC_TAMP_STAMP_EXTI) | \ - EXTI_MASK1(STM32_RTC_WKUP_EXTI), \ - EXTI_MODE_RISING_EDGE | EXTI_MODE_ACTION_INTERRUPT); \ -} while (false) - -/* Clearing EXTI interrupts. */ -#define STM32_RTC_CLEAR_ALL_EXTI() do { \ - extiClearGroup1(EXTI_MASK1(STM32_RTC_ALARM_EXTI) | \ - EXTI_MASK1(STM32_RTC_TAMP_STAMP_EXTI) | \ - EXTI_MASK1(STM32_RTC_WKUP_EXTI)); \ -} while (false) - -/* Masks used to preserve state of RTC and TAMP register reserved bits. */ -#define STM32_RTC_CR_MASK 0xE7FFFF7F -#define STM32_RTC_PRER_MASK 0x007F7FFF -#define STM32_TAMP_CR1_MASK 0x003C0007 -#define STM32_TAMP_CR2_MASK 0x07070007 -#define STM32_TAMP_FLTCR_MASK 0x000000FF -#define STM32_TAMP_IER_MASK 0x003C0007 - -#if defined(STM32G441xx) || defined(STM32G483xx) || defined(STM32G484xx) || \ - defined(__DOXYGEN__) -#define STM32_HAS_HASH1 TRUE -#define STM32_HAS_CRYP1 TRUE -#else -#define STM32_HAS_HASH1 FALSE -#define STM32_HAS_CRYP1 FALSE -#endif - /* RCC attributes.*/ #define STM32_RCC_HAS_LSI TRUE #define STM32_RCC_HAS_CSI TRUE @@ -120,67 +65,25 @@ #define STM32_RCC_PLL3_HAS_R TRUE /*===========================================================================*/ -/* STM32G473xx, STM32G4843xx, STM32G474xx, STM32G484xx. */ +/* STM32H562xx, STM32H563xx, STM32H573xx. */ /*===========================================================================*/ -#if defined(STM32G473xx) || defined(STM32G483xx) || \ - defined(STM32G474xx) || defined(STM32G484xx) || \ - defined(__DOXYGEN__) +#if defined(STM32H562xx) || defined(STM32H563xx) || \ + defined(STM32H573xx) || defined(__DOXYGEN__) /* ADC attributes.*/ #define STM32_HAS_ADC1 TRUE -#define STM32_HAS_ADC2 TRUE -#define STM32_HAS_ADC3 TRUE -#define STM32_HAS_ADC4 TRUE -#define STM32_HAS_ADC5 TRUE - -/* CAN attributes.*/ -#define STM32_HAS_FDCAN1 TRUE -#define STM32_HAS_FDCAN2 TRUE -#define STM32_HAS_FDCAN3 TRUE -#define STM32_FDCAN_FLS_NBR 28U -#define STM32_FDCAN_FLE_NBR 8U -#define STM32_FDCAN_RF0_NBR 3U -#define STM32_FDCAN_RF1_NBR 3U -#define STM32_FDCAN_RB_NBR 0U -#define STM32_FDCAN_TEF_NBR 3U -#define STM32_FDCAN_TB_NBR 3U -#define STM32_FDCAN_TM_NBR 0U - -/* DAC attributes.*/ -#define STM32_HAS_DAC1_CH1 TRUE -#define STM32_HAS_DAC1_CH2 TRUE -#define STM32_HAS_DAC2_CH1 TRUE -#define STM32_HAS_DAC2_CH2 FALSE -#define STM32_HAS_DAC3_CH1 TRUE -#define STM32_HAS_DAC3_CH2 TRUE -#define STM32_HAS_DAC4_CH1 TRUE -#define STM32_HAS_DAC4_CH2 TRUE - -/* DMA attributes.*/ -#define STM32_ADVANCED_DMA TRUE -#define STM32_DMA_SUPPORTS_DMAMUX TRUE -#define STM32_DMA_SUPPORTS_CSELR FALSE -#define STM32_DMA1_NUM_CHANNELS 8 -#define STM32_DMA2_NUM_CHANNELS 8 - -/* ETH attributes.*/ -#define STM32_HAS_ETH FALSE +#define STM32_HAS_ADC2 FALSE +#define STM32_HAS_ADC3 FALSE +#define STM32_HAS_ADC4 FALSE +#define STM32_HAS_ADC5 FALSE /* EXTI attributes.*/ -#define STM32_EXTI_HAS_CR FALSE -#define STM32_EXTI_SEPARATE_RF FALSE -#define STM32_EXTI_NUM_LINES 44 -#define STM32_EXTI_IMR1_MASK 0x1F840000U -#define STM32_EXTI_IMR2_MASK 0xFFFFFF3CU - -/* Flash attributes.*/ -#define STM32_FLASH_NUMBER_OF_BANKS 2 -#define STM32_FLASH_SECTOR_SIZE 2048U -#define STM32_FLASH_LINE_SIZE 8U -#if !defined(STM32_FLASH_SECTORS_PER_BANK) || defined(__DOXYGEN__) -#define STM32_FLASH_SECTORS_PER_BANK 128 /* Maximum, can be redefined.*/ -#endif +#define STM32_EXTI_HAS_CR TRUE +#define STM32_EXTI_SEPARATE_RF TRUE +#define STM32_EXTI_NUM_LINES 58 +#define STM32_EXTI_IMR1_MASK 0xFFFE0000U +#define STM32_EXTI_IMR2_MASK 0x03DBBFFFU /* GPIO attributes.*/ #define STM32_HAS_GPIOA TRUE @@ -190,8 +93,8 @@ #define STM32_HAS_GPIOE TRUE #define STM32_HAS_GPIOF TRUE #define STM32_HAS_GPIOG TRUE -#define STM32_HAS_GPIOH FALSE -#define STM32_HAS_GPIOI FALSE +#define STM32_HAS_GPIOH TRUE +#define STM32_HAS_GPIOI TRUE #define STM32_HAS_GPIOJ FALSE #define STM32_HAS_GPIOK FALSE #define STM32_GPIO_EN_MASK (RCC_AHB2ENR_GPIOAEN | \ @@ -200,28 +103,17 @@ RCC_AHB2ENR_GPIODEN | \ RCC_AHB2ENR_GPIOEEN | \ RCC_AHB2ENR_GPIOFEN | \ - RCC_AHB2ENR_GPIOGEN) - -/* I2C attributes.*/ -#define STM32_HAS_I2C1 TRUE -#define STM32_HAS_I2C2 TRUE -#define STM32_HAS_I2C3 TRUE -#define STM32_HAS_I2C4 TRUE - -/* OCTOSPI attributes.*/ -#define STM32_HAS_OCTOSPI1 FALSE -#define STM32_HAS_OCTOSPI2 FALSE - -/* QUADSPI attributes.*/ -#define STM32_HAS_QUADSPI1 TRUE + RCC_AHB2ENR_GPIOGEN | \ + RCC_AHB2ENR_GPIOHEN | \ + RCC_AHB2ENR_GPIOIEN) /* SDMMC attributes.*/ -#define STM32_HAS_SDMMC1 FALSE -#define STM32_HAS_SDMMC2 FALSE +#define STM32_HAS_SDMMC1 TRUE +#define STM32_HAS_SDMMC2 TRUE /* SPI attributes.*/ #define STM32_HAS_SPI1 TRUE -#define STM32_SPI1_SUPPORTS_I2S FALSE +#define STM32_SPI1_SUPPORTS_I2S TRUE #define STM32_HAS_SPI2 TRUE #define STM32_SPI2_SUPPORTS_I2S TRUE @@ -232,8 +124,11 @@ #define STM32_HAS_SPI4 TRUE #define STM32_SPI4_SUPPORTS_I2S FALSE -#define STM32_HAS_SPI5 FALSE -#define STM32_HAS_SPI6 FALSE +#define STM32_HAS_SPI5 TRUE +#define STM32_SPI5_SUPPORTS_I2S FALSE + +#define STM32_HAS_SPI6 TRUE +#define STM32_SPI5_SUPPORTS_I2S FALSE /* TIM attributes.*/ #define STM32_TIM_MAX_CHANNELS 6 @@ -270,224 +165,17 @@ #define STM32_TIM8_IS_32BITS FALSE #define STM32_TIM8_CHANNELS 6 -#define STM32_HAS_TIM15 TRUE -#define STM32_TIM15_IS_32BITS FALSE -#define STM32_TIM15_CHANNELS 2 +#define STM32_HAS_TIM12 TRUE +#define STM32_TIM12_IS_32BITS FALSE +#define STM32_TIM12_CHANNELS 2 -#define STM32_HAS_TIM16 TRUE -#define STM32_TIM16_IS_32BITS FALSE -#define STM32_TIM16_CHANNELS 1 +#define STM32_HAS_TIM13 TRUE +#define STM32_TIM13_IS_32BITS FALSE +#define STM32_TIM13_CHANNELS 1 -#define STM32_HAS_TIM17 TRUE -#define STM32_TIM17_IS_32BITS FALSE -#define STM32_TIM17_CHANNELS 1 - -#define STM32_HAS_TIM20 TRUE -#define STM32_TIM20_IS_32BITS FALSE -#define STM32_TIM20_CHANNELS 6 - -#define STM32_HAS_TIM9 FALSE -#define STM32_HAS_TIM10 FALSE -#define STM32_HAS_TIM11 FALSE -#define STM32_HAS_TIM12 FALSE -#define STM32_HAS_TIM13 FALSE -#define STM32_HAS_TIM14 FALSE -#define STM32_HAS_TIM18 FALSE -#define STM32_HAS_TIM19 FALSE -#define STM32_HAS_TIM21 FALSE -#define STM32_HAS_TIM22 FALSE - -/* USART attributes.*/ -#define STM32_HAS_USART1 TRUE -#define STM32_HAS_USART2 TRUE -#define STM32_HAS_USART3 TRUE -#define STM32_HAS_UART4 TRUE -#define STM32_HAS_UART5 TRUE -#define STM32_HAS_LPUART1 TRUE -#define STM32_HAS_USART6 FALSE -#define STM32_HAS_UART7 FALSE -#define STM32_HAS_UART8 FALSE - -/* OTG/USB attributes.*/ -#define STM32_HAS_OTG1 FALSE -#define STM32_HAS_OTG2 FALSE - -#define STM32_HAS_USB TRUE -#define STM32_USB_ACCESS_SCHEME_2x16 TRUE -#define STM32_USB_PMA_SIZE 1024 -#define STM32_USB_HAS_BCDR TRUE - -/* IWDG attributes.*/ -#define STM32_HAS_IWDG TRUE -#define STM32_IWDG_IS_WINDOWED TRUE - -/* LTDC attributes.*/ -#define STM32_HAS_LTDC FALSE - -/* DMA2D attributes.*/ -#define STM32_HAS_DMA2D FALSE - -/* FSMC attributes.*/ -#define STM32_HAS_FSMC FALSE - -/* CRC attributes.*/ -#define STM32_HAS_CRC TRUE -#define STM32_CRC_PROGRAMMABLE TRUE - -/* DCMI attributes.*/ -#define STM32_HAS_DCMI FALSE - -#endif /* defined(STM32G474xx) || defined(STM32G484xx) */ - -/*===========================================================================*/ -/* STM32G491xx. */ -/*===========================================================================*/ - -#if defined(STM32G491xx) || \ - defined(__DOXYGEN__) - -/* ADC attributes.*/ -#define STM32_HAS_ADC1 TRUE -#define STM32_HAS_ADC2 TRUE -#define STM32_HAS_ADC3 TRUE -#define STM32_HAS_ADC4 FALSE -#define STM32_HAS_ADC5 FALSE - -/* CAN attributes.*/ -#define STM32_HAS_FDCAN1 TRUE -#define STM32_HAS_FDCAN2 TRUE -#define STM32_HAS_FDCAN3 FALSE -#define STM32_FDCAN_FLS_NBR 28U -#define STM32_FDCAN_FLE_NBR 8U -#define STM32_FDCAN_RF0_NBR 3U -#define STM32_FDCAN_RF1_NBR 3U -#define STM32_FDCAN_RB_NBR 0U -#define STM32_FDCAN_TEF_NBR 3U -#define STM32_FDCAN_TB_NBR 3U -#define STM32_FDCAN_TM_NBR 0U - -/* DAC attributes.*/ -#define STM32_HAS_DAC1_CH1 TRUE -#define STM32_HAS_DAC1_CH2 TRUE -#define STM32_HAS_DAC2_CH1 FALSE -#define STM32_HAS_DAC2_CH2 FALSE -#define STM32_HAS_DAC3_CH1 TRUE -#define STM32_HAS_DAC3_CH2 TRUE -#define STM32_HAS_DAC4_CH1 FALSE -#define STM32_HAS_DAC4_CH2 FALSE - -/* DMA attributes.*/ -#define STM32_ADVANCED_DMA TRUE -#define STM32_DMA_SUPPORTS_DMAMUX TRUE -#define STM32_DMA_SUPPORTS_CSELR FALSE -#define STM32_DMA1_NUM_CHANNELS 8 -#define STM32_DMA2_NUM_CHANNELS 8 - -/* ETH attributes.*/ -#define STM32_HAS_ETH FALSE - -/* EXTI attributes.*/ -#define STM32_EXTI_HAS_CR FALSE -#define STM32_EXTI_SEPARATE_RF FALSE -#define STM32_EXTI_NUM_LINES 44 -#define STM32_EXTI_IMR1_MASK 0x1F840000U -#define STM32_EXTI_IMR2_MASK 0xFFFFFF3CU - -/* Flash attributes.*/ -#define STM32_FLASH_NUMBER_OF_BANKS 2 -#define STM32_FLASH_SECTOR_SIZE 2048U -#define STM32_FLASH_LINE_SIZE 8U -#if !defined(STM32_FLASH_SECTORS_PER_BANK) || defined(__DOXYGEN__) -#define STM32_FLASH_SECTORS_PER_BANK 128 /* Maximum, can be redefined.*/ -#endif - -/* GPIO attributes.*/ -#define STM32_HAS_GPIOA TRUE -#define STM32_HAS_GPIOB TRUE -#define STM32_HAS_GPIOC TRUE -#define STM32_HAS_GPIOD TRUE -#define STM32_HAS_GPIOE TRUE -#define STM32_HAS_GPIOF TRUE -#define STM32_HAS_GPIOG TRUE -#define STM32_HAS_GPIOH FALSE -#define STM32_HAS_GPIOI FALSE -#define STM32_HAS_GPIOJ FALSE -#define STM32_HAS_GPIOK FALSE -#define STM32_GPIO_EN_MASK (RCC_AHB2ENR_GPIOAEN | \ - RCC_AHB2ENR_GPIOBEN | \ - RCC_AHB2ENR_GPIOCEN | \ - RCC_AHB2ENR_GPIODEN | \ - RCC_AHB2ENR_GPIOEEN | \ - RCC_AHB2ENR_GPIOFEN | \ - RCC_AHB2ENR_GPIOGEN) - -/* I2C attributes.*/ -#define STM32_HAS_I2C1 TRUE -#define STM32_HAS_I2C2 TRUE -#define STM32_HAS_I2C3 TRUE -#define STM32_HAS_I2C4 FALSE - -/* OCTOSPI attributes.*/ -#define STM32_HAS_OCTOSPI1 FALSE -#define STM32_HAS_OCTOSPI2 FALSE - -/* QUADSPI attributes.*/ -#define STM32_HAS_QUADSPI1 TRUE - -/* SDMMC attributes.*/ -#define STM32_HAS_SDMMC1 FALSE -#define STM32_HAS_SDMMC2 FALSE - -/* SPI attributes.*/ -#define STM32_HAS_SPI1 TRUE -#define STM32_SPI1_SUPPORTS_I2S FALSE - -#define STM32_HAS_SPI2 TRUE -#define STM32_SPI2_SUPPORTS_I2S TRUE - -#define STM32_HAS_SPI3 TRUE -#define STM32_SPI3_SUPPORTS_I2S TRUE - -#define STM32_HAS_SPI4 FALSE -#define STM32_SPI4_SUPPORTS_I2S FALSE - -#define STM32_HAS_SPI5 FALSE -#define STM32_HAS_SPI6 FALSE - -/* TIM attributes.*/ -#define STM32_TIM_MAX_CHANNELS 6 - -#define STM32_HAS_TIM1 TRUE -#define STM32_TIM1_IS_32BITS FALSE -#define STM32_TIM1_CHANNELS 4 - -#define STM32_HAS_TIM2 TRUE -#define STM32_TIM2_IS_32BITS TRUE -#define STM32_TIM2_CHANNELS 4 - -#define STM32_HAS_TIM3 TRUE -#define STM32_TIM3_IS_32BITS FALSE -#define STM32_TIM3_CHANNELS 4 - -#define STM32_HAS_TIM4 TRUE -#define STM32_TIM4_IS_32BITS FALSE -#define STM32_TIM4_CHANNELS 4 - -#define STM32_HAS_TIM5 FALSE -#define STM32_TIM5_IS_32BITS FALSE -#define STM32_TIM5_CHANNELS 0 - -#define STM32_HAS_TIM6 TRUE -#define STM32_TIM6_IS_32BITS FALSE -#define STM32_TIM6_CHANNELS 0 - -#define STM32_HAS_TIM7 TRUE -#define STM32_TIM7_IS_32BITS FALSE -#define STM32_TIM7_CHANNELS 0 - -#define STM32_HAS_TIM8 TRUE -#define STM32_TIM8_IS_32BITS FALSE -#define STM32_TIM8_CHANNELS 4 +#define STM32_HAS_TIM14 TRUE +#define STM32_TIM14_IS_32BITS FALSE +#define STM32_TIM14_CHANNELS 1 #define STM32_HAS_TIM15 TRUE #define STM32_TIM15_IS_32BITS FALSE @@ -501,226 +189,9 @@ #define STM32_TIM17_IS_32BITS FALSE #define STM32_TIM17_CHANNELS 1 -#define STM32_HAS_TIM20 TRUE -#define STM32_TIM20_IS_32BITS FALSE -#define STM32_TIM20_CHANNELS 4 - #define STM32_HAS_TIM9 FALSE #define STM32_HAS_TIM10 FALSE #define STM32_HAS_TIM11 FALSE -#define STM32_HAS_TIM12 FALSE -#define STM32_HAS_TIM13 FALSE -#define STM32_HAS_TIM14 FALSE -#define STM32_HAS_TIM18 FALSE -#define STM32_HAS_TIM19 FALSE -#define STM32_HAS_TIM21 FALSE -#define STM32_HAS_TIM22 FALSE - -/* USART attributes.*/ -#define STM32_HAS_USART1 TRUE -#define STM32_HAS_USART2 TRUE -#define STM32_HAS_USART3 TRUE -#define STM32_HAS_UART4 TRUE -#define STM32_HAS_UART5 TRUE -#define STM32_HAS_LPUART1 TRUE -#define STM32_HAS_USART6 FALSE -#define STM32_HAS_UART7 FALSE -#define STM32_HAS_UART8 FALSE - -/* OTG/USB attributes.*/ -#define STM32_HAS_OTG1 FALSE -#define STM32_HAS_OTG2 FALSE - -#define STM32_HAS_USB TRUE -#define STM32_USB_ACCESS_SCHEME_2x16 TRUE -#define STM32_USB_PMA_SIZE 1024 -#define STM32_USB_HAS_BCDR TRUE - -/* IWDG attributes.*/ -#define STM32_HAS_IWDG TRUE -#define STM32_IWDG_IS_WINDOWED TRUE - -/* LTDC attributes.*/ -#define STM32_HAS_LTDC FALSE - -/* DMA2D attributes.*/ -#define STM32_HAS_DMA2D FALSE - -/* FSMC attributes.*/ -#define STM32_HAS_FSMC FALSE - -/* CRC attributes.*/ -#define STM32_HAS_CRC TRUE -#define STM32_CRC_PROGRAMMABLE TRUE - -/* DCMI attributes.*/ -#define STM32_HAS_DCMI FALSE - -#endif /* defined(STM32G491xx) */ - -/*===========================================================================*/ -/* STM32G431xx, STM32G441xx, STM32G471xx. */ -/*===========================================================================*/ - -#if defined(STM32G431xx) || defined(STM32G441xx) || \ - defined(__DOXYGEN__) - -/* ADC attributes.*/ -#define STM32_HAS_ADC1 TRUE -#define STM32_HAS_ADC2 TRUE -#define STM32_HAS_ADC3 FALSE -#define STM32_HAS_ADC4 FALSE -#define STM32_HAS_ADC5 FALSE - -/* CAN attributes.*/ -#define STM32_HAS_FDCAN1 TRUE -#define STM32_HAS_FDCAN2 FALSE -#define STM32_HAS_FDCAN3 FALSE -#define STM32_FDCAN_FLS_NBR 28U -#define STM32_FDCAN_FLE_NBR 8U -#define STM32_FDCAN_RF0_NBR 3U -#define STM32_FDCAN_RF1_NBR 3U -#define STM32_FDCAN_RB_NBR 0U -#define STM32_FDCAN_TEF_NBR 3U -#define STM32_FDCAN_TB_NBR 3U -#define STM32_FDCAN_TM_NBR 0U - -/* DAC attributes.*/ -#define STM32_HAS_DAC1_CH1 TRUE -#define STM32_HAS_DAC1_CH2 TRUE -#define STM32_HAS_DAC2_CH1 FALSE -#define STM32_HAS_DAC2_CH2 FALSE -#define STM32_HAS_DAC3_CH1 TRUE -#define STM32_HAS_DAC3_CH2 TRUE -#define STM32_HAS_DAC4_CH1 FALSE -#define STM32_HAS_DAC4_CH2 FALSE - -/* DMA attributes.*/ -#define STM32_ADVANCED_DMA TRUE -#define STM32_DMA_SUPPORTS_DMAMUX TRUE -#define STM32_DMA_SUPPORTS_CSELR FALSE -#define STM32_DMA1_NUM_CHANNELS 6 -#define STM32_DMA2_NUM_CHANNELS 6 - -/* ETH attributes.*/ -#define STM32_HAS_ETH FALSE - -/* EXTI attributes.*/ -#define STM32_EXTI_HAS_CR FALSE -#define STM32_EXTI_SEPARATE_RF FALSE -#define STM32_EXTI_NUM_LINES 44 -#define STM32_EXTI_IMR1_MASK 0x1F840000U -#define STM32_EXTI_IMR2_MASK 0xFFFFFF3CU - -/* Flash attributes.*/ -#define STM32_FLASH_NUMBER_OF_BANKS 2 -#define STM32_FLASH_SECTOR_SIZE 2048U -#define STM32_FLASH_LINE_SIZE 8U -#if !defined(STM32_FLASH_SECTORS_PER_BANK) || defined(__DOXYGEN__) -#define STM32_FLASH_SECTORS_PER_BANK 128 /* Maximum, can be redefined.*/ -#endif - -/* GPIO attributes.*/ -#define STM32_HAS_GPIOA TRUE -#define STM32_HAS_GPIOB TRUE -#define STM32_HAS_GPIOC TRUE -#define STM32_HAS_GPIOD TRUE -#define STM32_HAS_GPIOE TRUE -#define STM32_HAS_GPIOF TRUE -#define STM32_HAS_GPIOG TRUE -#define STM32_HAS_GPIOH FALSE -#define STM32_HAS_GPIOI FALSE -#define STM32_HAS_GPIOJ FALSE -#define STM32_HAS_GPIOK FALSE -#define STM32_GPIO_EN_MASK (RCC_AHB2ENR_GPIOAEN | \ - RCC_AHB2ENR_GPIOBEN | \ - RCC_AHB2ENR_GPIOCEN | \ - RCC_AHB2ENR_GPIODEN | \ - RCC_AHB2ENR_GPIOEEN | \ - RCC_AHB2ENR_GPIOFEN | \ - RCC_AHB2ENR_GPIOGEN) - -/* I2C attributes.*/ -#define STM32_HAS_I2C1 TRUE -#define STM32_HAS_I2C2 TRUE -#define STM32_HAS_I2C3 TRUE -#define STM32_HAS_I2C4 FALSE - -/* OCTOSPI attributes.*/ -#define STM32_HAS_OCTOSPI1 FALSE -#define STM32_HAS_OCTOSPI2 FALSE - -/* QUADSPI attributes.*/ -#define STM32_HAS_QUADSPI1 FALSE - -/* SDMMC attributes.*/ -#define STM32_HAS_SDMMC1 FALSE -#define STM32_HAS_SDMMC2 FALSE - -/* SPI attributes.*/ -#define STM32_HAS_SPI1 TRUE -#define STM32_SPI1_SUPPORTS_I2S FALSE - -#define STM32_HAS_SPI2 TRUE -#define STM32_SPI2_SUPPORTS_I2S TRUE - -#define STM32_HAS_SPI3 TRUE -#define STM32_SPI3_SUPPORTS_I2S TRUE - -#define STM32_HAS_SPI4 FALSE -#define STM32_HAS_SPI5 FALSE -#define STM32_HAS_SPI6 FALSE - -/* TIM attributes.*/ -#define STM32_TIM_MAX_CHANNELS 6 - -#define STM32_HAS_TIM1 TRUE -#define STM32_TIM1_IS_32BITS FALSE -#define STM32_TIM1_CHANNELS 6 - -#define STM32_HAS_TIM2 TRUE -#define STM32_TIM2_IS_32BITS TRUE -#define STM32_TIM2_CHANNELS 4 - -#define STM32_HAS_TIM3 TRUE -#define STM32_TIM3_IS_32BITS FALSE -#define STM32_TIM3_CHANNELS 4 - -#define STM32_HAS_TIM4 TRUE -#define STM32_TIM4_IS_32BITS FALSE -#define STM32_TIM4_CHANNELS 4 - -#define STM32_HAS_TIM6 TRUE -#define STM32_TIM6_IS_32BITS FALSE -#define STM32_TIM6_CHANNELS 0 - -#define STM32_HAS_TIM7 TRUE -#define STM32_TIM7_IS_32BITS FALSE -#define STM32_TIM7_CHANNELS 0 - -#define STM32_HAS_TIM8 TRUE -#define STM32_TIM8_IS_32BITS FALSE -#define STM32_TIM8_CHANNELS 6 - -#define STM32_HAS_TIM15 TRUE -#define STM32_TIM15_IS_32BITS FALSE -#define STM32_TIM15_CHANNELS 2 - -#define STM32_HAS_TIM16 TRUE -#define STM32_TIM16_IS_32BITS FALSE -#define STM32_TIM16_CHANNELS 1 - -#define STM32_HAS_TIM17 TRUE -#define STM32_TIM17_IS_32BITS FALSE -#define STM32_TIM17_CHANNELS 1 - -#define STM32_HAS_TIM5 FALSE -#define STM32_HAS_TIM9 FALSE -#define STM32_HAS_TIM10 FALSE -#define STM32_HAS_TIM11 FALSE -#define STM32_HAS_TIM12 FALSE -#define STM32_HAS_TIM13 FALSE -#define STM32_HAS_TIM14 FALSE #define STM32_HAS_TIM18 FALSE #define STM32_HAS_TIM19 FALSE #define STM32_HAS_TIM20 FALSE @@ -732,42 +203,26 @@ #define STM32_HAS_USART2 TRUE #define STM32_HAS_USART3 TRUE #define STM32_HAS_UART4 TRUE -#define STM32_HAS_UART5 FALSE +#define STM32_HAS_UART5 TRUE +#define STM32_HAS_USART6 TRUE +#define STM32_HAS_UART7 TRUE +#define STM32_HAS_UART8 TRUE +#define STM32_HAS_UART9 TRUE +#define STM32_HAS_USART10 TRUE +#define STM32_HAS_USART11 TRUE +#define STM32_HAS_UART12 TRUE #define STM32_HAS_LPUART1 TRUE -#define STM32_HAS_USART6 FALSE -#define STM32_HAS_UART7 FALSE -#define STM32_HAS_UART8 FALSE - -/* OTG/USB attributes.*/ -#define STM32_HAS_OTG1 FALSE -#define STM32_HAS_OTG2 FALSE #define STM32_HAS_USB TRUE #define STM32_USB_ACCESS_SCHEME_2x16 TRUE -#define STM32_USB_PMA_SIZE 1024 +#define STM32_USB_PMA_SIZE 2048 #define STM32_USB_HAS_BCDR TRUE /* IWDG attributes.*/ #define STM32_HAS_IWDG TRUE #define STM32_IWDG_IS_WINDOWED TRUE -/* LTDC attributes.*/ -#define STM32_HAS_LTDC FALSE - -/* DMA2D attributes.*/ -#define STM32_HAS_DMA2D FALSE - -/* FSMC attributes.*/ -#define STM32_HAS_FSMC FALSE - -/* CRC attributes.*/ -#define STM32_HAS_CRC TRUE -#define STM32_CRC_PROGRAMMABLE TRUE - -/* DCMI attributes.*/ -#define STM32_HAS_DCMI FALSE - -#endif /* defined(STM32G431xx) || defined(STM32G441xx) */ +#endif /* defined(STM32H562xx) || defined(STM32H563xx) || defined(STM32H573xx) */ /** @} */