More STM32F3xx ADC code, not complete yet.
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@4975 35acf78f-673a-0410-8e92-d51de3d6d3f4
This commit is contained in:
gdisirio
parent
fdfd900d97
commit
cc94e31e38
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@ -303,6 +303,40 @@ void adc_lld_stop_conversion(ADCDriver *adcp) {
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adc_lld_stop_adc(adcp->adc);
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}
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/**
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* @brief Programs the analog watchdog 2.
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* @note This function must be called after starting the driver and
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* before starting a conversion.
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*
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* @param[in] adc pointer to the physical ADC to configure
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* @param[in] low lower limit, as a 12 bits value
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* @param[in] high upper limit, as a 12 bits value
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* @param[in] channels bit mask of guarded channels
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*
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* @api
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*/
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void adcSTM32SetWatchdog2(ADC_TypeDef *adc, uint16_t low, uint16_t high,
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uint32_t channels) {
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}
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/**
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* @brief Programs the analog watchdog 3.
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* @note This function must be called after starting the driver and
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* before starting a conversion.
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*
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* @param[in] adc pointer to the physical ADC to configure
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* @param[in] low lower limit, as a 12 bits value
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* @param[in] high upper limit, as a 12 bits value
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* @param[in] channels bit mask of guarded channels
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*
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* @api
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*/
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void adcSTM32SetWatchdog3(ADC_TypeDef *adc, uint16_t low, uint16_t high,
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uint32_t channels) {
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}
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#endif /* HAL_USE_ADC */
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/** @} */
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@ -35,6 +35,30 @@
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/* Driver constants. */
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/*===========================================================================*/
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/**
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* @name Available analog channels
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* @{
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*/
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#define ADC_CHANNEL_IN1 1 /**< @brief External analog input 1. */
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#define ADC_CHANNEL_IN2 2 /**< @brief External analog input 2. */
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#define ADC_CHANNEL_IN3 3 /**< @brief External analog input 3. */
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#define ADC_CHANNEL_IN4 4 /**< @brief External analog input 4. */
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#define ADC_CHANNEL_IN5 5 /**< @brief External analog input 5. */
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#define ADC_CHANNEL_IN6 6 /**< @brief External analog input 6. */
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#define ADC_CHANNEL_IN7 7 /**< @brief External analog input 7. */
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#define ADC_CHANNEL_IN8 8 /**< @brief External analog input 8. */
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#define ADC_CHANNEL_IN9 9 /**< @brief External analog input 9. */
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#define ADC_CHANNEL_IN10 10 /**< @brief External analog input 10. */
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#define ADC_CHANNEL_IN11 11 /**< @brief External analog input 11. */
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#define ADC_CHANNEL_IN12 12 /**< @brief External analog input 12. */
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#define ADC_CHANNEL_IN13 13 /**< @brief External analog input 13. */
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#define ADC_CHANNEL_IN14 14 /**< @brief External analog input 14. */
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#define ADC_CHANNEL_IN15 15 /**< @brief External analog input 15. */
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#define ADC_CHANNEL_IN16 16 /**< @brief External analog input 16. */
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#define ADC_CHANNEL_IN17 17 /**< @brief External analog input 17. */
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#define ADC_CHANNEL_IN18 18 /**< @brief External analog input 18. */
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/** @} */
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/**
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* @name Sampling rates
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* @{
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@ -66,6 +90,52 @@
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#define ADC_TR(low, high) (((uint32_t)(high) << 16) | (uint32_t)(low))
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/** @} */
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/**
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* @name CFGR register configuration helpers
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* @{
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*/
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#define ADC_CFGR_RES_MASK (3 << 3)
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#define ADC_CFGR_RES_12BITS (0 << 3)
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#define ADC_CFGR_RES_10BITS (1 << 3)
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#define ADC_CFGR_RES_8BITS (2 << 3)
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#define ADC_CFGR_RES_6BITS (3 << 3)
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#define ADC_CFGR_ALIGN_MASK (1 << 5)
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#define ADC_CFGR_ALIGN_RIGHT (0 << 5)
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#define ADC_CFGR_ALIGN_LEFT (1 << 5)
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#define ADC_CFGR_EXTSEL_MASK (15 << 6)
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#define ADC_CFGR_EXTSEL_SRC(n) ((n) << 6)
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#define ADC_CFGR_EXTEN_MASK (3 << 10)
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#define ADC_CFGR_EXTEN_DISABLED (0 << 10)
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#define ADC_CFGR_EXTEN_RISING (1 << 10)
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#define ADC_CFGR_EXTEN_FALLING (2 << 10)
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#define ADC_CFGR_EXTEN_BOTH (3 << 10)
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#define ADC_CFGR_DISCEN_MASK (1 << 16)
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#define ADC_CFGR_DISCEN_DISABLED (0 << 16)
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#define ADC_CFGR_DISCEN_ENABLED (1 << 16)
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#define ADC_CFGR_DISCNUM_MASK (7 << 17)
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#define ADC_CFGR_DISCNUM(n) ((n) << 17)
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#define ADC_CFGR_AWD1_DISABLED 0
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#define ADC_CFGR_AWD1_ALL (1 << 23)
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#define ADC_CFGR_AWD1_SINGLE(n) (((n) << 26) | (1 << 23) | (1 << 22))
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/** @} */
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/**
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* @name ADC clock modes
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* @{
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*/
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#define ADC_CCR_CKMODE_MASK (3 << 16)
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#define ADC_CCR_CKMODE_ADCCK (0 << 16)
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#define ADC_CCR_CKMODE_AHB_DIV1 (1 << 16)
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#define ADC_CCR_CKMODE_AHB_DIV2 (2 << 16)
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#define ADC_CCR_CKMODE_AHB_DIV4 (3 << 16)
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/** @} */
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/*===========================================================================*/
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/* Driver pre-compile time settings. */
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/*===========================================================================*/
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@ -148,6 +218,20 @@
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#if !defined(STM32_ADC_ADC34_DMA_IRQ_PRIORITY) || defined(__DOXYGEN__)
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#define STM32_ADC_ADC34_DMA_IRQ_PRIORITY 2
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#endif
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/**
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* @brief ADC1/ADC2 clock source and mode.
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*/
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#if !defined(STM32_ADC_ADC12_CLOCK_MODE) || defined(__DOXYGEN__)
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#define STM32_ADC_ADC12_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV1
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#endif
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/**
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* @brief ADC3/ADC4 clock source and mode.
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*/
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#if !defined(STM32_ADC_ADC34_CLOCK_MODE) || defined(__DOXYGEN__)
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#define STM32_ADC_ADC34_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV1
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#endif
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/** @} */
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/*===========================================================================*/
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@ -235,6 +319,38 @@
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#error "Invalid DMA priority assigned to ADC34"
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#endif
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#if STM32_ADC_ADC12_CLOCK_MODE == ADC_CCR_CKMODE_ADCCK
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#define STM32_ADC12_CLOCK STM32ADC12CLK
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#elif STM32_ADC_ADC12_CLOCK_MODE == ADC_CCR_CKMODE_AHB_DIV1
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#define STM32_ADC12_CLOCK (STM32_HCLK / 1)
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#elif STM32_ADC_ADC12_CLOCK_MODE == ADC_CCR_CKMODE_AHB_DIV2
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#define STM32_ADC12_CLOCK (STM32_HCLK / 2)
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#elif STM32_ADC_ADC12_CLOCK_MODE == ADC_CCR_CKMODE_AHB_DIV4
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#define STM32_ADC12_CLOCK (STM32_HCLK / 4)
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#else
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#error "invalid clock mode selected for STM32_ADC_ADC12_CLOCK_MODE"
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#endif
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#if STM32_ADC_ADC34_CLOCK_MODE == ADC_CCR_CKMODE_ADCCK
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#define STM32_ADC34_CLOCK STM32ADC34CLK
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#elif STM32_ADC_ADC34_CLOCK_MODE == ADC_CCR_CKMODE_AHB_DIV1
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#define STM32_ADC34_CLOCK (STM32_HCLK / 1)
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#elif STM32_ADC_ADC34_CLOCK_MODE == ADC_CCR_CKMODE_AHB_DIV2
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#define STM32_ADC34_CLOCK (STM32_HCLK / 2)
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#elif STM32_ADC_ADC34_CLOCK_MODE == ADC_CCR_CKMODE_AHB_DIV4
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#define STM32_ADC34_CLOCK (STM32_HCLK / 4)
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#else
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#error "invalid clock mode selected for STM32_ADC_ADC12_CLOCK_MODE"
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#endif
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#if STM32_ADC12_CLOCK > 72000000
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#error "STM32_ADC12_CLOCK exceeding maximum frequency (72000000)"
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#endif
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#if STM32_ADC34_CLOCK > 72000000
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#error "STM32_ADC34_CLOCK exceeding maximum frequency (72000000)"
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#endif
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#if !defined(STM32_DMA_REQUIRED)
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#define STM32_DMA_REQUIRED
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#endif
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@ -317,23 +433,46 @@ typedef struct {
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adcerrorcallback_t error_cb;
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/* End of the mandatory fields.*/
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/**
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* @brief ADC CFGR1 register initialization data.
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* @brief ADC CFGR register initialization data.
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* @note The bits DMAEN, DMACFG, OVRMOD, CONT are enforced internally to the driver.
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*/
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uint32_t cfgr1;
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uint32_t cfgr;
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/**
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* @brief ADC TR register initialization data.
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* @brief ADC TR1 register initialization data.
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*/
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uint32_t tr;
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uint32_t tr1;
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/**
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* @brief ADC SMPR register initialization data.
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* @brief ADC SMPR1 register initialization data.
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* @details In this field must be specified the sample times for channels
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* 0...9.
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*/
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uint32_t smpr;
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uint32_t smpr1;
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/**
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* @brief ADC CHSELR register initialization data.
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* @details The number of bits at logic level one in this register must
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* be equal to the number in the @p num_channels field.
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* @brief ADC SMPR2 register initialization data.
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* @details In this field must be specified the sample times for channels
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* 10...18.
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*/
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uint32_t chselr;
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uint32_t smpr2;
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/**
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* @brief ADC SQR1 register initialization data.
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* @details Conversion group sequence 1...4 + sequence length.
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*/
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uint32_t sqr1;
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/**
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* @brief ADC SQR2 register initialization data.
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* @details Conversion group sequence 5...9.
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*/
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uint32_t sqr2;
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/**
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* @brief ADC SQR3 register initialization data.
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* @details Conversion group sequence 10...15.
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*/
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uint32_t sqr3;
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/**
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* @brief ADC SQR4 register initialization data.
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* @details Conversion group sequence 16...17.
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*/
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uint32_t sqr4;
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} ADCConversionGroup;
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/**
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@ -349,35 +488,35 @@ typedef struct {
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*/
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struct ADCDriver {
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/**
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* @brief Driver state.
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* @brief Driver state.
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*/
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adcstate_t state;
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/**
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* @brief Current configuration data.
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* @brief Current configuration data.
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*/
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const ADCConfig *config;
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/**
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* @brief Current samples buffer pointer or @p NULL.
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* @brief Current samples buffer pointer or @p NULL.
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*/
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adcsample_t *samples;
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/**
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* @brief Current samples buffer depth or @p 0.
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* @brief Current samples buffer depth or @p 0.
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*/
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size_t depth;
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/**
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* @brief Current conversion group pointer or @p NULL.
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* @brief Current conversion group pointer or @p NULL.
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*/
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const ADCConversionGroup *grpp;
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#if ADC_USE_WAIT || defined(__DOXYGEN__)
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/**
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* @brief Waiting thread.
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* @brief Waiting thread.
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*/
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Thread *thread;
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#endif
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#if ADC_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__)
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#if CH_USE_MUTEXES || defined(__DOXYGEN__)
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/**
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* @brief Mutex protecting the peripheral.
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* @brief Mutex protecting the peripheral.
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*/
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Mutex mutex;
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#elif CH_USE_SEMAPHORES
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@ -389,19 +528,19 @@ struct ADCDriver {
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#endif
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/* End of the mandatory fields.*/
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/**
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* @brief Pointer to the master ADCx registers block.
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* @brief Pointer to the master ADCx registers block.
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*/
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ADC_TypeDef *adcm;
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/**
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* @brief Pointer to the slave ADCx registers block.
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* @brief Pointer to the slave ADCx registers block.
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*/
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ADC_TypeDef *adc2;
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ADC_TypeDef *adcs;
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/**
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* @brief Pointer to associated DMA channel.
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* @brief Pointer to associated DMA channel.
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*/
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const stm32_dma_stream_t *dmastp;
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/**
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* @brief DMA mode bit mask.
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* @brief DMA mode bit mask.
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*/
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uint32_t dmamode;
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};
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@ -411,12 +550,59 @@ struct ADCDriver {
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/*===========================================================================*/
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/**
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* @brief Changes the value of the ADC CCR registers.
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* @details Use this function in order to enable or disable the internal
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* analog sources. See the documentation in the STM32F3xx Reference
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* Manual.
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* @name Sequences building helper macros
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* @{
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*/
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#define adcSTM32SetCCR(adc, ccr) ((adc)->CCR = (ccr))
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/**
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* @brief Number of channels in a conversion sequence.
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*/
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#define ADC_SQR1_NUM_CH(n) (((n) - 1) << 0)
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#define ADC_SQR1_SQ1_N(n) ((n) << 6) /**< @brief 1st channel in seq. */
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#define ADC_SQR1_SQ2_N(n) ((n) << 12) /**< @brief 2nd channel in seq. */
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#define ADC_SQR1_SQ3_N(n) ((n) << 18) /**< @brief 3rd channel in seq. */
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#define ADC_SQR1_SQ4_N(n) ((n) << 24) /**< @brief 4th channel in seq. */
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#define ADC_SQR2_SQ5_N(n) ((n) << 0) /**< @brief 5th channel in seq. */
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#define ADC_SQR2_SQ6_N(n) ((n) << 6) /**< @brief 6th channel in seq. */
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#define ADC_SQR2_SQ7_N(n) ((n) << 12) /**< @brief 7th channel in seq. */
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#define ADC_SQR2_SQ8_N(n) ((n) << 18) /**< @brief 8th channel in seq. */
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#define ADC_SQR2_SQ9_N(n) ((n) << 24) /**< @brief 9th channel in seq. */
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#define ADC_SQR3_SQ10_N(n) ((n) << 0) /**< @brief 10th channel in seq.*/
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#define ADC_SQR3_SQ11_N(n) ((n) << 6) /**< @brief 11th channel in seq.*/
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#define ADC_SQR3_SQ12_N(n) ((n) << 12) /**< @brief 12th channel in seq.*/
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#define ADC_SQR3_SQ13_N(n) ((n) << 18) /**< @brief 13th channel in seq.*/
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#define ADC_SQR3_SQ14_N(n) ((n) << 24) /**< @brief 14th channel in seq.*/
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#define ADC_SQR4_SQ15_N(n) ((n) << 0) /**< @brief 15th channel in seq.*/
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#define ADC_SQR4_SQ16_N(n) ((n) << 6) /**< @brief 16th channel in seq.*/
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/** @} */
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/**
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* @name Sampling rate settings helper macros
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* @{
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*/
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#define ADC_SMPR1_SMP_AN1(n) ((n) << 3) /**< @brief AN1 sampling time. */
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#define ADC_SMPR1_SMP_AN2(n) ((n) << 6) /**< @brief AN2 sampling time. */
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#define ADC_SMPR1_SMP_AN3(n) ((n) << 9) /**< @brief AN3 sampling time. */
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#define ADC_SMPR1_SMP_AN4(n) ((n) << 12) /**< @brief AN4 sampling time. */
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#define ADC_SMPR1_SMP_AN5(n) ((n) << 15) /**< @brief AN5 sampling time. */
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#define ADC_SMPR1_SMP_AN6(n) ((n) << 18) /**< @brief AN6 sampling time. */
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#define ADC_SMPR1_SMP_AN7(n) ((n) << 21) /**< @brief AN7 sampling time. */
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#define ADC_SMPR1_SMP_AN8(n) ((n) << 24) /**< @brief AN8 sampling time. */
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#define ADC_SMPR1_SMP_AN9(n) ((n) << 27) /**< @brief AN9 sampling time. */
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#define ADC_SMPR2_SMP_AN10(n) ((n) << 0) /**< @brief AN10 sampling time. */
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#define ADC_SMPR2_SMP_AN11(n) ((n) << 3) /**< @brief AN11 sampling time. */
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#define ADC_SMPR2_SMP_AN12(n) ((n) << 6) /**< @brief AN12 sampling time. */
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#define ADC_SMPR2_SMP_AN13(n) ((n) << 9) /**< @brief AN13 sampling time. */
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#define ADC_SMPR2_SMP_AN14(n) ((n) << 12) /**< @brief AN14 sampling time. */
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#define ADC_SMPR2_SMP_AN15(n) ((n) << 15) /**< @brief AN15 sampling time. */
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#define ADC_SMPR2_SMP_AN16(n) ((n) << 18) /**< @brief AN16 sampling time. */
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#define ADC_SMPR2_SMP_AN17(n) ((n) << 21) /**< @brief AN17 sampling time. */
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#define ADC_SMPR2_SMP_AN18(n) ((n) << 24) /**< @brief AN18 sampling time. */
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/** @} */
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/*===========================================================================*/
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/* External declarations. */
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@ -446,6 +632,8 @@ extern "C" {
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void adc_lld_stop(ADCDriver *adcp);
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void adc_lld_start_conversion(ADCDriver *adcp);
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void adc_lld_stop_conversion(ADCDriver *adcp);
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void adcSTM32SetWatchdog2(uint16_t low, uint16_t high, uint32_t channels);
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void adcSTM32SetWatchdog3(uint16_t low, uint16_t high, uint32_t channels);
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#ifdef __cplusplus
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}
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#endif
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