From ce910a52fce6fc1530dddebdb8459aa90a47022f Mon Sep 17 00:00:00 2001
From: Giovanni Di Sirio <gdisirio@gmail.com>
Date: Sat, 5 Jun 2021 10:35:05 +0000
Subject: [PATCH] New alignment macros used.

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@14492 27425a3e-05d8-49a3-a47f-9c15f0e5edd8
---
 testhal/STM32/multi/ADC/main.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/testhal/STM32/multi/ADC/main.c b/testhal/STM32/multi/ADC/main.c
index 3274ef52f..fd37fa2be 100644
--- a/testhal/STM32/multi/ADC/main.c
+++ b/testhal/STM32/multi/ADC/main.c
@@ -30,12 +30,12 @@
 /* Buffers are allocated with size and address aligned to the cache
    line size.*/
 #if CACHE_LINE_SIZE > 0
-CC_ALIGN(CACHE_LINE_SIZE)
+CC_ALIGN_DATA(CACHE_LINE_SIZE)
 #endif
 adcsample_t samples1[CACHE_SIZE_ALIGN(adcsample_t, ADC_GRP1_NUM_CHANNELS * ADC_GRP1_BUF_DEPTH)];
 
 #if CACHE_LINE_SIZE > 0
-CC_ALIGN(CACHE_LINE_SIZE)
+CC_ALIGN_DATA(CACHE_LINE_SIZE)
 #endif
 adcsample_t samples2[CACHE_SIZE_ALIGN(adcsample_t, ADC_GRP2_NUM_CHANNELS * ADC_GRP2_BUF_DEPTH)];