diff --git a/demos/STM32/RT-STM32H723ZG-NUCLEO144/cfg/mcuconf.h b/demos/STM32/RT-STM32H723ZG-NUCLEO144/cfg/mcuconf.h
index 8cb7ff3ef..9a1c3d3b2 100644
--- a/demos/STM32/RT-STM32H723ZG-NUCLEO144/cfg/mcuconf.h
+++ b/demos/STM32/RT-STM32H723ZG-NUCLEO144/cfg/mcuconf.h
@@ -46,8 +46,7 @@
  * Memory attributes settings.
  */
 #define STM32_NOCACHE_MPU_REGION            MPU_REGION_6
-#define STM32_NOCACHE_SRAM1_SRAM2           FALSE
-#define STM32_NOCACHE_SRAM3                 TRUE
+#define STM32_NOCACHE_SRAM1_SRAM2           TRUE
 
 /*
  * PWR system settings.
@@ -104,11 +103,11 @@
 #define STM32_PLL3_Q_ENABLED                TRUE
 #define STM32_PLL3_R_ENABLED                TRUE
 #define STM32_PLL3_DIVM_VALUE               4
-#define STM32_PLL3_DIVN_VALUE               400
+#define STM32_PLL3_DIVN_VALUE               240
 #define STM32_PLL3_FRACN_VALUE              0
-#define STM32_PLL3_DIVP_VALUE               8
-#define STM32_PLL3_DIVQ_VALUE               8
-#define STM32_PLL3_DIVR_VALUE               8
+#define STM32_PLL3_DIVP_VALUE               10
+#define STM32_PLL3_DIVQ_VALUE               10
+#define STM32_PLL3_DIVR_VALUE               10
 
 /*
  * Core clocks dynamic settings (can be changed at runtime).
@@ -149,7 +148,7 @@
 #define STM32_SAI1SEL                       STM32_SAI1SEL_PLL1_Q_CK
 #define STM32_LPTIM1SEL                     STM32_LPTIM1SEL_PCLK1
 #define STM32_CECSEL                        STM32_CECSEL_LSE_CK
-#define STM32_USBSEL                        STM32_USBSEL_PLL1_Q_CK
+#define STM32_USBSEL                        STM32_USBSEL_PLL3_Q_CK
 #define STM32_I2C1235SEL                    STM32_I2C1235SEL_PCLK1
 #define STM32_RNGSEL                        STM32_RNGSEL_HSI48_CK
 #define STM32_USART16910SEL                 STM32_USART16910SEL_PCLK2
diff --git a/os/hal/ports/STM32/STM32H7xx/hal_lld.c b/os/hal/ports/STM32/STM32H7xx/hal_lld.c
index cd0f357ce..c9e528177 100644
--- a/os/hal/ports/STM32/STM32H7xx/hal_lld.c
+++ b/os/hal/ports/STM32/STM32H7xx/hal_lld.c
@@ -173,6 +173,7 @@ void hal_lld_init(void) {
   {
     uint32_t base, size;
 
+#if defined(HAL_LLD_TYPE1_H)
 #if (STM32_NOCACHE_SRAM1_SRAM2 == TRUE) && (STM32_NOCACHE_SRAM3 == TRUE)
     base = 0x30000000U;
     size = MPU_RASR_SIZE_512K;
@@ -186,6 +187,14 @@ void hal_lld_init(void) {
 #error "invalid constants used in mcuconf.h"
 #endif
 
+#elif defined(HAL_LLD_TYPE2_H)
+#if STM32_NOCACHE_SRAM3 == TRUE
+#error "SRAM3 not present on this device"
+#endif
+    base = 0x30000000U;
+    size = MPU_RASR_SIZE_32K;
+#endif
+
     /* The SRAM2 bank can optionally made a non cache-able area for use by
        DMA engines.*/
     mpuConfigureRegion(STM32_NOCACHE_MPU_REGION,
diff --git a/os/hal/ports/STM32/STM32H7xx/hal_lld.h b/os/hal/ports/STM32/STM32H7xx/hal_lld.h
index e3b506134..506a1e828 100644
--- a/os/hal/ports/STM32/STM32H7xx/hal_lld.h
+++ b/os/hal/ports/STM32/STM32H7xx/hal_lld.h
@@ -86,7 +86,7 @@
  * @brief   Add no-cache attribute to SRAM3.
  */
 #if !defined(STM32_NOCACHE_SRAM3) || defined(__DOXYGEN__)
-#define STM32_NOCACHE_SRAM3                 TRUE
+#define STM32_NOCACHE_SRAM3                 FALSE
 #endif
 /** @} */
 
diff --git a/tools/ftl/processors/conf/mcuconf_stm32h723xx/mcuconf.h.ftl b/tools/ftl/processors/conf/mcuconf_stm32h723xx/mcuconf.h.ftl
index f55eb066c..5c5ceaaec 100644
--- a/tools/ftl/processors/conf/mcuconf_stm32h723xx/mcuconf.h.ftl
+++ b/tools/ftl/processors/conf/mcuconf_stm32h723xx/mcuconf.h.ftl
@@ -29,7 +29,7 @@
 #define MCUCONF_H
 
 /*
- * STM32H7xx drivers configuration.
+ * STM32H723/33/25/35 drivers configuration.
  * The following settings override the default settings present in
  * the various device driver implementation headers.
  * Note that the settings for each driver only have effect if the whole
@@ -57,8 +57,7 @@
  * Memory attributes settings.
  */
 #define STM32_NOCACHE_MPU_REGION            ${doc.STM32_NOCACHE_MPU_REGION!"MPU_REGION_6"}
-#define STM32_NOCACHE_SRAM1_SRAM2           ${doc.STM32_NOCACHE_SRAM1_SRAM2!"FALSE"}
-#define STM32_NOCACHE_SRAM3                 ${doc.STM32_NOCACHE_SRAM3!"TRUE"}
+#define STM32_NOCACHE_SRAM1_SRAM2           ${doc.STM32_NOCACHE_SRAM1_SRAM2!"TRUE"}
 
 /*
  * PWR system settings.
@@ -115,11 +114,11 @@
 #define STM32_PLL3_Q_ENABLED                ${doc.STM32_PLL3_Q_ENABLED!"TRUE"}
 #define STM32_PLL3_R_ENABLED                ${doc.STM32_PLL3_R_ENABLED!"TRUE"}
 #define STM32_PLL3_DIVM_VALUE               ${doc.STM32_PLL3_DIVM_VALUE!"4"}
-#define STM32_PLL3_DIVN_VALUE               ${doc.STM32_PLL3_DIVN_VALUE!"400"}
+#define STM32_PLL3_DIVN_VALUE               ${doc.STM32_PLL3_DIVN_VALUE!"240"}
 #define STM32_PLL3_FRACN_VALUE              ${doc.STM32_PLL3_FRACN_VALUE!"0"}
-#define STM32_PLL3_DIVP_VALUE               ${doc.STM32_PLL3_DIVP_VALUE!"8"}
-#define STM32_PLL3_DIVQ_VALUE               ${doc.STM32_PLL3_DIVQ_VALUE!"8"}
-#define STM32_PLL3_DIVR_VALUE               ${doc.STM32_PLL3_DIVR_VALUE!"8"}
+#define STM32_PLL3_DIVP_VALUE               ${doc.STM32_PLL3_DIVP_VALUE!"10"}
+#define STM32_PLL3_DIVQ_VALUE               ${doc.STM32_PLL3_DIVQ_VALUE!"10"}
+#define STM32_PLL3_DIVR_VALUE               ${doc.STM32_PLL3_DIVR_VALUE!"10"}
 
 /*
  * Core clocks dynamic settings (can be changed at runtime).
@@ -160,7 +159,7 @@
 #define STM32_SAI1SEL                       ${doc.STM32_SAI1SEL!"STM32_SAI1SEL_PLL1_Q_CK"}
 #define STM32_LPTIM1SEL                     ${doc.STM32_LPTIM1SEL!"STM32_LPTIM1SEL_PCLK1"}
 #define STM32_CECSEL                        ${doc.STM32_CECSEL!"STM32_CECSEL_LSE_CK"}
-#define STM32_USBSEL                        ${doc.STM32_USBSEL!"STM32_USBSEL_PLL1_Q_CK"}
+#define STM32_USBSEL                        ${doc.STM32_USBSEL!"STM32_USBSEL_PLL3_Q_CK"}
 #define STM32_I2C1235SEL                    ${doc.STM32_I2C1235SEL!"STM32_I2C1235SEL_PCLK1"}
 #define STM32_RNGSEL                        ${doc.STM32_RNGSEL!"STM32_RNGSEL_HSI48_CK"}
 #define STM32_USART16910SEL                 ${doc.STM32_USART16910SEL!"STM32_USART16910SEL_PCLK2"}