diff --git a/os/hal/ports/STM32/LLD/RCCv1/stm32_ahb.inc b/os/hal/ports/STM32/LLD/RCCv1/stm32_ahb.inc index 7cf2b5c30..1236dfa69 100644 --- a/os/hal/ports/STM32/LLD/RCCv1/stm32_ahb.inc +++ b/os/hal/ports/STM32/LLD/RCCv1/stm32_ahb.inc @@ -31,14 +31,15 @@ * @{ */ #if defined(RCC_CFGR_HPRE_Pos) -#define STM32_HPRE_MASK (15U << RCC_CFGR_HPRE_Pos) -#define STM32_HPRE_FIELD(n) ((n) << RCC_CFGR_HPRE_Pos) +#define STM32_HPRE_POS RCC_CFGR_HPRE_Pos +#define STM32_HPRE_MASK RCC_CFGR_HPRE_Msk #elif defined(RCC_CFGR2_HPRE_Pos) -#define STM32_HPRE_MASK (15U << RCC_CFGR2_HPRE_Pos) -#define STM32_HPRE_FIELD(n) ((n) << RCC_CFGR2_HPRE_Pos) +#define STM32_HPRE_POS RCC_CFGR2_HPRE_Pos +#define STM32_HPRE_MASK RCC_CFGR2_HPRE_Msk #else #error "unknown register name" #endif +#define STM32_HPRE_FIELD(n) ((n) << STM32_HPRE_POS) #define STM32_HPRE_DIV1 STM32_HPRE_FIELD(0U) #define STM32_HPRE_DIV2 STM32_HPRE_FIELD(8U) #define STM32_HPRE_DIV4 STM32_HPRE_FIELD(9U) diff --git a/os/hal/ports/STM32/LLD/RCCv1/stm32_pll1.inc b/os/hal/ports/STM32/LLD/RCCv1/stm32_pll1.inc index b58763e7e..e05370c7d 100644 --- a/os/hal/ports/STM32/LLD/RCCv1/stm32_pll1.inc +++ b/os/hal/ports/STM32/LLD/RCCv1/stm32_pll1.inc @@ -407,11 +407,21 @@ /* Driver local functions. */ /*===========================================================================*/ -__STATIC_INLINE bool pll1_not_locked(void) { +__STATIC_INLINE void pll1_enable(void) { - return (bool)((RCC->CR & RCC_CR_PLL1RDY) == 0U); + RCC->CR |= RCC_CR_PLL1ON; } + __STATIC_INLINE void pll1_disable(void) { + + RCC->CR &= ~RCC_CR_PLL1ON; + } + + __STATIC_INLINE bool pll1_not_locked(void) { + + return (bool)((RCC->CR & RCC_CR_PLL1RDY) == 0U); + } + __STATIC_INLINE void pll1_wait_lock(void) { while (pll1_not_locked()) { @@ -421,16 +431,13 @@ __STATIC_INLINE void pll1_wait_lock(void) { #endif /* STM32_RCC_HAS_PLL1 */ -__STATIC_INLINE void pll1_activate(uint32_t cfgr, uint32_t divr, uint32_t fracr) { +__STATIC_INLINE void pll1_setup(uint32_t cfgr, uint32_t divr, uint32_t fracr) { /* PLL1 activation.*/ RCC->PLL1CFGR = cfgr & ~STM32_PLLFRACEN_MASK; RCC->PLL1DIVR = divr; RCC->PLL1FRACR = fracr; - RCC->PLL1CFGR = cfgr | STM32_PLLFRACEN_MASK; - RCC->CR |= RCC_CR_PLL1ON; - - pll1_wait_lock(); + RCC->PLL1CFGR = cfgr; } __STATIC_INLINE void pll1_init(void) { @@ -438,13 +445,14 @@ __STATIC_INLINE void pll1_init(void) { #if STM32_RCC_HAS_PLL1 #if STM32_ACTIVATE_PLL1 /* PLL1 activation.*/ - pll1_activate(STM32_PLL1REN | STM32_PLL1QEN | - STM32_PLL1PEN | STM32_PLL1M | - STM32_PLL1RGE | STM32_PLL1VCOSEL | - STM32_PLL1SRC, - STM32_PLL1R | STM32_PLL1Q | - STM32_PLL1P | STM32_PLL1N, - 0U); /* TODO FRACR */ + pll1_setup(STM32_PLL1REN | STM32_PLL1QEN | + STM32_PLL1PEN | STM32_PLL1M | + STM32_PLL1RGE | STM32_PLL1VCOSEL | + STM32_PLL1SRC, + STM32_PLL1R | STM32_PLL1Q | + STM32_PLL1P | STM32_PLL1N, + 0U); /* TODO FRACR */ + pll1_enable(); pll1_wait_lock(); #endif #endif @@ -455,7 +463,7 @@ __STATIC_INLINE void pll1_deinit(void) { #if STM32_RCC_HAS_PLL1 #if STM32_ACTIVATE_PLL1 /* PLL1 de-activation.*/ - RCC->CR &= ~RCC_CR_PLL1ON; + pll1_disable(); #endif #endif } diff --git a/os/hal/ports/STM32/LLD/RCCv1/stm32_pll2.inc b/os/hal/ports/STM32/LLD/RCCv1/stm32_pll2.inc index 05914366b..e3d76740b 100644 --- a/os/hal/ports/STM32/LLD/RCCv1/stm32_pll2.inc +++ b/os/hal/ports/STM32/LLD/RCCv1/stm32_pll2.inc @@ -407,11 +407,21 @@ /* Driver local functions. */ /*===========================================================================*/ -__STATIC_INLINE bool pll2_not_locked(void) { +__STATIC_INLINE void pll2_enable(void) { - return (bool)((RCC->CR & RCC_CR_PLL2RDY) == 0U); + RCC->CR |= RCC_CR_PLL2ON; } + __STATIC_INLINE void pll2_disable(void) { + + RCC->CR &= ~RCC_CR_PLL2ON; + } + + __STATIC_INLINE bool pll2_not_locked(void) { + + return (bool)((RCC->CR & RCC_CR_PLL2RDY) == 0U); + } + __STATIC_INLINE void pll2_wait_lock(void) { while (pll2_not_locked()) { @@ -421,16 +431,13 @@ __STATIC_INLINE void pll2_wait_lock(void) { #endif /* STM32_RCC_HAS_PLL2 */ -__STATIC_INLINE void pll2_activate(uint32_t cfgr, uint32_t divr, uint32_t fracr) { +__STATIC_INLINE void pll2_setup(uint32_t cfgr, uint32_t divr, uint32_t fracr) { /* PLL2 activation.*/ RCC->PLL2CFGR = cfgr & ~STM32_PLLFRACEN_MASK; RCC->PLL2DIVR = divr; RCC->PLL2FRACR = fracr; - RCC->PLL2CFGR = cfgr | STM32_PLLFRACEN_MASK; - RCC->CR |= RCC_CR_PLL2ON; - - pll2_wait_lock(); + RCC->PLL2CFGR = cfgr; } __STATIC_INLINE void pll2_init(void) { @@ -438,13 +445,14 @@ __STATIC_INLINE void pll2_init(void) { #if STM32_RCC_HAS_PLL2 #if STM32_ACTIVATE_PLL2 /* PLL2 activation.*/ - pll2_activate(STM32_PLL2REN | STM32_PLL2QEN | - STM32_PLL2PEN | STM32_PLL2M | - STM32_PLL2RGE | STM32_PLL2VCOSEL | - STM32_PLL2SRC, - STM32_PLL2R | STM32_PLL2Q | - STM32_PLL2P | STM32_PLL2N, - 0U); /* TODO FRACR */ + pll2_setup(STM32_PLL2REN | STM32_PLL2QEN | + STM32_PLL2PEN | STM32_PLL2M | + STM32_PLL2RGE | STM32_PLL2VCOSEL | + STM32_PLL2SRC, + STM32_PLL2R | STM32_PLL2Q | + STM32_PLL2P | STM32_PLL2N, + 0U); /* TODO FRACR */ + pll2_enable(); pll2_wait_lock(); #endif #endif @@ -455,7 +463,7 @@ __STATIC_INLINE void pll2_deinit(void) { #if STM32_RCC_HAS_PLL2 #if STM32_ACTIVATE_PLL2 /* PLL2 de-activation.*/ - RCC->CR &= ~RCC_CR_PLL2ON; + pll2_disable(); #endif #endif } diff --git a/os/hal/ports/STM32/LLD/RCCv1/stm32_pll3.inc b/os/hal/ports/STM32/LLD/RCCv1/stm32_pll3.inc index f14abe21e..303d903f4 100644 --- a/os/hal/ports/STM32/LLD/RCCv1/stm32_pll3.inc +++ b/os/hal/ports/STM32/LLD/RCCv1/stm32_pll3.inc @@ -407,11 +407,21 @@ /* Driver local functions. */ /*===========================================================================*/ -__STATIC_INLINE bool pll3_not_locked(void) { +__STATIC_INLINE void pll3_enable(void) { - return (bool)((RCC->CR & RCC_CR_PLL3RDY) == 0U); + RCC->CR |= RCC_CR_PLL3ON; } + __STATIC_INLINE void pll3_disable(void) { + + RCC->CR &= ~RCC_CR_PLL3ON; + } + + __STATIC_INLINE bool pll3_not_locked(void) { + + return (bool)((RCC->CR & RCC_CR_PLL3RDY) == 0U); + } + __STATIC_INLINE void pll3_wait_lock(void) { while (pll3_not_locked()) { @@ -421,16 +431,13 @@ __STATIC_INLINE void pll3_wait_lock(void) { #endif /* STM32_RCC_HAS_PLL3 */ -__STATIC_INLINE void pll3_activate(uint32_t cfgr, uint32_t divr, uint32_t fracr) { +__STATIC_INLINE void pll3_setup(uint32_t cfgr, uint32_t divr, uint32_t fracr) { /* PLL3 activation.*/ RCC->PLL3CFGR = cfgr & ~STM32_PLLFRACEN_MASK; RCC->PLL3DIVR = divr; RCC->PLL3FRACR = fracr; - RCC->PLL3CFGR = cfgr | STM32_PLLFRACEN_MASK; - RCC->CR |= RCC_CR_PLL3ON; - - pll3_wait_lock(); + RCC->PLL3CFGR = cfgr; } __STATIC_INLINE void pll3_init(void) { @@ -438,13 +445,14 @@ __STATIC_INLINE void pll3_init(void) { #if STM32_RCC_HAS_PLL3 #if STM32_ACTIVATE_PLL3 /* PLL3 activation.*/ - pll3_activate(STM32_PLL3REN | STM32_PLL3QEN | - STM32_PLL3PEN | STM32_PLL3M | - STM32_PLL3RGE | STM32_PLL3VCOSEL | - STM32_PLL3SRC, - STM32_PLL3R | STM32_PLL3Q | - STM32_PLL3P | STM32_PLL3N, - 0U); /* TODO FRACR */ + pll3_setup(STM32_PLL3REN | STM32_PLL3QEN | + STM32_PLL3PEN | STM32_PLL3M | + STM32_PLL3RGE | STM32_PLL3VCOSEL | + STM32_PLL3SRC, + STM32_PLL3R | STM32_PLL3Q | + STM32_PLL3P | STM32_PLL3N, + 0U); /* TODO FRACR */ + pll3_enable(); pll3_wait_lock(); #endif #endif @@ -455,7 +463,7 @@ __STATIC_INLINE void pll3_deinit(void) { #if STM32_RCC_HAS_PLL3 #if STM32_ACTIVATE_PLL3 /* PLL3 de-activation.*/ - RCC->CR &= ~RCC_CR_PLL3ON; + pll3_disable(); #endif #endif } diff --git a/os/hal/ports/STM32/STM32H5xx/hal_lld.c b/os/hal/ports/STM32/STM32H5xx/hal_lld.c index d0da7899b..2fb259644 100644 --- a/os/hal/ports/STM32/STM32H5xx/hal_lld.c +++ b/os/hal/ports/STM32/STM32H5xx/hal_lld.c @@ -370,22 +370,22 @@ static bool hal_lld_clock_check_tree(const halclkcfg_t *ccp) { } /* HSE clock.*/ - if ((ccp->rcc_cr & RCC_CR_HSEON) != 0U) { + if ((ccp->rcc_cr & STM32_HSEON) != 0U) { hseclk = STM32_HSECLK; } /* HSI48 clock after divider.*/ - if ((ccp->rcc_cr & RCC_CR_HSI48ON) != 0U) { + if ((ccp->rcc_cr & STM32_HSI48ON) != 0U) { hsi48clk = STM32_HSI48CLK; } /* HSI clock after divider.*/ - if ((ccp->rcc_cr & RCC_CR_HSION) != 0U) { + if ((ccp->rcc_cr & STM32_HSION) != 0U) { hsiclk = STM32_HSI64CLK / (1U << ((ccp->rcc_cr & STM32_HSIDIV_MASK) >> STM32_HSIDIV_POS)); } /* CSI clock.*/ - if ((ccp->rcc_cr & RCC_CR_CSION) != 0U) { + if ((ccp->rcc_cr & STM32_CSION) != 0U) { csiclk = STM32_CSICLK; } @@ -435,7 +435,7 @@ static bool hal_lld_clock_check_tree(const halclkcfg_t *ccp) { } /* PLL1 outputs.*/ - if ((ccp->rcc_cr & RCC_CR_PLL1ON) != 0U) { + if ((ccp->rcc_cr & STM32_PLL1ON) != 0U) { uint32_t mdiv, ndiv; halfreq_t vcoclk; @@ -486,7 +486,7 @@ static bool hal_lld_clock_check_tree(const halclkcfg_t *ccp) { } /* PLL2 outputs.*/ - if ((ccp->rcc_cr & RCC_CR_PLL2ON) != 0U) { + if ((ccp->rcc_cr & STM32_PLL2ON) != 0U) { uint32_t mdiv, ndiv; halfreq_t vcoclk; @@ -534,7 +534,7 @@ static bool hal_lld_clock_check_tree(const halclkcfg_t *ccp) { } /* PLL3 outputs.*/ - if ((ccp->rcc_cr & RCC_CR_PLL3ON) != 0U) { + if ((ccp->rcc_cr & STM32_PLL3ON) != 0U) { uint32_t mdiv, ndiv; halfreq_t vcoclk; @@ -604,10 +604,10 @@ static bool hal_lld_clock_check_tree(const halclkcfg_t *ccp) { } /* HCLK frequency.*/ - hclk = sysclk / hprediv[(ccp->rcc_cfgr2 & RCC_CFGR2_HPRE_Msk) >> RCC_CFGR2_HPRE_Pos]; + hclk = sysclk / hprediv[(ccp->rcc_cfgr2 & STM32_HPRE_MASK) >> STM32_HPRE_POS]; /* PPRE1 frequency.*/ - n = pprediv[(ccp->rcc_cfgr2 & RCC_CFGR2_PPRE1_Msk) >> RCC_CFGR2_PPRE1_Pos]; + n = pprediv[(ccp->rcc_cfgr2 & STM32_PPRE1_MASK) >> STM32_PPRE1_POS]; pclk1 = hclk / n; if (n < 2) { pclk1tim = pclk1; @@ -617,7 +617,7 @@ static bool hal_lld_clock_check_tree(const halclkcfg_t *ccp) { } /* PPRE2 frequency.*/ - n = pprediv[(ccp->rcc_cfgr2 & RCC_CFGR2_PPRE2_Msk) >> RCC_CFGR2_PPRE2_Pos]; + n = pprediv[(ccp->rcc_cfgr2 & STM32_PPRE2_MASK) >> STM32_PPRE2_POS]; pclk2 = hclk / n; if (n < 2) { pclk2tim = pclk2; @@ -627,7 +627,7 @@ static bool hal_lld_clock_check_tree(const halclkcfg_t *ccp) { } /* PPRE3 frequency.*/ - n = pprediv[(ccp->rcc_cfgr2 & RCC_CFGR2_PPRE3_Msk) >> RCC_CFGR2_PPRE3_Pos]; + n = pprediv[(ccp->rcc_cfgr2 & STM32_PPRE3_MASK) >> STM32_PPRE3_POS]; pclk3 = hclk / n; /* MCO1 clock.*/ @@ -729,6 +729,7 @@ static bool hal_lld_clock_check_tree(const halclkcfg_t *ccp) { * @notapi */ static bool hal_lld_clock_raw_switch(const halclkcfg_t *ccp) { + uint32_t cr, mask; #if 0 /* Restoring default PWR settings related clocks and sleep modes.*/ @@ -741,99 +742,82 @@ static bool hal_lld_clock_raw_switch(const halclkcfg_t *ccp) { } #endif + /* Setting flash ACR to the safest value while we play with clocks.*/ + flash_set_acr(FLASH_ACR_LATENCY_5WS); + /* HSI could be not activated, activating it taking care to not disturb other clocks yet, not touching the divider.*/ - RCC->CR |= RCC_CR_HSION; - while ((RCC->CR & RCC_CR_HSIRDY) == 0U) { + RCC->CR |= STM32_HSION; + while ((RCC->CR & STM32_HSIRDY) == 0U) { /* Waiting for HSI activation.*/ } - /* Switching to HSI as clock source as in a post-reset situation.*/ + /* Switching to HSI as clock source as in a post-reset situation. + Resetting up all dividers and MCOs.*/ RCC->CFGR1 = STM32_RCC_CFGR1_RESET; RCC->CFGR2 = STM32_RCC_CFGR2_RESET; while ((RCC->CFGR1 & STM32_SWS_MASK) != STM32_SWS_HSI) { /* Wait until HSI is selected.*/ } - /* Resetting the whole RCC_CR register, shutting down everything but HSI.*/ - RCC->CR = STM32_RCC_CR_RESET; - while ((RCC->CR & RCC_CR_HSIDIVF) == 0U) { + /* Resetting the whole RCC_CR register, basically shutting down everything + except HSI.*/ + cr = STM32_RCC_CR_RESET; + RCC->CR = cr; + while ((RCC->CR & STM32_HSIDIVF) == 0U) { /* Waiting for new HSIDIV setting to be propagated.*/ } /* Resetting flash ACR settings to the default value.*/ flash_set_acr(STM32_FLASH_ACR_RESET); - /* HSE setup, if required, before starting the PLL.*/ - if ((ccp->rcc_cr & RCC_CR_HSEON) != 0U) { - hse_enable(); - } + /* Setting up all clocks while keeping the rest untouched at reset value.*/ + cr |= ccp->rcc_cr & (STM32_HSEON | STM32_HSI48ON | STM32_CSION); + RCC->CR = cr; - /* HSI48 setup, if required, before starting the PLL.*/ - if ((ccp->rcc_cr & RCC_CR_HSI48ON) != 0U) { - hsi48_enable(); - } - - /* CSI setup, if required, before starting the PLL.*/ - if ((ccp->rcc_cr & RCC_CR_CSION) != 0U) { - csi_enable(); + /* Waiting for all enabled clocks to become stable.*/ + mask = (ccp->rcc_cr & (STM32_HSEON | STM32_HSI48ON | STM32_CSION)) << 1; + while ((RCC->CR & mask) != mask) { + /* Waiting.*/ + /* TODO timeout and failure.*/ } /* PLLs setup.*/ - if ((ccp->rcc_cr & RCC_CR_PLL1ON) != 0U) { - pll1_activate(ccp->plls[0].cfgr, ccp->plls[0].divr, 0U); - } - if ((ccp->rcc_cr & RCC_CR_PLL2ON) != 0U) { - pll2_activate(ccp->plls[1].cfgr, ccp->plls[1].divr, 0U); - } - if ((ccp->rcc_cr & RCC_CR_PLL3ON) != 0U) { - pll3_activate(ccp->plls[2].cfgr, ccp->plls[2].divr, 0U); - } + pll1_setup(ccp->plls[0].cfgr, ccp->plls[0].divr, ccp->plls[0].frac); + pll2_setup(ccp->plls[1].cfgr, ccp->plls[1].divr, ccp->plls[1].frac); + pll3_setup(ccp->plls[2].cfgr, ccp->plls[2].divr, ccp->plls[2].frac); - /* PLL activation polling if required.*/ - while (true) { - if (((ccp->rcc_cr & RCC_CR_PLLON) != 0U) && pll_not_locked()) { - continue; - } - break; - } + /* Activating enabled PLLs together.*/ + cr |= ccp->rcc_cr & (STM32_PLL3ON | STM32_PLL2ON | STM32_PLL1ON); + RCC->CR = cr; - /* MCO and bus dividers first.*/ - RCC->CFGR = (RCC->CFGR & RCC_CFGR_SW_Msk) | (ccp->rcc_cfgr & ~RCC_CFGR_SW_Msk); + /* Waiting for all enabled PLLs to become stable.*/ + mask = (ccp->rcc_cr & (STM32_PLL3ON | STM32_PLL2ON | STM32_PLL1ON)) << 1; + while ((RCC->CR & mask) != mask) { + /* Waiting.*/ + /* TODO timeout and failure.*/ + } /* Final flash ACR settings.*/ flash_set_acr(ccp->flash_acr); /* Final PWR modes.*/ - PWR->CR1 = ccp->pwr_cr1; - PWR->CR2 = ccp->pwr_cr2; - PWR->CR5 = ccp->pwr_cr5; - - /* Waiting for the correct regulator state.*/ - if ((ccp->pwr_cr1 & PWR_CR1_LPR) == 0U) { - /* Main mode selected.*/ - - while ((PWR->SR2 & PWR_SR2_REGLPF) != 0U) { - /* Waiting for the regulator to be in main mode.*/ - } - } - else { - /* Low power mode selected.*/ - - while ((PWR->SR2 & PWR_SR2_REGLPF) == 0U) { - /* Waiting for the regulator to be in low power mode.*/ - } + PWR->VOSCR = ccp->pwr_voscr; + while ((PWR->VOSSR & PWR_VOSSR_ACTVOSRDY) == 0U) { + /* Wait until regulator is stable.*/ } + PWR->VMCR = ccp->pwr_vmcr; /* Switching to the final clock source.*/ - RCC->CFGR = (RCC->CFGR & ~RCC_CFGR_SW_Msk) | (ccp->rcc_cfgr & RCC_CFGR_SW_Msk); - while ((RCC->CFGR & RCC_CFGR_SWS) != ((ccp->rcc_cfgr & RCC_CFGR_SW_Msk) << RCC_CFGR_SWS_Pos)) { - /* Waiting for clock switch.*/ + RCC->CFGR1 = ccp->rcc_cfgr1; + RCC->CFGR2 = ccp->rcc_cfgr2; + while ((RCC->CFGR1 & STM32_SWS_MASK) != (ccp->rcc_cfgr1 & STM32_SWS_MASK)) { + /* Wait until SYSCLK is stable.*/ } - /* If HSI16 is not in configuration then it is finally shut down.*/ - if ((ccp->rcc_cr & RCC_CR_HSION) == 0U) { - hsi16_disable(); + /* If HSI is not in configuration then it is finally shut down.*/ + if ((ccp->rcc_cr & STM32_HSION) == 0U) { + hsi_disable(); } return false; @@ -883,14 +867,11 @@ void stm32_clock_init(void) { board files.*/ rccResetAHB1(~0); rccResetAHB2(~STM32_GPIO_EN_MASK); - rccResetAHB3(~0); - rccResetAPB1R1(~0); - rccResetAPB1R2(~0); + rccResetAHB4(~0); + rccResetAPB1L(~0); + rccResetAPB1H(~0); rccResetAPB2(~0); - - /* SYSCFG clock enabled here because it is a multi-functional unit shared - among multiple drivers.*/ - rccEnableAPB2(RCC_APB2ENR_SYSCFGEN, false); + rccResetAPB3(~0); /* RTC APB clock enable.*/ #if (HAL_USE_RTC == TRUE) && defined(RCC_APB1ENR1_RTCAPBEN) @@ -900,9 +881,6 @@ void stm32_clock_init(void) { /* Static PWR configurations.*/ hal_lld_set_static_pwr(); - /* Backup domain made accessible.*/ - PWR->CR1 |= PWR_CR1_DBP; - /* Backup domain reset.*/ bd_reset(); diff --git a/os/hal/ports/STM32/STM32H5xx/hal_lld.h b/os/hal/ports/STM32/STM32H5xx/hal_lld.h index 84bd778e2..0c1919e9a 100644 --- a/os/hal/ports/STM32/STM32H5xx/hal_lld.h +++ b/os/hal/ports/STM32/STM32H5xx/hal_lld.h @@ -114,8 +114,56 @@ * @name RCC_CR register bits definitions * @{ */ -#define STM32_HSIDIV_POS 3 -#define STM32_HSIDIV_MASK (3U << STM32_HSIDIV_POS) +#define STM32_PLL3ON_POS RCC_CR_PLL3ON_Pos +#define STM32_PLL3ON_MASK RCC_CR_PLL3ON_Msk +#define STM32_PLL3ON (1U << STM32_PLL3ON_POS) + +#define STM32_PLL2ON_POS RCC_CR_PLL2ON_Pos +#define STM32_PLL2ON_MASK RCC_CR_PLL2ON_Msk +#define STM32_PLL2ON (1U << STM32_PLL2ON_POS) + +#define STM32_PLL1ON_POS RCC_CR_PLL1ON_Pos +#define STM32_PLL1ON_MASK RCC_CR_PLL1ON_Msk +#define STM32_PLL1ON (1U << STM32_PLL1ON_POS) + +#define STM32_HSERDY_POS RCC_CR_HSERDY_Pos +#define STM32_HSERDY_MASK RCC_CR_HSERDY_Msk +#define STM32_HSERDY (1U << STM32_HSERDY_POS) + +#define STM32_HSEON_POS RCC_CR_HSEON_Pos +#define STM32_HSEON_MASK RCC_CR_HSEON_Msk +#define STM32_HSEON (1U << STM32_HSEON_POS) + +#define STM32_HSI48RDY_POS RCC_CR_HSI48RDY_Pos +#define STM32_HSI48RDY_MASK RCC_CR_HSI48RDY_Msk +#define STM32_HSI48RDY (1U << STM32_HSI48RDY_POS) + +#define STM32_HSI48ON_POS RCC_CR_HSI48ON_Pos +#define STM32_HSI48ON_MASK RCC_CR_HSI48ON_Msk +#define STM32_HSI48ON (1U << STM32_HSI48ON_POS) + +#define STM32_CSIRDY_POS RCC_CR_CSIRDY_Pos +#define STM32_CSIRDY_MASK RCC_CR_CSIRDY_Msk +#define STM32_CSIRDY (1U << STM32_CSIRDY_POS) + +#define STM32_CSION_POS RCC_CR_HSION_Pos +#define STM32_CSION_MASK RCC_CR_HSION_Msk +#define STM32_CSION (1U << STM32_HSION_POS) + +#define STM32_HSIRDY_POS RCC_CR_HSIRDY_Pos +#define STM32_HSIRDY_MASK RCC_CR_HSIRDY_Msk +#define STM32_HSIRDY (1U << STM32_HSIRDY_POS) + +#define STM32_HSION_POS RCC_CR_HSION_Pos +#define STM32_HSION_MASK RCC_CR_HSION_Msk +#define STM32_HSION (1U << STM32_HSION_POS) + +#define STM32_HSIDIVF_POS RCC_CR_HSIDIVF_Pos +#define STM32_HSIDIVF_MASK RCC_CR_HSIDIVF_Msk +#define STM32_HSIDIVF (1U << STM32_HSIDIVF_POS) + +#define STM32_HSIDIV_POS RCC_CR_HSIDIV_Pos +#define STM32_HSIDIV_MASK RCC_CR_HSIDIV_Msk #define STM32_HSIDIV_FIELD(n) ((n) << STM32_HSIDIV_POS) #define STM32_HSIDIV_DIV1 STM32_HSIDIV_FIELD(0U) #define STM32_HSIDIV_DIV2 STM32_HSIDIV_FIELD(1U) @@ -127,8 +175,9 @@ * @name RCC_CFGR1 register bits definitions * @{ */ -#define STM32_SW_MASK (3U << 0) -#define STM32_SW_FIELD(n) ((n) << 0) +#define STM32_SW_POS RCC_CFGR1_SW_Pos +#define STM32_SW_MASK RCC_CFGR1_SW_Msk +#define STM32_SW_FIELD(n) ((n) << STM32_SW_POS) #define STM32_SW_HSI STM32_SW_FIELD(0U) #define STM32_SW_CSI STM32_SW_FIELD(1U) #define STM32_SW_HSE STM32_SW_FIELD(2U) @@ -190,6 +239,31 @@ #define STM32_MCO2PRE_NOCLOCK STM32_MCO2PRE_FIELD(0U) /** @} */ +/** + * @name RCC_CFGR2 register bits definitions + * @{ + */ +#define STM32_APB3DIS_POS RCC_CFGR2_APB3DIS_Pos +#define STM32_APB3DIS_MASK RCC_CFGR2_APB3DIS_Msk +#define STM32_APB3DIS (1U << STM32_APB3DIS_POS) + +#define STM32_APB2DIS_POS RCC_CFGR2_APB2DIS_Pos +#define STM32_APB2DIS_MASK RCC_CFGR2_APB2DIS_Msk +#define STM32_APB2DIS (1U << STM32_APB2DIS_POS) + +#define STM32_APB1DIS_POS RCC_CFGR2_APB1DIS_Pos +#define STM32_APB1DIS_MASK RCC_CFGR2_APB1DIS_Msk +#define STM32_APB1DIS (1U << STM32_APB1DIS_POS) + +#define STM32_AHB2DIS_POS RCC_CFGR2_AHB2DIS_Pos +#define STM32_AHB2DIS_MASK RCC_CFGR2_AHB2DIS_Msk +#define STM32_AHB2DIS (1U << STM32_AHB2DIS_POS) + +#define STM32_AHB1DIS_POS RCC_CFGR2_AHB1DIS_Pos +#define STM32_AHB1DIS_MASK RCC_CFGR2_AHB1DIS_Msk +#define STM32_AHB1DIS (1U << STM32_AHB1DIS_POS) +/** @} */ + /** * @name RCC_PLLxCFGR register bits definitions * @{