andreika-git
/
ChibiOS
mirror of https://github.com/andreika-git/ChibiOS.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

ADCv3 working on L4 in single mode. 

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@8598 35acf78f-673a-0410-8e92-d51de3d6d3f4
This commit is contained in:
Giovanni Di Sirio 2015-12-14 11:40:18 +00:00
parent 5c2d8efab3
commit d0487d83cf
4 changed files with 90 additions and 38 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

62
os/hal/ports/STM32/LLD/ADCv3/adc_lld.c
View File

@ -30,6 +30,18 @@
/* Driver local definitions. */
/*===========================================================================*/
#define ADC1_DMA_CHANNEL \
STM32_DMA_GETCHANNEL(STM32_ADC_ADC1_DMA_STREAM, STM32_ADC1_DMA_CHN)
#define ADC2_DMA_CHANNEL \
STM32_DMA_GETCHANNEL(STM32_ADC_ADC2_DMA_STREAM, STM32_ADC2_DMA_CHN)
#define ADC3_DMA_CHANNEL \
STM32_DMA_GETCHANNEL(STM32_ADC_ADC3_DMA_STREAM, STM32_ADC3_DMA_CHN)
#define ADC4_DMA_CHANNEL \
STM32_DMA_GETCHANNEL(STM32_ADC_ADC4_DMA_STREAM, STM32_ADC4_DMA_CHN)
#if STM32_ADC_DUAL_MODE
#if STM32_ADC_COMPACT_SAMPLES
/* Compact type dual mode.*/
@ -421,12 +433,18 @@ void adc_lld_init(void) {
#if STM32_ADC_USE_ADC1
/* Driver initialization.*/
adcObjectInit(&ADCD1);
ADCD1.adcm = ADC1;
#if STM32_ADC_DUAL_MODE
ADCD1.adcs = ADC2;
#if defined(ADC1_2_COMMON)
ADCD1.adcc = ADC1_2_COMMON;
#elif defined(ADC123_COMMON)
ADCD1.adcc = ADC123_COMMON;
#else
ADCD1.adcc = ADC1_COMMON;
#endif
ADCD1.dmastp = STM32_DMA1_STREAM1;
ADCD1.adcm = ADC1;
#if STM32_ADC_DUAL_MODE
ADCD1.adcs = ADC2;
#endif
ADCD1.dmastp = STM32_DMA_STREAM(STM32_ADC_ADC1_DMA_STREAM);
ADCD1.dmamode = ADC_DMA_SIZE |
STM32_DMA_CR_PL(STM32_ADC_ADC1_DMA_PRIORITY) |
STM32_DMA_CR_DIR_P2M |
@ -437,12 +455,18 @@ void adc_lld_init(void) {
#if STM32_ADC_USE_ADC3
/* Driver initialization.*/
adcObjectInit(&ADCD3);
ADCD3.adcm = ADC3;
#if STM32_ADC_DUAL_MODE
ADCD3.adcs = ADC4;
#if defined(ADC3_4_COMMON)
ADCD3.adcc = ADC3_4_COMMON;
#elif defined(ADC123_COMMON)
ADCD1.adcc = ADC123_COMMON;
#else
ADCD3.adcc = ADC3_COMMON;
#endif
ADCD3.dmastp = STM32_DMA2_STREAM5;
ADCD3.adcm = ADC3;
#if STM32_ADC_DUAL_MODE
ADCD3.adcs = ADC4;
#endif
ADCD3.dmastp = STM32_DMA_STREAM(STM32_ADC_ADC3_DMA_STREAM);
ADCD3.dmamode = ADC_DMA_SIZE |
STM32_DMA_CR_PL(STM32_ADC_ADC3_DMA_PRIORITY) |
STM32_DMA_CR_DIR_P2M |
@ -468,13 +492,13 @@ void adc_lld_init(void) {
#if defined(STM32F3XX)
#if STM32_ADC_USE_ADC1 || STM32_ADC_USE_ADC2
rccEnableADC12(FALSE);
// osalSysPolledDelayX(12);
rccResetADC12();
ADC1_2_COMMON->CCR = STM32_ADC_ADC123_CLOCK_MODE | ADC_DMA_MDMA;
rccDisableADC12(FALSE);
#endif
#if STM32_ADC_USE_ADC3 || STM32_ADC_USE_ADC4
rccEnableADC34(FALSE);
// osalSysPolledDelayX(12);
rccResetADC34();
ADC3_4_COMMON->CCR = STM32_ADC_ADC123_CLOCK_MODE | ADC_DMA_MDMA;
rccDisableADC34(FALSE);
#endif
@ -482,7 +506,7 @@ void adc_lld_init(void) {
#if defined(STM32L4XX)
rccEnableADC123(FALSE);
// osalSysPolledDelayX(12);
rccResetADC123();
ADC123_COMMON->CCR = STM32_ADC_ADC123_CLOCK_MODE | ADC_DMA_MDMA;
rccDisableADC123(FALSE);
#endif
@ -516,6 +540,9 @@ void adc_lld_start(ADCDriver *adcp) {
clkmask |= (1 << 0);
#if defined(STM32F3XX)
rccEnableADC12(FALSE);
#endif
#if defined(STM32L4XX)
rccEnableADC123(FALSE);
#endif
}
#endif /* STM32_ADC_USE_ADC1 */
@ -532,6 +559,9 @@ void adc_lld_start(ADCDriver *adcp) {
clkmask |= (1 << 1);
#if defined(STM32F3XX)
rccEnableADC12(FALSE);
#endif
#if defined(STM32L4XX)
rccEnableADC123(FALSE);
#endif
}
#endif /* STM32_ADC_USE_ADC2 */
@ -548,6 +578,9 @@ void adc_lld_start(ADCDriver *adcp) {
clkmask |= (1 << 2);
#if defined(STM32F3XX)
rccEnableADC34(FALSE);
#endif
#if defined(STM32L4XX)
rccEnableADC123(FALSE);
#endif
}
#endif /* STM32_ADC_USE_ADC3 */
@ -564,14 +597,13 @@ void adc_lld_start(ADCDriver *adcp) {
clkmask |= (1 << 3);
#if defined(STM32F3XX)
rccEnableADC34(FALSE);
#endif
#if defined(STM32L4XX)
rccEnableADC123(FALSE);
#endif
}
#endif /* STM32_ADC_USE_ADC4 */
#if defined(STM32L4XX)
rccEnableADC123(FALSE);
#endif
/* Setting DMA peripheral-side pointer.*/
#if STM32_ADC_DUAL_MODE
dmaStreamSetPeripheral(adcp->dmastp, &adcp->adcc->CDR);

40
os/hal/ports/STM32/LLD/ADCv3/adc_lld.h
View File

@ -482,6 +482,44 @@
#error "Invalid DMA priority assigned to ADC4"
#endif
/* Check on the presence of the DMA streams settings in mcuconf.h.*/
#if STM32_ADC_USE_ADC1 && !defined(STM32_ADC_ADC1_DMA_STREAM)
#error "ADC1 DMA stream not defined"
#endif
#if STM32_ADC_USE_ADC2 && !defined(STM32_ADC_ADC2_DMA_STREAM)
#error "ADC2 DMA stream not defined"
#endif
#if STM32_ADC_USE_ADC3 && !defined(STM32_ADC_ADC3_DMA_STREAM)
#error "ADC3 DMA stream not defined"
#endif
#if STM32_ADC_USE_ADC4 && !defined(STM32_ADC_ADC4_DMA_STREAM)
#error "ADC4 DMA stream not defined"
#endif
/* Check on the validity of the assigned DMA channels.*/
#if STM32_ADC_USE_ADC1 && \
!STM32_DMA_IS_VALID_ID(STM32_ADC_ADC1_DMA_STREAM, STM32_ADC1_DMA_MSK)
#error "invalid DMA stream associated to ADC1"
#endif
#if STM32_ADC_USE_ADC2 && \
!STM32_DMA_IS_VALID_ID(STM32_ADC_ADC2_DMA_STREAM, STM32_ADC2_DMA_MSK)
#error "invalid DMA stream associated to ADC2"
#endif
#if STM32_ADC_USE_ADC3 && \
!STM32_DMA_IS_VALID_ID(STM32_ADC_ADC3_DMA_STREAM, STM32_ADC3_DMA_MSK)
#error "invalid DMA stream associated to ADC3"
#endif
#if STM32_ADC_USE_ADC4 && \
!STM32_DMA_IS_VALID_ID(STM32_ADC_ADC4_DMA_STREAM, STM32_ADC4_DMA_MSK)
#error "invalid DMA stream associated to ADC4"
#endif
/* ADC clock source checks.*/
#if defined(STM32F3XX)
#if STM32_ADC_ADC12_CLOCK_MODE == ADC_CCR_CKMODE_ADCCK
@ -721,11 +759,11 @@ struct ADCDriver {
* @brief Pointer to the slave ADCx registers block.
*/
ADC_TypeDef *adcs;
#endif /* STM32_ADC_DUAL_MODE */
/**
* @brief Pointer to the common ADCx_y registers block.
*/
ADC_Common_TypeDef *adcc;
#endif /* STM32_ADC_DUAL_MODE */
/**
* @brief Pointer to associated DMA channel.
*/

23
testhal/STM32/STM32L4xx/GPT-ADC/main.c
View File

@ -17,10 +17,6 @@
#include "ch.h"
#include "hal.h"
/* TRUE means that DMA-accessible buffers are placed in a non-cached RAM
area and that no cache management is required.*/
#define DMA_BUFFERS_COHERENCE TRUE
/*===========================================================================*/
/* GPT driver related. */
/*===========================================================================*/
@ -42,16 +38,7 @@ static const GPTConfig gpt4cfg1 = {
#define ADC_GRP1_NUM_CHANNELS 2
#define ADC_GRP1_BUF_DEPTH 64
#if !DMA_BUFFERS_COHERENCE
/* Note, the buffer is aligned to a 32 bytes boundary because limitations
imposed by the data cache. Note, this is GNU specific, it must be
handled differently for other compilers.
Only required if the ADC buffer is placed in a cache-able area.*/
#if defined(__GNUC__)
__attribute__((aligned (32)))
#endif
#endif
static adcsample_t samples1[ADC_GRP1_NUM_CHANNELS * ADC_GRP1_BUF_DEPTH];
adcsample_t samples1[ADC_GRP1_NUM_CHANNELS * ADC_GRP1_BUF_DEPTH];
/*
* ADC streaming callback.
@ -59,15 +46,7 @@ static adcsample_t samples1[ADC_GRP1_NUM_CHANNELS * ADC_GRP1_BUF_DEPTH];
size_t nx = 0, ny = 0;
static void adccallback(ADCDriver *adcp, adcsample_t *buffer, size_t n) {
#if !DMA_BUFFERS_COHERENCE
/* DMA buffer invalidation because data cache, only invalidating the
half buffer just filled.
Only required if the ADC buffer is placed in a cache-able area.*/
dmaBufferInvalidate(buffer,
n * adcp->grpp->num_channels * sizeof (adcsample_t));
#else
(void)adcp;
#endif
/* Updating counters.*/
if (samples1 == buffer) {

3
testhal/STM32/STM32L4xx/GPT-ADC/mcuconf.h
View File

@ -99,6 +99,9 @@
#define STM32_ADC_USE_ADC1 TRUE
#define STM32_ADC_USE_ADC2 TRUE
#define STM32_ADC_USE_ADC3 TRUE
#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(1, 1)
#define STM32_ADC_ADC2_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
#define STM32_ADC_ADC3_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
#define STM32_ADC_ADC1_DMA_PRIORITY 2
#define STM32_ADC_ADC2_DMA_PRIORITY 2
#define STM32_ADC_ADC3_DMA_PRIORITY 2