[FSMC NAND] Low level driver cosmetical cleanup
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@7194 35acf78f-673a-0410-8e92-d51de3d6d3f4
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@ -20,7 +20,7 @@
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/**
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* @file nand_lld.c
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* @brief NAND Driver subsystem low level driver source template.
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* @brief NAND Driver subsystem low level driver source.
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*
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* @addtogroup NAND
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* @{
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@ -252,7 +252,7 @@ void nand_lld_init(void) {
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NANDD1.datalen = 0;
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NANDD1.thread = NULL;
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NANDD1.dma = STM32_DMA_STREAM(STM32_NAND_DMA_STREAM);
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NANDD1.nand = (FSMC_NAND_TypeDef *)FSMC_Bank2_R_BASE;
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NANDD1.nand = FSMCD1.nand1;
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NANDD1.map_data = (uint8_t*)FSMC_Bank2_MAP_COMMON_DATA;
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NANDD1.map_cmd = (uint8_t*)FSMC_Bank2_MAP_COMMON_CMD;
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NANDD1.map_addr = (uint8_t*)FSMC_Bank2_MAP_COMMON_ADDR;
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@ -265,7 +265,7 @@ void nand_lld_init(void) {
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NANDD2.datalen = 0;
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NANDD2.thread = NULL;
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NANDD2.dma = STM32_DMA_STREAM(STM32_NAND_DMA_STREAM);
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NANDD2.nand = (FSMC_NAND_TypeDef *)FSMC_Bank3_R_BASE;
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NANDD2.nand = FSMCD1.nand2;
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NANDD2.map_data = (uint8_t*)FSMC_Bank3_MAP_COMMON_DATA;
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NANDD2.map_cmd = (uint8_t*)FSMC_Bank3_MAP_COMMON_CMD;
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NANDD2.map_addr = (uint8_t*)FSMC_Bank3_MAP_COMMON_ADDR;
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@ -403,8 +403,7 @@ uint8_t nand_lld_write_data(NANDDriver *nandp, const uint8_t *data,
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nandp->nand->PCR |= FSMC_PCR_ECCEN;
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}
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dmaStartMemCopy(nandp->dma, nandp->dmamode,
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data, nandp->map_data, datalen);
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dmaStartMemCopy(nandp->dma, nandp->dmamode, data, nandp->map_data, datalen);
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nand_lld_suspend_thread(nandp);
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osalSysUnlock();
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@ -430,8 +429,7 @@ uint8_t nand_lld_write_data(NANDDriver *nandp, const uint8_t *data,
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*
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* @notapi
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*/
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uint8_t nand_lld_erase(NANDDriver *nandp,
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uint8_t *addr, size_t addrlen){
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uint8_t nand_lld_erase(NANDDriver *nandp, uint8_t *addr, size_t addrlen){
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nandp->state = NAND_ERASE;
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@ -457,8 +455,7 @@ uint8_t nand_lld_erase(NANDDriver *nandp,
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*
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* @notapi
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*/
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void nand_lld_polled_read_data(NANDDriver *nandp,
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uint8_t *data, size_t len){
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void nand_lld_polled_read_data(NANDDriver *nandp, uint8_t *data, size_t len){
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size_t i = 0;
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for (i=0; i<len; i++)
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@ -474,8 +471,7 @@ void nand_lld_polled_read_data(NANDDriver *nandp,
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*
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* @notapi
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*/
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void nand_lld_write_addr(NANDDriver *nandp,
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const uint8_t *addr, size_t len){
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void nand_lld_write_addr(NANDDriver *nandp, const uint8_t *addr, size_t len){
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size_t i = 0;
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for (i=0; i<len; i++)
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@ -20,7 +20,7 @@
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/**
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* @file nand_lld.h
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* @brief NAND Driver subsystem low level driver header template.
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* @brief NAND Driver subsystem low level driver header.
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*
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* @addtogroup NAND
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* @{
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@ -38,7 +38,6 @@
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/*===========================================================================*/
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#define NAND_MIN_PAGE_SIZE 256
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#define NAND_MAX_PAGE_SIZE 8192
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#define NAND_BAD_MAP_END_MARK ((uint16_t)0xFFFF)
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/*===========================================================================*/
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/* Driver pre-compile time settings. */
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@ -49,10 +48,10 @@
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* @{
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*/
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/**
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* @brief EMD FSMC1 interrupt priority level setting.
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* @brief FSMC1 interrupt priority level setting.
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*/
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#if !defined(STM32_EMC_FSMC1_IRQ_PRIORITY) || defined(__DOXYGEN__)
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#define STM32_EMC_FSMC1_IRQ_PRIORITY 10
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#define STM32_EMC_FSMC1_IRQ_PRIORITY 10
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#endif
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/**
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@ -60,7 +59,7 @@
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* @details If set to @p TRUE the support for NAND1 is included.
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*/
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#if !defined(STM32_NAND_USE_NAND1) || defined(__DOXYGEN__)
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#define STM32_NAND_USE_NAND1 FALSE
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#define STM32_NAND_USE_NAND1 FALSE
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#endif
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/**
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@ -68,7 +67,7 @@
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* @details If set to @p TRUE the support for NAND2 is included.
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*/
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#if !defined(STM32_NAND_USE_NAND2) || defined(__DOXYGEN__)
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#define STM32_NAND_USE_NAND2 FALSE
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#define STM32_NAND_USE_NAND2 FALSE
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#endif
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/**
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@ -77,7 +76,7 @@
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* error can only happen because programming errors.
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*/
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#if !defined(STM32_NAND_DMA_ERROR_HOOK) || defined(__DOXYGEN__)
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#define STM32_NAND_DMA_ERROR_HOOK(nandp) osalSysHalt("DMA failure")
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#define STM32_NAND_DMA_ERROR_HOOK(nandp) osalSysHalt("DMA failure")
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#endif
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/**
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@ -85,29 +84,29 @@
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* @details If set to @p TRUE the support for internal FSMC interrupt included.
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*/
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#if !defined(STM32_NAND_USE_INT) || defined(__DOXYGEN__)
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#define STM32_NAND_USE_INT FALSE
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#define STM32_NAND_USE_INT FALSE
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#endif
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/**
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* @brief NAND1 DMA priority (0..3|lowest..highest).
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*/
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#if !defined(STM32_NAND_NAND1_DMA_PRIORITY) || defined(__DOXYGEN__)
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#define STM32_NAND_NAND1_DMA_PRIORITY 0
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#define STM32_NAND_NAND1_DMA_PRIORITY 0
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#endif
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/**
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* @brief NAND2 DMA priority (0..3|lowest..highest).
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*/
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#if !defined(STM32_NAND_NAND2_DMA_PRIORITY) || defined(__DOXYGEN__)
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#define STM32_NAND_NAND2_DMA_PRIORITY 0
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#define STM32_NAND_NAND2_DMA_PRIORITY 0
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#endif
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/**
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* @brief DMA stream used for NAND1 operations.
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* @brief DMA stream used for NAND operations.
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* @note This option is only available on platforms with enhanced DMA.
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*/
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#if !defined(STM32_NAND_DMA_STREAM) || defined(__DOXYGEN__)
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#define STM32_NAND_DMA_STREAM STM32_DMA_STREAM_ID(2, 6)
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#define STM32_NAND_DMA_STREAM STM32_DMA_STREAM_ID(2, 6)
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#endif
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/** @} */
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@ -120,11 +119,7 @@
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#error "NAND driver activated but no NAND peripheral assigned"
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#endif
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#if STM32_NAND_USE_FSMC_NAND1 && !STM32_HAS_FSMC
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#error "FSMC not present in the selected device"
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#endif
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#if STM32_NAND_USE_FSMC_NAND2 && !STM32_HAS_FSMC
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#if (STM32_NAND_USE_FSMC_NAND2 || STM32_NAND_USE_FSMC_NAND1) && !STM32_HAS_FSMC
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#error "FSMC not present in the selected device"
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#endif
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@ -324,12 +319,9 @@ extern "C" {
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size_t datalen, uint8_t *addr, size_t addrlen, uint32_t *ecc);
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void nand_lld_read_data(NANDDriver *nandp, uint8_t *data,
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size_t datalen, uint8_t *addr, size_t addrlen, uint32_t *ecc);
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void nand_lld_polled_read_data(NANDDriver *nandp, uint8_t *data,
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size_t len);
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uint8_t nand_lld_erase(NANDDriver *nandp, uint8_t *addr,
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size_t addrlen);
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void nand_lld_write_addr(NANDDriver *nandp,
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const uint8_t *addr, size_t len);
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void nand_lld_polled_read_data(NANDDriver *nandp, uint8_t *data, size_t len);
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uint8_t nand_lld_erase(NANDDriver *nandp, uint8_t *addr, size_t addrlen);
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void nand_lld_write_addr(NANDDriver *nandp, const uint8_t *addr, size_t len);
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void nand_lld_write_cmd(NANDDriver *nandp, uint8_t cmd);
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uint8_t nand_lld_read_status(NANDDriver *nandp);
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#ifdef __cplusplus
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