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I2C. API changes. rw_bit field moved from slave config ctructure to the driver structure. 

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/branches/i2c_dev@2845 35acf78f-673a-0410-8e92-d51de3d6d3f4
This commit is contained in:
barthess 2011-03-27 14:57:47 +00:00
parent d0397838ae
commit d16a6e24d9
3 changed files with 18 additions and 10 deletions
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2
os/hal/include/i2c.h
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@ -161,8 +161,6 @@ struct I2CSlaveConfig{
*/ */
uint16_t address; uint16_t address;
//TODO: (is it need?) merge rw_bit, restart and address in one 16-bit variable.
uint8_t rw_bit;
bool_t restart; // send restart if TRUE. Else sent stop event after complete data tx/rx bool_t restart; // send restart if TRUE. Else sent stop event after complete data tx/rx

14
os/hal/platforms/STM32/i2c_lld.c
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@ -124,7 +124,7 @@ static void i2c_serve_event_interrupt(I2CDriver *i2cp) {
if(!(i2cp->id_slave_config->address & 0x8000)){ // slave address is 7-bit if(!(i2cp->id_slave_config->address & 0x8000)){ // slave address is 7-bit
i2cp->id_i2c->DR = ((i2cp->id_slave_config->address & 0x7F) << 1) | i2cp->id_i2c->DR = ((i2cp->id_slave_config->address & 0x7F) << 1) |
i2cp->id_slave_config->rw_bit; i2cp->rw_bit;
i2cp->id_state = I2C_MWAIT_ADDR_ACK; i2cp->id_state = I2C_MWAIT_ADDR_ACK;
return; return;
} }
@ -139,7 +139,7 @@ static void i2c_serve_event_interrupt(I2CDriver *i2cp) {
// "wait" interrupt with ADD10 flag // "wait" interrupt with ADD10 flag
if ((i2cp->id_state == I2C_10BIT_HANDSHAKE) && (i2cp->id_i2c->SR1 & I2C_SR1_ADD10)){ if ((i2cp->id_state == I2C_10BIT_HANDSHAKE) && (i2cp->id_i2c->SR1 & I2C_SR1_ADD10)){
i2cp->id_i2c->DR = i2cp->id_slave_config->address & 0x00FF; // send remaining bits of address i2cp->id_i2c->DR = i2cp->id_slave_config->address & 0x00FF; // send remaining bits of address
if (!(i2cp->id_slave_config->rw_bit)) if (!(i2cp->rw_bit))
// in transmit mode there is nothing to do with 10-bit handshaking // in transmit mode there is nothing to do with 10-bit handshaking
i2cp->id_state = I2C_MWAIT_ADDR_ACK; i2cp->id_state = I2C_MWAIT_ADDR_ACK;
return; return;
@ -310,7 +310,7 @@ void i2c_lld_start(I2CDriver *i2cp) {
i2c_lld_set_clock(i2cp); i2c_lld_set_clock(i2cp);
i2c_lld_set_opmode(i2cp); i2c_lld_set_opmode(i2cp);
i2cp->id_i2c->CR2 |= I2C_CR2_ITERREN | I2C_CR2_ITEVTEN | I2C_CR2_ITBUFEN; i2cp->id_i2c->CR2 |= I2C_CR2_ITERREN | I2C_CR2_ITEVTEN | I2C_CR2_ITBUFEN;// enable interrupts
i2cp->id_i2c->CR1 |= 1; // enable interface i2cp->id_i2c->CR1 |= 1; // enable interface
} }
@ -477,7 +477,7 @@ void i2c_lld_master_stop(I2CDriver *i2cp){
void i2c_lld_master_transmit(I2CDriver *i2cp, I2CSlaveConfig *i2cscfg){ void i2c_lld_master_transmit(I2CDriver *i2cp, I2CSlaveConfig *i2cscfg){
i2cp->id_slave_config = i2cscfg; i2cp->id_slave_config = i2cscfg;
i2cp->id_slave_config->rw_bit = I2C_WRITE; i2cp->rw_bit = I2C_WRITE;
// generate start condition. Later transmission goes in background // generate start condition. Later transmission goes in background
i2c_lld_master_start(i2cp); i2c_lld_master_start(i2cp);
@ -486,7 +486,7 @@ void i2c_lld_master_transmit(I2CDriver *i2cp, I2CSlaveConfig *i2cscfg){
void i2c_lld_master_receive(I2CDriver *i2cp, I2CSlaveConfig *i2cscfg){ void i2c_lld_master_receive(I2CDriver *i2cp, I2CSlaveConfig *i2cscfg){
i2cp->id_slave_config = i2cscfg; i2cp->id_slave_config = i2cscfg;
i2cp->id_slave_config->rw_bit = I2C_READ; i2cp->rw_bit = I2C_READ;
// generate (re)start condition. Later connection goes asynchronously // generate (re)start condition. Later connection goes asynchronously
i2c_lld_master_start(i2cp); i2c_lld_master_start(i2cp);
@ -495,7 +495,7 @@ void i2c_lld_master_receive(I2CDriver *i2cp, I2CSlaveConfig *i2cscfg){
/** /**
* @brief Transmits data ever the I2C bus as masteri2cp. * @brief Transmits data via I2C bus.
* *
* @note This function does not use interrupts * @note This function does not use interrupts
* *
@ -508,7 +508,7 @@ void i2c_lld_master_transmit_NI(I2CDriver *i2cp, I2CSlaveConfig *i2cscfg, bool_t
int i = 0; int i = 0;
i2cp->id_slave_config = i2cscfg; i2cp->id_slave_config = i2cscfg;
i2cp->id_slave_config->rw_bit = I2C_WRITE; i2cp->rw_bit = I2C_WRITE;
i2cp->id_i2c->CR1 |= I2C_CR1_START; // generate start condition i2cp->id_i2c->CR1 |= I2C_CR1_START; // generate start condition

12
os/hal/platforms/STM32/i2c_lld.h
View File

@ -116,6 +116,12 @@ struct I2CDriver{
* @brief Driver state. * @brief Driver state.
*/ */
i2cstate_t id_state; i2cstate_t id_state;
#if I2C_USE_WAIT
/**
* @brief Thread waiting for I/O completion.
*/
Thread *thread;
#endif /* I2C_USE_WAIT */
#if I2C_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__) #if I2C_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__)
#if CH_USE_MUTEXES || defined(__DOXYGEN__) #if CH_USE_MUTEXES || defined(__DOXYGEN__)
/** /**
@ -134,8 +140,12 @@ struct I2CDriver{
* @brief Current slave configuration data. * @brief Current slave configuration data.
*/ */
I2CSlaveConfig *id_slave_config; I2CSlaveConfig *id_slave_config;
/**
* @brief RW-bit sent to slave.
*/
uint8_t rw_bit;
/* End of the mandatory fields.*/ /*********** End of the mandatory fields. **********************************/
/** /**
* @brief Pointer to the I2Cx registers block. * @brief Pointer to the I2Cx registers block.