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Fixed warnings with __STATIC_INLINE, modified target core checks. 

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@14625 27425a3e-05d8-49a3-a47f-9c15f0e5edd8
This commit is contained in:
vrepetenko 2021-07-26 09:31:10 +00:00
parent 87662794c0
commit d21a907e0c
3 changed files with 10 additions and 23 deletions
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10
os/hal/ports/STM32/STM32WLxx/hal_lld.c
View File

@ -202,27 +202,24 @@ static const system_limits_t vos_range2 = {
/* Driver local functions. */
/*===========================================================================*/
#if (STM32_NO_INIT == FALSE || defined(HAL_LLD_USE_CLOCK_MANAGEMENT)) || defined(__DOXYGEN__)
/**
* @brief Safe setting of flash ACR register.
*
* @param[in] acr value for the ACR register
*/
static void flash_set_acr(uint32_t acr) {
__STATIC_INLINE void flash_set_acr(uint32_t acr) {
FLASH->ACR = acr;
while ((FLASH->ACR & FLASH_ACR_LATENCY_Msk) != (acr & FLASH_ACR_LATENCY_Msk)) {
/* Waiting for flash wait states setup.*/
}
}
#endif /* (STM32_NO_INIT == TRUE || defined(HAL_LLD_USE_CLOCK_MANAGEMENT)) */
#if (STM32_NO_INIT == FALSE) || defined(__DOXYGEN__)
/**
* @brief Configures the PWR unit.
* @note CR1, CR2 and CR5 are not initialized inside this function.
*/
static void hal_lld_set_static_pwr(void) {
__STATIC_INLINE void hal_lld_set_static_pwr(void) {
/* Static PWR configurations.*/
PWR->CR3 = STM32_PWR_CR3;
@ -240,7 +237,7 @@ static void hal_lld_set_static_pwr(void) {
/**
* @brief Initializes static muxes and dividers.
*/
static void hal_lld_set_static_clocks(void) {
__STATIC_INLINE void hal_lld_set_static_clocks(void) {
uint32_t ccipr;
@ -258,7 +255,6 @@ static void hal_lld_set_static_clocks(void) {
RCC->CCIPR = ccipr;
}
#endif /* (STM32_NO_INIT == FALSE) */
#if defined(HAL_LLD_USE_CLOCK_MANAGEMENT) || defined(__DOXYGEN__)
static bool hal_lld_check_pll(const system_limits_t *slp,

19
os/hal/ports/STM32/STM32WLxx/hal_lld.h
View File

@ -367,14 +367,6 @@
#define STM32_NO_INIT FALSE
#endif
/**
* @brief Target code for this HAL configuration.
* @note Core 1 is the Cortex-M4, core 2 is the Cortex-M0+.
*/
#if !defined(STM32_TARGET_CORE) || defined(__DOXYGEN__)
#define STM32_TARGET_CORE 1
#endif
/**
* @brief Enables the dynamic clock handling.
*/
@ -734,12 +726,11 @@
#error "Using a wrong mcuconf.h file, STM32WLxx_MCUCONF not defined"
#endif
/**
* @brief Target core for this HAL configuration.
* @note Core 1 is the Cortex-M4, core 2 is the Cortex-M0+.
/*
* Target core checks.
*/
#if !defined(STM32_TARGET_CORE) || defined(__DOXYGEN__)
#define STM32_TARGET_CORE 1
#if !defined(STM32_TARGET_CORE)
#error "STM32_TARGET_CORE not defined in mcuconf.h"
#endif
#if (STM32_TARGET_CORE == 2) && (STM32_HAS_M0 == FALSE)
@ -748,7 +739,7 @@
#if (defined(CORE_CM0PLUS) && (STM32_TARGET_CORE == 1)) || \
(!defined(CORE_CM0PLUS) && (STM32_TARGET_CORE == 2))
#error "wrong target core specified"
#error "wrong target core specified in mcuconf.h"
#endif
/*

4
os/hal/ports/STM32/STM32WLxx/stm32_registry.h
View File

@ -200,7 +200,7 @@
#define STM32_RTC_TAMP_STAMP_EXTI 19
#define STM32_RTC_WKUP_EXTI 20
#if STM32_TARGET_CORE == 1
#if !defined(CORE_CM0PLUS)
#define STM32_RTC_TAMP_STAMP_HANDLER Vector48
#define STM32_RTC_WKUP_HANDLER Vector4C
@ -221,7 +221,7 @@
#define STM32_RTC_IRQ_ENABLE() \
nvicEnableVector(STM32_RTC_COMMON_NUMBER, STM32_IRQ_EXTI17_20_IRQ_PRIORITY)
#endif /* STM32_TARGET_CORE == 1 */
#endif /* !defined(CORE_CM0PLUS) */
/* Enabling RTC-related EXTI lines.*/
#define STM32_RTC_ENABLE_ALL_EXTI() do { \