Fixed bug #1117.
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/branches/stable_20.3.x@13789 27425a3e-05d8-49a3-a47f-9c15f0e5edd8
This commit is contained in:
Giovanni Di Sirio
parent
0344bb0f5b
commit
d265a8170b
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@ -32,25 +32,29 @@
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#if STM32_ADC_DUAL_MODE == TRUE
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#if STM32_ADC_COMPACT_SAMPLES == TRUE
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/* Compact type dual mode.*/
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#define ADC_DMA_SIZE (STM32_DMA_CR_MSIZE_HWORD | STM32_DMA_CR_PSIZE_HWORD)
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#define ADC_DMA_DAMDF ADC_CCR_DAMDF_HWORD
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/* Compact type dual mode, 2x8-bit.*/
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#define ADC12_DMA_SIZE (STM32_DMA_CR_MSIZE_HWORD | STM32_DMA_CR_PSIZE_HWORD)
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#define ADC3_BDMA_SIZE (STM32_BDMA_CR_MSIZE_BYTE | STM32_BDMA_CR_PSIZE_BYTE)
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#define ADC_DMA_DAMDF ADC_CCR_DAMDF_BYTE
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#else /* STM32_ADC_COMPACT_SAMPLES == FALSE */
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/* Large type dual mode.*/
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#define ADC_DMA_SIZE (STM32_DMA_CR_MSIZE_WORD | STM32_DMA_CR_PSIZE_WORD)
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#define ADC_DMA_DAMDF ADC_CCR_DAMDF_WORD
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/* Large type dual mode, 2x16bit.*/
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#define ADC12_DMA_SIZE (STM32_DMA_CR_MSIZE_WORD | STM32_DMA_CR_PSIZE_WORD)
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#define ADC3_BDMA_SIZE (STM32_BDMA_CR_MSIZE_HWORD | STM32_BDMA_CR_PSIZE_HWORD)
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#define ADC_DMA_DAMDF ADC_CCR_DAMDF_HWORD
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#endif /* !STM32_ADC_COMPACT_SAMPLES */
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#else /* STM32_ADC_DUAL_MODE == FALSE */
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#if STM32_ADC_COMPACT_SAMPLES
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/* Compact type single mode.*/
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#define ADC_DMA_SIZE (STM32_DMA_CR_MSIZE_BYTE | STM32_DMA_CR_PSIZE_BYTE)
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/* Compact type single mode, 8-bit.*/
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#define ADC12_DMA_SIZE (STM32_DMA_CR_MSIZE_BYTE | STM32_DMA_CR_PSIZE_BYTE)
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#define ADC3_BDMA_SIZE (STM32_BDMA_CR_MSIZE_BYTE | STM32_BDMA_CR_PSIZE_BYTE)
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#define ADC_DMA_DAMDF ADC_CCR_DAMDF_DISABLED
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#else /* STM32_ADC_COMPACT_SAMPLES == FALSE */
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/* Large type single mode.*/
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#define ADC_DMA_SIZE (STM32_DMA_CR_MSIZE_HWORD | STM32_DMA_CR_PSIZE_HWORD)
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/* Large type single mode, 16-bit.*/
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#define ADC12_DMA_SIZE (STM32_DMA_CR_MSIZE_HWORD | STM32_DMA_CR_PSIZE_HWORD)
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#define ADC3_BDMA_SIZE (STM32_BDMA_CR_MSIZE_HWORD | STM32_BDMA_CR_PSIZE_HWORD)
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#define ADC_DMA_DAMDF ADC_CCR_DAMDF_DISABLED
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#endif /* STM32_ADC_COMPACT_SAMPLES == FALSE */
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#endif /* STM32_ADC_DUAL_MODE == FALSE */
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@ -90,7 +94,9 @@ static void adc_lld_vreg_on(ADCDriver *adcp) {
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adcp->adcm->CR = ADC_CR_ADVREGEN;
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#if STM32_ADC_DUAL_MODE
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if (&ADCD1 == adcp) {
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adcp->adcs->CR = ADC_CR_ADVREGEN;
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}
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#endif
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osalSysPolledDelayX(OSAL_US2RTC(STM32_SYS_CK, 10U));
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}
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@ -104,7 +110,9 @@ static void adc_lld_vreg_off(ADCDriver *adcp) {
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adcp->adcm->CR = ADC_CR_DEEPPWD;
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#if STM32_ADC_DUAL_MODE
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if (&ADCD1 == adcp) {
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adcp->adcs->CR = ADC_CR_DEEPPWD;
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}
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#endif
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}
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@ -120,10 +128,12 @@ static void adc_lld_analog_on(ADCDriver *adcp) {
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while ((adcp->adcm->ISR & ADC_ISR_ADRDY) == 0U)
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;
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#if STM32_ADC_DUAL_MODE
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if (&ADCD1 == adcp) {
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adcp->adcs->ISR = ADC_ISR_ADRDY;
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adcp->adcs->CR |= ADC_CR_ADEN;
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while ((adcp->adcs->ISR & ADC_ISR_ADRDY) == 0U)
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;
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}
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#endif
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}
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@ -138,9 +148,11 @@ static void adc_lld_analog_off(ADCDriver *adcp) {
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while ((adcp->adcm->CR & ADC_CR_ADDIS) != 0U)
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;
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#if STM32_ADC_DUAL_MODE
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if (&ADCD1 == adcp) {
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adcp->adcs->CR |= ADC_CR_ADDIS;
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while ((adcp->adcs->CR & ADC_CR_ADDIS) != 0U)
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;
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}
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#endif
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}
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@ -160,6 +172,7 @@ static void adc_lld_calibrate(ADCDriver *adcp) {
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while ((adcp->adcm->CR & ADC_CR_ADCAL) != 0U)
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;
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#if STM32_ADC_DUAL_MODE
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if (&ADCD1 == adcp) {
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osalDbgAssert(adcp->adcs->CR == ADC_CR_ADVREGEN, "invalid register state");
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adcp->adcs->CR &= ~(ADC_CR_ADCALDIF | ADC_CR_ADCALLIN);
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@ -168,6 +181,7 @@ static void adc_lld_calibrate(ADCDriver *adcp) {
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adcp->adcs->CR |= ADC_CR_ADCAL;
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while ((adcp->adcs->CR & ADC_CR_ADCAL) != 0U)
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;
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}
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#endif
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}
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@ -186,6 +200,7 @@ static void adc_lld_stop_adc(ADCDriver *adcp) {
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adcp->adcm->PCSEL = 0U;
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}
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#if (STM32_ADC_USE_ADC12 == TRUE) || defined(__DOXYGEN__)
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/**
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* @brief ADC DMA service routine.
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*
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@ -215,7 +230,9 @@ static void adc_lld_serve_dma_interrupt(ADCDriver *adcp, uint32_t flags) {
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}
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}
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}
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#endif /* STM32_ADC_USE_ADC12 == TRUE */
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#if (STM32_ADC_USE_ADC3 == TRUE) || defined(__DOXYGEN__)
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/**
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* @brief ADC BDMA service routine.
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*
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@ -245,6 +262,7 @@ static void adc_lld_serve_bdma_interrupt(ADCDriver *adcp, uint32_t flags) {
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}
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}
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}
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#endif /* STM32_ADC_USE_ADC3 == TRUE */
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/**
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* @brief ADC IRQ service routine.
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@ -295,11 +313,11 @@ OSAL_IRQ_HANDLER(STM32_ADC12_HANDLER) {
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OSAL_IRQ_PROLOGUE();
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isr = ADC1->ISR;
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#if STM32_ADC_DUAL_MODE == TRUE
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#if STM32_ADC_DUAL_MODE
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isr |= ADC2->ISR;
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#endif
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ADC1->ISR = isr;
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#if STM32_ADC_DUAL_MODE == TRUE
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#if STM32_ADC_DUAL_MODE
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ADC2->ISR = isr;
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#endif
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#if defined(STM32_ADC_ADC12_IRQ_HOOK)
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@ -353,7 +371,7 @@ void adc_lld_init(void) {
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ADCD1.adcs = ADC2;
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#endif
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ADCD1.data.dma = NULL;
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ADCD1.dmamode = ADC_DMA_SIZE |
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ADCD1.dmamode = ADC12_DMA_SIZE |
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STM32_DMA_CR_PL(STM32_ADC_ADC12_DMA_PRIORITY) |
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STM32_DMA_CR_DIR_P2M |
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STM32_DMA_CR_MINC | STM32_DMA_CR_TCIE |
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@ -367,11 +385,11 @@ void adc_lld_init(void) {
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ADCD3.adcc = ADC3_COMMON;
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ADCD3.adcm = ADC3;
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ADCD3.data.bdma = NULL;
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ADCD3.dmamode = ADC_DMA_SIZE |
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STM32_DMA_CR_PL(STM32_ADC_ADC3_DMA_PRIORITY) |
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STM32_DMA_CR_DIR_P2M |
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STM32_DMA_CR_MINC | STM32_DMA_CR_TCIE |
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STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE;
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ADCD3.dmamode = ADC3_BDMA_SIZE |
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STM32_BDMA_CR_PL(STM32_ADC_ADC3_DMA_PRIORITY) |
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STM32_BDMA_CR_DIR_P2M |
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STM32_BDMA_CR_MINC | STM32_BDMA_CR_TCIE |
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STM32_BDMA_CR_TEIE;
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nvicEnableVector(STM32_ADC3_NUMBER, STM32_ADC_ADC3_IRQ_PRIORITY);
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#endif /* STM32_ADC_USE_ADC3 == TRUE */
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@ -386,7 +404,7 @@ void adc_lld_init(void) {
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#if STM32_ADC_USE_ADC3 == TRUE
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rccEnableADC3(true);
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rccResetADC3();
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ADC3_COMMON->CCR = STM32_ADC_ADC3_CLOCK_MODE | ADC_DMA_DAMDF;
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ADC3_COMMON->CCR = STM32_ADC_ADC3_CLOCK_MODE;
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rccDisableADC3();
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#endif
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#endif
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@ -417,6 +435,21 @@ void adc_lld_start(ADCDriver *adcp) {
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osalDbgAssert(adcp->data.dma != NULL, "unable to allocate stream");
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rccEnableADC12(true);
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dmaSetRequestSource(adcp->data.dma, STM32_DMAMUX1_ADC1);
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/* Setting DMA peripheral-side pointer.*/
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#if STM32_ADC_DUAL_MODE
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dmaStreamSetPeripheral(adcp->data.dma, &adcp->adcc->CDR);
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#else
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dmaStreamSetPeripheral(adcp->data.dma, &adcp->adcm->DR);
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#endif
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/* Differential channels setting.*/
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#if STM32_ADC_DUAL_MODE
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adcp->adcm->DIFSEL = adcp->config->difsel;
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adcp->adcs->DIFSEL = adcp->config->difsel;
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#else
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adcp->adcm->DIFSEL = adcp->config->difsel;
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#endif
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}
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#endif /* STM32_ADC_USE_ADC12 == TRUE */
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@ -429,28 +462,35 @@ void adc_lld_start(ADCDriver *adcp) {
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osalDbgAssert(adcp->data.bdma != NULL, "unable to allocate stream");
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rccEnableADC3(true);
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bdmaSetRequestSource(adcp->data.bdma, STM32_DMAMUX2_ADC3_REQ);
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}
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#endif /* STM32_ADC_USE_ADC3 == TRUE */
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/* Setting DMA peripheral-side pointer.*/
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#if STM32_ADC_DUAL_MODE == TRUE
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dmaStreamSetPeripheral(adcp->data.dma, &adcp->adcc->CDR);
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#else
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dmaStreamSetPeripheral(adcp->data.dma, &adcp->adcm->DR);
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#endif
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bdmaStreamSetPeripheral(adcp->data.bdma, &adcp->adcm->DR);
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/* Differential channels setting.*/
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#if STM32_ADC_DUAL_MODE == TRUE
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adcp->adcm->DIFSEL = adcp->config->difsel;
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adcp->adcs->DIFSEL = adcp->config->difsel;
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#else
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adcp->adcm->DIFSEL = adcp->config->difsel;
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#endif
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}
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#endif /* STM32_ADC_USE_ADC3 == TRUE */
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/* Master ADC calibration.*/
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adc_lld_vreg_on(adcp);
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adc_lld_calibrate(adcp);
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/* Configure the ADC boost. */
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#if STM32_ADC_USE_ADC12 == TRUE
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if (&ADCD1 == adcp) {
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adcp->adcm->CR |= STM32_ADC12_BOOST;
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#if STM32_ADC_DUAL_MODE
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adcp->adcs->CR |= STM32_ADC12_BOOST;
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#endif
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}
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#endif
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#if STM32_ADC_USE_ADC3 == TRUE
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if (&ADCD3 == adcp) {
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adcp->adcm->CR |= STM32_ADC3_BOOST;
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}
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#endif
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/* Master ADC enabled here in order to reduce conversions latencies.*/
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adc_lld_analog_on(adcp);
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}
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@ -496,7 +536,7 @@ void adc_lld_stop(ADCDriver *adcp) {
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adcp->data.bdma = NULL;
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/* Resetting CCR options except default ones.*/
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adcp->adcc->CCR = STM32_ADC_ADC3_CLOCK_MODE | ADC_DMA_DAMDF;
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adcp->adcc->CCR = STM32_ADC_ADC3_CLOCK_MODE;
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rccDisableADC3();
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}
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#endif
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@ -513,12 +553,17 @@ void adc_lld_stop(ADCDriver *adcp) {
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void adc_lld_start_conversion(ADCDriver *adcp) {
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uint32_t dmamode, cfgr;
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const ADCConversionGroup *grpp = adcp->grpp;
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#if STM32_ADC_DUAL_MODE
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uint32_t ccr = grpp->ccr & ~(ADC_CCR_CKMODE_MASK | ADC_CCR_DUAL_MASK);
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#endif
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#if STM32_ADC_USE_ADC12 == TRUE
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#if STM32_ADC_DUAL_MODE
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uint32_t ccr;
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#endif
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if (&ADCD1 == adcp) {
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#if STM32_ADC_DUAL_MODE
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ccr = grpp->ccr & ~(ADC_CCR_CKMODE_MASK | ADC_CCR_DAMDF_MASK);
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osalDbgAssert(!STM32_ADC_DUAL_MODE || ((grpp->num_channels & 1) == 0),
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"odd number of channels in dual mode");
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#endif
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/* Calculating control registers values.*/
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dmamode = adcp->dmamode;
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@ -530,10 +575,10 @@ void adc_lld_start_conversion(ADCDriver *adcp) {
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is enabled in order to allow streaming processing.*/
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dmamode |= STM32_DMA_CR_HTIE;
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}
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}
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else {
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cfgr = grpp->cfgr | ADC_CFGR_DMNGT_ONESHOT;
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}
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}
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/* DMA setup.*/
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dmaStreamSetMemory0(adcp->data.dma, adcp->samples);
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@ -546,18 +591,47 @@ void adc_lld_start_conversion(ADCDriver *adcp) {
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#endif
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dmaStreamSetMode(adcp->data.dma, dmamode);
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dmaStreamEnable(adcp->data.dma);
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}
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#endif /* STM32_ADC_USE_ADC12 == TRUE */
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#if STM32_ADC_USE_ADC3 == TRUE
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if (&ADCD3 == adcp) {
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/* Calculating control registers values.*/
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dmamode = adcp->dmamode;
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if (grpp->circular) {
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dmamode |= STM32_BDMA_CR_CIRC;
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cfgr = grpp->cfgr | ADC_CFGR_DMNGT_CIRCULAR;
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if (adcp->depth > 1) {
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/* If circular buffer depth > 1, then the half transfer interrupt
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is enabled in order to allow streaming processing.*/
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dmamode |= STM32_BDMA_CR_HTIE;
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}
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}
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else {
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cfgr = grpp->cfgr | ADC_CFGR_DMNGT_ONESHOT;
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}
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/* DMA setup.*/
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bdmaStreamSetMemory(adcp->data.bdma, adcp->samples);
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bdmaStreamSetTransactionSize(adcp->data.bdma, (uint32_t)grpp->num_channels *
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(uint32_t)adcp->depth);
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bdmaStreamSetMode(adcp->data.bdma, dmamode);
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bdmaStreamEnable(adcp->data.bdma);
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}
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#endif /* STM32_ADC_USE_ADC3 == TRUE */
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/* ADC setup, if it is defined a callback for the analog watch dog then it
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is enabled.*/
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adcp->adcm->ISR = adcp->adcm->ISR;
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adcp->adcm->IER = ADC_IER_OVRIE | ADC_IER_AWD1IE;
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#if STM32_ADC_DUAL_MODE
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#if STM32_ADC_DUAL_MODE == TRUE && STM32_ADC_USE_ADC12 == TRUE
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/* Configuration for dual mode ADC12 */
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if (&ADCD1 == adcp) {
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/* Configuring the CCR register with the user-specified settings
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in the conversion group configuration structure, static settings are
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preserved.*/
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adcp->adcc->CCR = (adcp->adcc->CCR &
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(ADC_CCR_CKMODE_MASK | ADC_CCR_DUAL_MASK)) | ccr;
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(ADC_CCR_CKMODE_MASK | ADC_CCR_DAMDF_MASK)) | ccr;
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adcp->adcm->CFGR2 = grpp->cfgr2;
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adcp->adcm->PCSEL = grpp->pcsel;
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@ -591,8 +665,16 @@ void adc_lld_start_conversion(ADCDriver *adcp) {
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/* ADC configuration.*/
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adcp->adcm->CFGR = cfgr;
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adcp->adcs->CFGR = cfgr;
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}
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#else /* !STM32_ADC_DUAL_MODE */
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#endif /* STM32_ADC_DUAL_MODE == TRUE && STM32_ADC_USE_ADC12 == TRUE */
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#if STM32_ADC_DUAL_MODE == FALSE || STM32_ADC_USE_ADC3 == TRUE
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/* Configuration for ADC3 and single mode ADC1 */
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#if STM32_ADC_DUAL_MODE == TRUE && STM32_ADC_USE_ADC3 == TRUE
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if (&ADCD3 == adcp)
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#endif
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{
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adcp->adcm->CFGR2 = grpp->cfgr2;
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adcp->adcm->PCSEL = grpp->pcsel;
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adcp->adcm->LTR1 = grpp->ltr1;
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@ -610,7 +692,8 @@ void adc_lld_start_conversion(ADCDriver *adcp) {
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/* ADC configuration.*/
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adcp->adcm->CFGR = cfgr;
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#endif /* !STM32_ADC_DUAL_MODE */
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}
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#endif
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/* Starting conversion.*/
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adcp->adcm->CR |= ADC_CR_ADSTART;
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@ -625,7 +708,18 @@ void adc_lld_start_conversion(ADCDriver *adcp) {
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*/
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void adc_lld_stop_conversion(ADCDriver *adcp) {
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#if STM32_ADC_USE_ADC12 == TRUE
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if (&ADCD1 == adcp) {
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dmaStreamDisable(adcp->data.dma);
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}
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#endif /* STM32_ADC_USE_ADC12 == TRUE */
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#if STM32_ADC_USE_ADC3 == TRUE
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if (&ADCD3 == adcp) {
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bdmaStreamDisable(adcp->data.bdma);
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}
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#endif /* STM32_ADC_USE_ADC12 == TRUE */
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|
||||
adc_lld_stop_adc(adcp);
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -54,6 +54,7 @@
|
|||
#define ADC_CHANNEL_IN16 16U /**< @brief External analog input 16. */
|
||||
#define ADC_CHANNEL_IN17 17U /**< @brief External analog input 17. */
|
||||
#define ADC_CHANNEL_IN18 18U /**< @brief External analog input 18. */
|
||||
#define ADC_CHANNEL_IN19 19U /**< @brief External analog input 19. */
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
|
|
@ -79,6 +80,7 @@
|
|||
#define ADC_SELMASK_IN16 (1U << ADC_CHANNEL_IN16)
|
||||
#define ADC_SELMASK_IN17 (1U << ADC_CHANNEL_IN17)
|
||||
#define ADC_SELMASK_IN18 (1U << ADC_CHANNEL_IN18)
|
||||
#define ADC_SELMASK_IN19 (1U << ADC_CHANNEL_IN19)
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
|
|
@ -109,10 +111,16 @@
|
|||
|
||||
#define ADC_CFGR_RES_MASK (7U << 2U)
|
||||
#define ADC_CFGR_RES_16BITS (0U << 2U)
|
||||
#define ADC_CFGR_RES_10BITS (3U << 2U)
|
||||
#if !defined(STM32_ENFORCE_H7_REV_XY)
|
||||
#define ADC_CFGR_RES_14BITS (5U << 2U)
|
||||
#define ADC_CFGR_RES_12BITS (6U << 2U)
|
||||
#define ADC_CFGR_RES_8BITS (7U << 2U)
|
||||
#else
|
||||
#define ADC_CFGR_RES_14BITS (1U << 2U)
|
||||
#define ADC_CFGR_RES_12BITS (2U << 2U)
|
||||
#define ADC_CFGR_RES_10BITS (3U << 2U)
|
||||
#define ADC_CFGR_RES_8BITS (4U << 2U)
|
||||
#endif
|
||||
|
||||
#define ADC_CFGR_EXTSEL_MASK (15U << 5U)
|
||||
#define ADC_CFGR_EXTSEL_SRC(n) ((n) << 5U)
|
||||
|
|
@ -137,12 +145,20 @@
|
|||
*/
|
||||
#define ADC_CCR_DUAL_MASK (31U << 0U)
|
||||
#define ADC_CCR_DUAL_FIELD(n) ((n) << 0U)
|
||||
#define ADC_CCR_DUAL_INDEPENDENT (0U << 0U) /**< @brief Independent, dual mode disabled. */
|
||||
#define ADC_CCR_DUAL_REG_SIMULT (6U << 0U) /**< @brief Regular simultaneous. */
|
||||
#define ADC_CCR_DUAL_REG_INTERL (7U << 0U) /**< @brief Regular interleaved. */
|
||||
#define ADC_CCR_DUAL_INJ_SIMULT (5U << 0U) /**< @brief Injected simultaneous. */
|
||||
#define ADC_CCR_DUAL_INJ_ALTERNATE (9U << 0U) /**< @brief Injected alternate trigger. */
|
||||
#define ADC_CCR_DUAL_REG_SIM_INJ_SIM (1U << 0U) /**< @brief Combined regular simultaneous + injected simultaneous. */
|
||||
#define ADC_CCR_DUAL_REG_SIM_INJ_ALT (2U << 0U) /**< @brief Combined regular simultaneous + injected alternate trigger. */
|
||||
#define ADC_CCR_DUAL_REG_INT_INJ_SIM (3U << 0U) /**< @brief Combined regular interleaved + injected simultaneous. */
|
||||
#define ADC_CCR_DELAY_MASK (15U << 8U)
|
||||
#define ADC_CCR_DELAY_FIELD(n) ((n) << 8U)
|
||||
#define ADC_CCR_DAMDF_MASK (3U << 14U)
|
||||
#define ADC_CCR_DAMDF_DISABLED (0U << 14U)
|
||||
#define ADC_CCR_DAMDF_HWORD (2U << 14U)
|
||||
#define ADC_CCR_DAMDF_WORD (3U << 14U)
|
||||
#define ADC_CCR_DAMDF_BYTE (3U << 14U)
|
||||
#define ADC_CCR_CKMODE_MASK (3U << 16U)
|
||||
#define ADC_CCR_CKMODE_ADCCK (0U << 16U)
|
||||
#define ADC_CCR_CKMODE_AHB_DIV1 (1U << 16U)
|
||||
|
|
@ -294,6 +310,11 @@
|
|||
#error "ADC driver activated but no ADC peripheral assigned"
|
||||
#endif
|
||||
|
||||
/* Dual mode is only supported with ADC12.*/
|
||||
#if !STM32_ADC_USE_ADC12 && STM32_ADC_DUAL_MODE
|
||||
#error "STM32_ADC_DUAL_MODE only supported with ADC12"
|
||||
#endif
|
||||
|
||||
/* Check on the presence of the DMA streams settings in mcuconf.h.*/
|
||||
#if STM32_ADC_USE_ADC12 && !defined(STM32_ADC_ADC12_DMA_STREAM)
|
||||
#error "STM32_ADC_ADC12_DMA_STREAM not defined"
|
||||
|
|
@ -336,7 +357,42 @@
|
|||
#error "Invalid IRQ priority assigned to ADC3"
|
||||
#endif
|
||||
|
||||
#if !defined(STM32_ENFORCE_H7_REV_XY)
|
||||
/* ADC clock source checks.*/
|
||||
#if (STM32_D1HPRE == STM32_D1HPRE_DIV1)
|
||||
#define STM32_ADC_SCLK STM32_HCLK
|
||||
#else
|
||||
#define STM32_ADC_SCLK (STM32_HCLK / 2)
|
||||
#endif
|
||||
|
||||
#if STM32_ADC_ADC12_CLOCK_MODE == ADC_CCR_CKMODE_ADCCK
|
||||
/* CHTODO: also check ADC_CCR_PRESC.*/
|
||||
#define STM32_ADC12_CLOCK (STM32_ADCCLK / 2)
|
||||
#elif STM32_ADC_ADC12_CLOCK_MODE == ADC_CCR_CKMODE_AHB_DIV1
|
||||
#define STM32_ADC12_CLOCK (STM32_ADC_SCLK / 1 / 2)
|
||||
#elif STM32_ADC_ADC12_CLOCK_MODE == ADC_CCR_CKMODE_AHB_DIV2
|
||||
#define STM32_ADC12_CLOCK (STM32_ADC_SCLK / 2 / 2)
|
||||
#elif STM32_ADC_ADC12_CLOCK_MODE == ADC_CCR_CKMODE_AHB_DIV4
|
||||
#define STM32_ADC12_CLOCK (STM32_ADC_SCLK / 4 / 2)
|
||||
#else
|
||||
#error "invalid clock mode selected for STM32_ADC_ADC12_CLOCK_MODE"
|
||||
#endif
|
||||
|
||||
#if STM32_ADC_ADC3_CLOCK_MODE == ADC_CCR_CKMODE_ADCCK
|
||||
/* CHTODO: also check ADC_CCR_PRESC.*/
|
||||
#define STM32_ADC3_CLOCK (STM32_ADCCLK / 2)
|
||||
#elif STM32_ADC_ADC3_CLOCK_MODE == ADC_CCR_CKMODE_AHB_DIV1
|
||||
#define STM32_ADC3_CLOCK (STM32_ADC_SCLK / 1 / 2)
|
||||
#elif STM32_ADC_ADC3_CLOCK_MODE == ADC_CCR_CKMODE_AHB_DIV2
|
||||
#define STM32_ADC3_CLOCK (STM32_ADC_SCLK / 2 / 2)
|
||||
#elif STM32_ADC_ADC3_CLOCK_MODE == ADC_CCR_CKMODE_AHB_DIV4
|
||||
#define STM32_ADC3_CLOCK (STM32_ADC_SCLK / 4 / 2)
|
||||
#else
|
||||
#error "invalid clock mode selected for STM32_ADC_ADC3_CLOCK_MODE"
|
||||
#endif
|
||||
|
||||
#else /* defined(STM32_ENFORCE_H7_REV_XY) */
|
||||
|
||||
#if STM32_ADC_ADC12_CLOCK_MODE == ADC_CCR_CKMODE_ADCCK
|
||||
#define STM32_ADC12_CLOCK STM32_ADCCLK
|
||||
#elif STM32_ADC_ADC12_CLOCK_MODE == ADC_CCR_CKMODE_AHB_DIV1
|
||||
|
|
@ -361,6 +417,8 @@
|
|||
#error "invalid clock mode selected for STM32_ADC_ADC3_CLOCK_MODE"
|
||||
#endif
|
||||
|
||||
#endif /* defined(STM32_ENFORCE_H7_REV_XY) */
|
||||
|
||||
#if STM32_ADC12_CLOCK > STM32_ADCCLK_MAX
|
||||
#error "STM32_ADC12_CLOCK exceeding maximum frequency (STM32_ADCCLK_MAX)"
|
||||
#endif
|
||||
|
|
@ -369,6 +427,44 @@
|
|||
#error "STM32_ADC3_CLOCK exceeding maximum frequency (STM32_ADCCLK_MAX)"
|
||||
#endif
|
||||
|
||||
#if !defined(STM32_ENFORCE_H7_REV_XY)
|
||||
/* ADC boost checks.*/
|
||||
#if STM32_ADC12_CLOCK > 6250000
|
||||
#define STM32_ADC12_BOOST (1U << 8U)
|
||||
#elif STM32_ADC12_CLOCK > 12500000
|
||||
#define STM32_ADC12_BOOST (2U << 8U)
|
||||
#elif STM32_ADC12_CLOCK > 25000000
|
||||
#define STM32_ADC12_BOOST (3U << 8U)
|
||||
#else
|
||||
#define STM32_ADC12_BOOST (0U << 8U)
|
||||
#endif
|
||||
|
||||
#if STM32_ADC3_CLOCK > 6250000
|
||||
#define STM32_ADC3_BOOST (1U << 8U)
|
||||
#elif STM32_ADC3_CLOCK > 12500000
|
||||
#define STM32_ADC3_BOOST (2U << 8U)
|
||||
#elif STM32_ADC3_CLOCK > 25000000
|
||||
#define STM32_ADC3_BOOST (3U << 8U)
|
||||
#else
|
||||
#define STM32_ADC3_BOOST (0U << 8U)
|
||||
#endif
|
||||
|
||||
#else /* defined(STM32_ENFORCE_H7_REV_XY) */
|
||||
|
||||
#if STM32_ADC12_CLOCK > 20000000
|
||||
#define STM32_ADC12_BOOST (1U << 8U)
|
||||
#else
|
||||
#define STM32_ADC12_BOOST (0U << 8U)
|
||||
#endif
|
||||
|
||||
#if STM32_ADC3_CLOCK > 20000000
|
||||
#define STM32_ADC3_BOOST (1U << 8U)
|
||||
#else
|
||||
#define STM32_ADC3_BOOST (0U << 8U)
|
||||
#endif
|
||||
|
||||
#endif /* defined(STM32_ENFORCE_H7_REV_XY) */
|
||||
|
||||
#if !defined(STM32_DMA_REQUIRED)
|
||||
#define STM32_DMA_REQUIRED
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -131,9 +131,9 @@
|
|||
* @name Status flags passed to the ISR callbacks
|
||||
* @{
|
||||
*/
|
||||
#define STM32_BDMA_ISR_TEIF BDMA_ISR_TEIF1
|
||||
#define STM32_BDMA_ISR_HTIF BDMA_ISR_HTIF1
|
||||
#define STM32_BDMA_ISR_TCIF BDMA_ISR_TCIF1
|
||||
#define STM32_BDMA_ISR_TEIF BDMA_ISR_TEIF0
|
||||
#define STM32_BDMA_ISR_HTIF BDMA_ISR_HTIF0
|
||||
#define STM32_BDMA_ISR_TCIF BDMA_ISR_TCIF0
|
||||
/** @} */
|
||||
|
||||
/*===========================================================================*/
|
||||
|
|
@ -272,15 +272,9 @@ typedef struct {
|
|||
*
|
||||
* @special
|
||||
*/
|
||||
#if !defined(STM32_ENFORCE_H7_REV_XY) || defined(__DOXYGEN__)
|
||||
#define bdmaStreamSetMemory(stp, addr) { \
|
||||
(stp)->channel->CM0AR = (uint32_t)(addr); \
|
||||
}
|
||||
#else
|
||||
#define bdmaStreamSetMemory(stp, addr) { \
|
||||
(stp)->channel->CMAR = (uint32_t)(addr); \
|
||||
}
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Sets the number of transfers to be performed.
|
||||
|
|
|
|||
|
|
@ -212,7 +212,7 @@
|
|||
/**
|
||||
* @brief Maximum ADC clock frequency.
|
||||
*/
|
||||
#define STM32_ADCCLK_MAX 100000000
|
||||
#define STM32_ADCCLK_MAX 50000000
|
||||
/** @} */
|
||||
|
||||
#else /* defined(STM32_ENFORCE_H7_REV_XY) */
|
||||
|
|
|
|||
|
|
@ -285,4 +285,5 @@
|
|||
<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="org.eclipse.cdt.make.core.GCCStandardMakePerProjectProfile"/>
|
||||
</scannerConfigBuildInfo>
|
||||
</storageModule>
|
||||
<storageModule moduleId="org.eclipse.cdt.make.core.buildtargets"/>
|
||||
</cproject>
|
||||
|
|
|
|||
Loading…
Reference in New Issue