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git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@4977 35acf78f-673a-0410-8e92-d51de3d6d3f4

This commit is contained in:
gdisirio 2012-12-27 11:31:57 +00:00
parent 1c4914bb0d
commit d2c0aea892
6 changed files with 274 additions and 110 deletions
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226
os/hal/platforms/STM32F3xx/adc_lld.c
View File

@ -57,18 +57,107 @@ ADCDriver ADCD3;
/* Driver local functions. */
/*===========================================================================*/
/**
* @brief Enables the ADC voltage regulator.
*
* @param[in] adcp pointer to the @p ADCDriver object
*/
static void adc_lld_vreg_on(ADCDriver *adcp) {
adcp->adcm->CR = ADC_CR_ADVREGEN_0;
#if STM32_ADC_DUAL_MODE
adcp->adcs->CR = ADC_CR_ADVREGEN_0;
#endif
halPolledDelay(US2RTT(10));
}
/**
* @brief Disables the ADC voltage regulator.
*
* @param[in] adcp pointer to the @p ADCDriver object
*/
static void adc_lld_vreg_off(ADCDriver *adcp) {
adcp->adcm->CR = ADC_CR_ADVREGEN_1;
#if STM32_ADC_DUAL_MODE
adcp->adcs->CR = ADC_CR_ADVREGEN_1;
#endif
}
/**
* @brief Enables the ADC analog circuit.
*
* @param[in] adcp pointer to the @p ADCDriver object
*/
static void adc_lld_analog_on(ADCDriver *adcp) {
adcp->adcm->CR = ADC_CR_ADEN;
while ((adcp->adcm->ISR & ADC_ISR_ADRDY) == 0)
;
#if STM32_ADC_DUAL_MODE
adcp->adcs->CR = ADC_CR_ADEN;
while ((adcp->adcs->ISR & ADC_ISR_ADRDY) == 0)
;
#endif
}
/**
* @brief Disables the ADC analog circuit.
*
* @param[in] adcp pointer to the @p ADCDriver object
*/
static void adc_lld_analog_off(ADCDriver *adcp) {
adcp->adcm->CR = ADC_CR_ADDIS;
while ((adcp->adcm->CR & ADC_CR_ADDIS) != 0)
;
#if STM32_ADC_DUAL_MODE
adcp->adcs->CR = ADC_CR_ADDIS;
while ((adcp->adcs->CR & ADC_CR_ADDIS) != 0)
;
#endif
}
/**
* @brief Calibrates and ADC unit.
*
* @param[in] adcp pointer to the @p ADCDriver object
*/
static void adc_lld_calibrate(ADCDriver *adcp) {
chDbgAssert(adcp->adcm->CR == 0, "adc_lld_calibrate(), #1",
"invalid register state");
adcp->adcm->CR |= ADC_CR_ADCAL;
while ((adcp->adcm->CR & ADC_CR_ADCAL) != 0)
;
#if STM32_ADC_DUAL_MODE
chDbgAssert(adcp->adcs->CR == 0, "adc_lld_calibrate(), #2",
"invalid register state");
adcp->adcs->CR |= ADC_CR_ADCAL;
while ((adcp->adcs->CR & ADC_CR_ADCAL) != 0)
;
#endif
}
/**
* @brief Stops an ongoing conversion, if any.
*
* @param[in] adc pointer to the ADC registers block
* @param[in] adcp pointer to the @p ADCDriver object
*/
static void adc_lld_stop_adc(ADC_TypeDef *adc) {
static void adc_lld_stop_adc(ADCDriver *adcp) {
if (adc->CR & ADC_CR_ADSTART) {
adc->CR |= ADC_CR_ADSTP;
while (adc->CR & ADC_CR_ADSTP)
if (adcp->adcm->CR & ADC_CR_ADSTART) {
adcp->adcm->CR |= ADC_CR_ADSTP;
while (adcp->adcm->CR & ADC_CR_ADSTP)
;
}
#if STM32_ADC_DUAL_MODE
if (adcp->adcs->CR & ADC_CR_ADSTART) {
adcp->adcs->CR |= ADC_CR_ADSTP;
while (adcp->adcs->CR & ADC_CR_ADSTP)
;
}
#endif
}
/**
@ -120,9 +209,17 @@ static void adc_lld_serve_interrupt(ADCDriver *adcp, uint32_t isr) {
to read data fast enough.*/
_adc_isr_error_code(adcp, ADC_ERR_OVERFLOW);
}
if (isr & ADC_ISR_AWD) {
if (isr & ADC_ISR_AWD1) {
/* Analog watchdog error.*/
_adc_isr_error_code(adcp, ADC_ERR_AWD);
_adc_isr_error_code(adcp, ADC_ERR_AWD1);
}
if (isr & ADC_ISR_AWD2) {
/* Analog watchdog error.*/
_adc_isr_error_code(adcp, ADC_ERR_AWD2);
}
if (isr & ADC_ISR_AWD3) {
/* Analog watchdog error.*/
_adc_isr_error_code(adcp, ADC_ERR_AWD3);
}
}
}
@ -212,27 +309,40 @@ void adc_lld_init(void) {
#if STM32_ADC_USE_ADC1
/* Driver initialization.*/
adcObjectInit(&ADCD1);
ADCD1.adc = ADC1;
ADCD1.adcm = ADC1;
#if STM32_ADC_DUAL_MODE
ADCD1.adcs = ADC2;
#endif
ADCD1.dmastp = STM32_DMA1_STREAM1;
ADCD1.dmamode = STM32_DMA_CR_PL(STM32_ADC_ADC1_DMA_PRIORITY) |
ADCD1.dmamode = STM32_DMA_CR_PL(STM32_ADC_ADC12_DMA_PRIORITY) |
STM32_DMA_CR_DIR_P2M |
STM32_DMA_CR_MSIZE_HWORD | STM32_DMA_CR_PSIZE_HWORD |
STM32_DMA_CR_MINC | STM32_DMA_CR_TCIE |
STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE;
nvicEnableVector(ADC1_2_IRQn,
CORTEX_PRIORITY_MASK(STM32_ADC_ADC12_IRQ_PRIORITY));
#endif /* STM32_ADC_USE_ADC1 */
#if STM32_ADC_USE_ADC3
/* Driver initialization.*/
adcObjectInit(&ADCD1);
ADCD3.adcm = ADC3;
#if STM32_ADC_DUAL_MODE
ADCD3.adcs = ADC4;
#endif
/* The shared vector is initialized on driver initialization and never
disabled.*/
nvicEnableVector(ADC1_COMP_IRQn,
CORTEX_PRIORITY_MASK(STM32_ADC_IRQ_PRIORITY));
/* Calibration procedure.*/
rccEnableADC1(FALSE);
chDbgAssert(ADC1->CR == 0, "adc_lld_init(), #1", "invalid register state");
ADC1->CR |= ADC_CR_ADCAL;
while (ADC1->CR & ADC_CR_ADCAL)
;
rccDisableADC1(FALSE);
ADCD3.dmastp = STM32_DMA2_STREAM5;
ADCD3.dmamode = STM32_DMA_CR_PL(STM32_ADC_ADC12_DMA_PRIORITY) |
STM32_DMA_CR_DIR_P2M |
STM32_DMA_CR_MSIZE_HWORD | STM32_DMA_CR_PSIZE_HWORD |
STM32_DMA_CR_MINC | STM32_DMA_CR_TCIE |
STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE;
nvicEnableVector(ADC3_IRQn,
CORTEX_PRIORITY_MASK(STM32_ADC_ADC34_IRQ_PRIORITY));
#if STM32_ADC_DUAL_MODE
nvicEnableVector(ADC4_IRQn,
CORTEX_PRIORITY_MASK(STM32_ADC_ADC34_IRQ_PRIORITY));
#endif
#endif /* STM32_ADC_USE_ADC3 */
}
/**
@ -250,30 +360,48 @@ void adc_lld_start(ADCDriver *adcp) {
if (&ADCD1 == adcp) {
bool_t b;
b = dmaStreamAllocate(adcp->dmastp,
STM32_ADC_ADC1_DMA_IRQ_PRIORITY,
STM32_ADC_ADC12_DMA_IRQ_PRIORITY,
(stm32_dmaisr_t)adc_lld_serve_dma_interrupt,
(void *)adcp);
chDbgAssert(!b, "adc_lld_start(), #1", "stream already allocated");
#if STM32_ADC_DUAL_MODE
dmaStreamSetPeripheral(adcp->dmastp, &ADC1_2->CDR);
#else
dmaStreamSetPeripheral(adcp->dmastp, &ADC1->DR);
rccEnableADC1(FALSE);
#if STM32_ADCSW == STM32_ADCSW_HSI14
/* Clock from HSI14, no need for jitter removal.*/
ADC1->CFGR2 = 0x00001000;
#else
#if STM32_ADCPRE == STM32_ADCPRE_DIV2
ADC1->CFGR2 = 0x00001000 | ADC_CFGR2_JITOFFDIV2;
#else
ADC1->CFGR2 = 0x00001000 | ADC_CFGR2_JITOFFDIV4;
#endif
#endif
rccEnableADC12(FALSE);
/* Clock source setting.*/
ADC1_2->CCR = ADC_CCR_CKMODE_AHB_DIV1;
}
#endif /* STM32_ADC_USE_ADC1 */
/* ADC initial setup, starting the analog part here in order to reduce
the latency when starting a conversion.*/
adcp->adc->CR = ADC_CR_ADEN;
while (!(adcp->adc->ISR & ADC_ISR_ADRDY))
;
#if STM32_ADC_USE_ADC3
if (&ADCD3 == adcp) {
bool_t b;
b = dmaStreamAllocate(adcp->dmastp,
STM32_ADC_ADC34_DMA_IRQ_PRIORITY,
(stm32_dmaisr_t)adc_lld_serve_dma_interrupt,
(void *)adcp);
chDbgAssert(!b, "adc_lld_start(), #2", "stream already allocated");
#if STM32_ADC_DUAL_MODE
dmaStreamSetPeripheral(adcp->dmastp, &ADC3_4->CDR);
#else
dmaStreamSetPeripheral(adcp->dmastp, &ADC3->DR);
#endif
rccEnableADC34(FALSE);
/* Clock source setting.*/
ADC3_4->CCR = ADC_CCR_CKMODE_AHB_DIV1;
}
#endif /* STM32_ADC_USE_ADC2 */
/* Master ADC calibration.*/
adc_lld_vreg_on(adcp);
adc_lld_calibrate(adcp);
/* Master ADC enabled here in order to reduce conversions latencies.*/
adc_lld_analog_on(adcp);
}
}
@ -289,19 +417,27 @@ void adc_lld_stop(ADCDriver *adcp) {
/* If in ready state then disables the ADC clock and analog part.*/
if (adcp->state == ADC_READY) {
/* Releasing the associated DMA channel.*/
dmaStreamRelease(adcp->dmastp);
/* Disabling ADC.*/
if (adcp->adc->CR & ADC_CR_ADEN) {
adc_lld_stop_adc(adcp->adc);
adcp->adc->CR |= ADC_CR_ADDIS;
while (adcp->adc->CR & ADC_CR_ADDIS)
;
/* Disabling the ADC.*/
if (adcp->adcm->CR & ADC_CR_ADEN) {
/* Stopping the ongoing conversion, if any.*/
adc_lld_stop_adc(adcp);
/* Disabling ADC analog circuit and regulator.*/
adc_lld_analog_off(adcp);
adc_lld_vreg_off(adcp);
}
#if STM32_ADC_USE_ADC1
if (&ADCD1 == adcp)
rccDisableADC1(FALSE);
rccDisableADC12(FALSE);
#endif
#if STM32_ADC_USE_ADC3
if (&ADCD1 == adcp)
rccDisableADC34(FALSE);
#endif
}
}

96
os/hal/platforms/STM32F3xx/adc_lld.h
View File

@ -118,7 +118,7 @@
#define ADC_CFGR_DISCEN_ENABLED (1 << 16)
#define ADC_CFGR_DISCNUM_MASK (7 << 17)
#define ADC_CFGR_DISCNUM(n) ((n) << 17)
#define ADC_CFGR_DISCNUM_VAL(n) ((n) << 17)
#define ADC_CFGR_AWD1_DISABLED 0
#define ADC_CFGR_AWD1_ALL (1 << 23)
@ -165,57 +165,57 @@
/**
* @brief ADC1/ADC2 DMA priority (0..3|lowest..highest).
*/
#if !defined(STM32_ADC_ADC1_DMA_PRIORITY) || defined(__DOXYGEN__)
#define STM32_ADC_ADC1_DMA_PRIORITY 2
#if !defined(STM32_ADC_ADC12_DMA_PRIORITY) || defined(__DOXYGEN__)
#define STM32_ADC_ADC12_DMA_PRIORITY 2
#endif
/**
* @brief ADC3/ADC4 DMA priority (0..3|lowest..highest).
*/
#if !defined(STM32_ADC_ADC3_DMA_PRIORITY) || defined(__DOXYGEN__)
#define STM32_ADC_ADC3_DMA_PRIORITY 2
#if !defined(STM32_ADC_ADC34_DMA_PRIORITY) || defined(__DOXYGEN__)
#define STM32_ADC_ADC34_DMA_PRIORITY 2
#endif
/**
* @brief ADC1/ADC2 interrupt priority level setting.
*/
#if !defined(STM32_ADC_ADC1_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define STM32_ADC_ADC1_IRQ_PRIORITY 2
#if !defined(STM32_ADC_ADC12_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define STM32_ADC_ADC12_IRQ_PRIORITY 2
#endif
/**
* @brief ADC3/ADC4 interrupt priority level setting.
*/
#if !defined(STM32_ADC3_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define STM32_ADC_ADC3_IRQ_PRIORITY 2
#if !defined(STM32_ADC34_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define STM32_ADC_ADC34_IRQ_PRIORITY 2
#endif
/**
* @brief ADC1/ADC2 DMA interrupt priority level setting.
*/
#if !defined(STM32_ADC_ADC1_DMA_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 2
#if !defined(STM32_ADC_ADC12_DMA_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define STM32_ADC_ADC12_DMA_IRQ_PRIORITY 2
#endif
/**
* @brief ADC3/ADC4 DMA interrupt priority level setting.
*/
#if !defined(STM32_ADC_ADC3_DMA_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define STM32_ADC_ADC3_DMA_IRQ_PRIORITY 2
#if !defined(STM32_ADC_ADC34_DMA_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define STM32_ADC_ADC34_DMA_IRQ_PRIORITY 2
#endif
/**
* @brief ADC1/ADC2 clock source and mode.
*/
#if !defined(STM32_ADC_ADC1_CLOCK_MODE) || defined(__DOXYGEN__)
#define STM32_ADC_ADC1_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV1
#if !defined(STM32_ADC_ADC12_CLOCK_MODE) || defined(__DOXYGEN__)
#define STM32_ADC_ADC12_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV1
#endif
/**
* @brief ADC3/ADC4 clock source and mode.
*/
#if !defined(STM32_ADC_ADC3_CLOCK_MODE) || defined(__DOXYGEN__)
#define STM32_ADC_ADC3_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV1
#if !defined(STM32_ADC_ADC34_CLOCK_MODE) || defined(__DOXYGEN__)
#define STM32_ADC_ADC34_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV1
#endif
/**
@ -238,70 +238,70 @@
#error "ADC3 not present in the selected device"
#endif
#if !STM32_ADC_USE_ADC1 ||!STM32_ADC_USE_ADC3
#if !STM32_ADC_USE_ADC1 && !STM32_ADC_USE_ADC3
#error "ADC driver activated but no ADC peripheral assigned"
#endif
#if STM32_ADC_USE_ADC1 && \
!CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_ADC_ADC1_IRQ_PRIORITY)
!CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_ADC_ADC12_IRQ_PRIORITY)
#error "Invalid IRQ priority assigned to ADC1"
#endif
#if STM32_ADC_USE_ADC1 && \
!CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_ADC_ADC1_DMA_IRQ_PRIORITY)
!CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_ADC_ADC12_DMA_IRQ_PRIORITY)
#error "Invalid IRQ priority assigned to ADC1 DMA"
#endif
#if STM32_ADC_USE_ADC1 && \
!STM32_DMA_IS_VALID_PRIORITY(STM32_ADC_ADC1_DMA_PRIORITY)
!STM32_DMA_IS_VALID_PRIORITY(STM32_ADC_ADC12_DMA_PRIORITY)
#error "Invalid DMA priority assigned to ADC1"
#endif
#if STM32_ADC_USE_ADC3 && \
!CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_ADC_ADC3_IRQ_PRIORITY)
!CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_ADC_ADC34_IRQ_PRIORITY)
#error "Invalid IRQ priority assigned to ADC3"
#endif
#if STM32_ADC_USE_ADC3 && \
!CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_ADC_ADC3_DMA_IRQ_PRIORITY)
!CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_ADC_ADC34_DMA_IRQ_PRIORITY)
#error "Invalid IRQ priority assigned to ADC3 DMA"
#endif
#if STM32_ADC_USE_ADC3 && \
!STM32_DMA_IS_VALID_PRIORITY(STM32_ADC_ADC3_DMA_PRIORITY)
!STM32_DMA_IS_VALID_PRIORITY(STM32_ADC_ADC34_DMA_PRIORITY)
#error "Invalid DMA priority assigned to ADC3"
#endif
#if STM32_ADC_ADC1_CLOCK_MODE == ADC_CCR_CKMODE_ADCCK
#define STM32_ADC1_CLOCK STM32ADC1CLK
#elif STM32_ADC_ADC1_CLOCK_MODE == ADC_CCR_CKMODE_AHB_DIV1
#define STM32_ADC1_CLOCK (STM32_HCLK / 1)
#elif STM32_ADC_ADC1_CLOCK_MODE == ADC_CCR_CKMODE_AHB_DIV2
#define STM32_ADC1_CLOCK (STM32_HCLK / 2)
#elif STM32_ADC_ADC1_CLOCK_MODE == ADC_CCR_CKMODE_AHB_DIV4
#define STM32_ADC1_CLOCK (STM32_HCLK / 4)
#if STM32_ADC_ADC12_CLOCK_MODE == ADC_CCR_CKMODE_ADCCK
#define STM32_ADC12_CLOCK STM32ADC1CLK
#elif STM32_ADC_ADC12_CLOCK_MODE == ADC_CCR_CKMODE_AHB_DIV1
#define STM32_ADC12_CLOCK (STM32_HCLK / 1)
#elif STM32_ADC_ADC12_CLOCK_MODE == ADC_CCR_CKMODE_AHB_DIV2
#define STM32_ADC12_CLOCK (STM32_HCLK / 2)
#elif STM32_ADC_ADC12_CLOCK_MODE == ADC_CCR_CKMODE_AHB_DIV4
#define STM32_ADC12_CLOCK (STM32_HCLK / 4)
#else
#error "invalid clock mode selected for STM32_ADC_ADC1_CLOCK_MODE"
#error "invalid clock mode selected for STM32_ADC_ADC12_CLOCK_MODE"
#endif
#if STM32_ADC_ADC3_CLOCK_MODE == ADC_CCR_CKMODE_ADCCK
#define STM32_ADC3_CLOCK STM32ADC3CLK
#elif STM32_ADC_ADC3_CLOCK_MODE == ADC_CCR_CKMODE_AHB_DIV1
#define STM32_ADC3_CLOCK (STM32_HCLK / 1)
#elif STM32_ADC_ADC3_CLOCK_MODE == ADC_CCR_CKMODE_AHB_DIV2
#define STM32_ADC3_CLOCK (STM32_HCLK / 2)
#elif STM32_ADC_ADC3_CLOCK_MODE == ADC_CCR_CKMODE_AHB_DIV4
#define STM32_ADC3_CLOCK (STM32_HCLK / 4)
#if STM32_ADC_ADC34_CLOCK_MODE == ADC_CCR_CKMODE_ADCCK
#define STM32_ADC34_CLOCK STM32ADC3CLK
#elif STM32_ADC_ADC34_CLOCK_MODE == ADC_CCR_CKMODE_AHB_DIV1
#define STM32_ADC34_CLOCK (STM32_HCLK / 1)
#elif STM32_ADC_ADC34_CLOCK_MODE == ADC_CCR_CKMODE_AHB_DIV2
#define STM32_ADC34_CLOCK (STM32_HCLK / 2)
#elif STM32_ADC_ADC34_CLOCK_MODE == ADC_CCR_CKMODE_AHB_DIV4
#define STM32_ADC34_CLOCK (STM32_HCLK / 4)
#else
#error "invalid clock mode selected for STM32_ADC_ADC1_CLOCK_MODE"
#error "invalid clock mode selected for STM32_ADC_ADC12_CLOCK_MODE"
#endif
#if STM32_ADC1_CLOCK > 72000000
#error "STM32_ADC1_CLOCK exceeding maximum frequency (72000000)"
#if STM32_ADC12_CLOCK > 72000000
#error "STM32_ADC12_CLOCK exceeding maximum frequency (72000000)"
#endif
#if STM32_ADC3_CLOCK > 72000000
#error "STM32_ADC3_CLOCK exceeding maximum frequency (72000000)"
#if STM32_ADC34_CLOCK > 72000000
#error "STM32_ADC34_CLOCK exceeding maximum frequency (72000000)"
#endif
#if !defined(STM32_DMA_REQUIRED)
@ -330,8 +330,8 @@ typedef uint16_t adc_channels_num_t;
typedef enum {
ADC_ERR_DMAFAILURE = 0, /**< DMA operations failure. */
ADC_ERR_OVERFLOW = 1, /**< ADC overflow condition. */
ADC_ERR_AWD1 = 2 /**< Watchdog 1 triggered. */
ADC_ERR_AWD2 = 3 /**< Watchdog 2 triggered. */
ADC_ERR_AWD1 = 2, /**< Watchdog 1 triggered. */
ADC_ERR_AWD2 = 3, /**< Watchdog 2 triggered. */
ADC_ERR_AWD3 = 4 /**< Watchdog 3 triggered. */
} adcerror_t;

1
os/hal/platforms/STM32F3xx/platform.mk
View File

@ -1,6 +1,7 @@
# List of all the STM32F3xx platform files.
PLATFORMSRC = ${CHIBIOS}/os/hal/platforms/STM32F3xx/stm32_dma.c \
${CHIBIOS}/os/hal/platforms/STM32F3xx/hal_lld.c \
${CHIBIOS}/os/hal/platforms/STM32F3xx/adc_lld.c \
${CHIBIOS}/os/hal/platforms/STM32F3xx/ext_lld_isr.c \
${CHIBIOS}/os/hal/platforms/STM32/can_lld.c \
${CHIBIOS}/os/hal/platforms/STM32/ext_lld.c \

37
os/hal/platforms/STM32F3xx/stm32_rcc.h
View File

@ -169,29 +169,54 @@
* @{
*/
/**
* @brief Enables the ADC1 peripheral clock.
* @brief Enables the ADC1/ADC2 peripheral clock.
*
* @param[in] lp low power enable flag
*
* @api
*/
#define rccEnableADC1(lp) rccEnableAPB2(RCC_APB2ENR_ADC1EN, lp)
#define rccEnableADC12(lp) rccEnableAHB(RCC_AHBENR_ADC12EN, lp)
/**
* @brief Disables the ADC1 peripheral clock.
* @brief Disables the ADC1/ADC2 peripheral clock.
*
* @param[in] lp low power enable flag
*
* @api
*/
#define rccDisableADC1(lp) rccDisableAPB2(RCC_APB2ENR_ADC1EN, lp)
#define rccDisableADC12(lp) rccDisableAHB(RCC_AHBENR_ADC12EN, lp)
/**
* @brief Resets the ADC1 peripheral.
* @brief Resets the ADC1/ADC2 peripheral.
*
* @api
*/
#define rccResetADC1() rccResetAPB2(RCC_APB2RSTR_ADC1RST)
#define rccResetADC12() rccResetAHB(RCC_AHBRSTR_ADC12RST)
/**
* @brief Enables the ADC3/ADC4 peripheral clock.
*
* @param[in] lp low power enable flag
*
* @api
*/
#define rccEnableADC34(lp) rccEnableAHB(RCC_AHBENR_ADC34EN, lp)
/**
* @brief Disables the ADC3/ADC4 peripheral clock.
*
* @param[in] lp low power enable flag
*
* @api
*/
#define rccDisableADC34(lp) rccDisableAHB(RCC_AHBENR_ADC34EN, lp)
/**
* @brief Resets the ADC3/ADC4 peripheral.
*
* @api
*/
#define rccResetADC34() rccResetAHB(RCC_AHBRSTR_ADC34RST)
/** @} */
/**

4
os/hal/platforms/STM32F3xx/stm32f30x.h
View File

@ -1031,7 +1031,9 @@ typedef struct
/* */
/******************************************************************************/
/******************** Bit definition for ADC_ISR register ********************/
#define ADC_ISR_ADRD ((uint32_t)0x00000001) /*!< ADC Ready (ADRDY) flag */
/* CHIBIOS FIX */
//#define ADC_ISR_ADRD ((uint32_t)0x00000001) /*!< ADC Ready (ADRDY) flag */
#define ADC_ISR_ADRDY ((uint32_t)0x00000001) /*!< ADC Ready (ADRDY) flag */
#define ADC_ISR_EOSMP ((uint32_t)0x00000002) /*!< ADC End of Sampling flag */
#define ADC_ISR_EOC ((uint32_t)0x00000004) /*!< ADC End of Regular Conversion flag */
#define ADC_ISR_EOS ((uint32_t)0x00000008) /*!< ADC End of Regular sequence of Conversions flag */

20
testhal/STM32F3xx/ADC/mcuconf.h
View File

@ -70,16 +70,16 @@
/*
* ADC driver system settings.
*/
#define STM32_ADC_USE_ADC1 FALSE
#define STM32_ADC_USE_ADC3 FALSE
#define STM32_ADC_ADC1_DMA_PRIORITY 2
#define STM32_ADC_ADC3_DMA_PRIORITY 2
#define STM32_ADC_ADC1_IRQ_PRIORITY 2
#define STM32_ADC_ADC3_IRQ_PRIORITY 2
#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 2
#define STM32_ADC_ADC3_DMA_IRQ_PRIORITY 2
#define STM32_ADC_ADC1_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV1
#define STM32_ADC_ADC3_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV1
#define STM32_ADC_USE_ADC1 TRUE
#define STM32_ADC_USE_ADC3 TRUE
#define STM32_ADC_ADC12_DMA_PRIORITY 2
#define STM32_ADC_ADC34_DMA_PRIORITY 2
#define STM32_ADC_ADC12_IRQ_PRIORITY 2
#define STM32_ADC_ADC34_IRQ_PRIORITY 2
#define STM32_ADC_ADC12_DMA_IRQ_PRIORITY 2
#define STM32_ADC_ADC34_DMA_IRQ_PRIORITY 2
#define STM32_ADC_ADC12_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV1
#define STM32_ADC_ADC34_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV1
#define STM32_ADC_DUAL_MODE FALSE
/*