git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@4977 35acf78f-673a-0410-8e92-d51de3d6d3f4
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@ -57,18 +57,107 @@ ADCDriver ADCD3;
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/* Driver local functions. */
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/* Driver local functions. */
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/*===========================================================================*/
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/*===========================================================================*/
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/**
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* @brief Enables the ADC voltage regulator.
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*
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* @param[in] adcp pointer to the @p ADCDriver object
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*/
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static void adc_lld_vreg_on(ADCDriver *adcp) {
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adcp->adcm->CR = ADC_CR_ADVREGEN_0;
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#if STM32_ADC_DUAL_MODE
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adcp->adcs->CR = ADC_CR_ADVREGEN_0;
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#endif
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halPolledDelay(US2RTT(10));
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}
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/**
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* @brief Disables the ADC voltage regulator.
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*
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* @param[in] adcp pointer to the @p ADCDriver object
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*/
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static void adc_lld_vreg_off(ADCDriver *adcp) {
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adcp->adcm->CR = ADC_CR_ADVREGEN_1;
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#if STM32_ADC_DUAL_MODE
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adcp->adcs->CR = ADC_CR_ADVREGEN_1;
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#endif
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}
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/**
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* @brief Enables the ADC analog circuit.
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*
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* @param[in] adcp pointer to the @p ADCDriver object
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*/
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static void adc_lld_analog_on(ADCDriver *adcp) {
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adcp->adcm->CR = ADC_CR_ADEN;
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while ((adcp->adcm->ISR & ADC_ISR_ADRDY) == 0)
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;
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#if STM32_ADC_DUAL_MODE
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adcp->adcs->CR = ADC_CR_ADEN;
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while ((adcp->adcs->ISR & ADC_ISR_ADRDY) == 0)
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;
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#endif
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}
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/**
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* @brief Disables the ADC analog circuit.
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*
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* @param[in] adcp pointer to the @p ADCDriver object
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*/
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static void adc_lld_analog_off(ADCDriver *adcp) {
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adcp->adcm->CR = ADC_CR_ADDIS;
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while ((adcp->adcm->CR & ADC_CR_ADDIS) != 0)
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;
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#if STM32_ADC_DUAL_MODE
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adcp->adcs->CR = ADC_CR_ADDIS;
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while ((adcp->adcs->CR & ADC_CR_ADDIS) != 0)
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;
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#endif
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}
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/**
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* @brief Calibrates and ADC unit.
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*
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* @param[in] adcp pointer to the @p ADCDriver object
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*/
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static void adc_lld_calibrate(ADCDriver *adcp) {
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chDbgAssert(adcp->adcm->CR == 0, "adc_lld_calibrate(), #1",
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"invalid register state");
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adcp->adcm->CR |= ADC_CR_ADCAL;
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while ((adcp->adcm->CR & ADC_CR_ADCAL) != 0)
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;
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#if STM32_ADC_DUAL_MODE
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chDbgAssert(adcp->adcs->CR == 0, "adc_lld_calibrate(), #2",
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"invalid register state");
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adcp->adcs->CR |= ADC_CR_ADCAL;
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while ((adcp->adcs->CR & ADC_CR_ADCAL) != 0)
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;
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#endif
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}
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/**
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/**
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* @brief Stops an ongoing conversion, if any.
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* @brief Stops an ongoing conversion, if any.
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*
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*
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* @param[in] adc pointer to the ADC registers block
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* @param[in] adcp pointer to the @p ADCDriver object
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*/
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*/
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static void adc_lld_stop_adc(ADC_TypeDef *adc) {
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static void adc_lld_stop_adc(ADCDriver *adcp) {
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if (adc->CR & ADC_CR_ADSTART) {
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if (adcp->adcm->CR & ADC_CR_ADSTART) {
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adc->CR |= ADC_CR_ADSTP;
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adcp->adcm->CR |= ADC_CR_ADSTP;
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while (adc->CR & ADC_CR_ADSTP)
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while (adcp->adcm->CR & ADC_CR_ADSTP)
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;
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;
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}
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}
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#if STM32_ADC_DUAL_MODE
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if (adcp->adcs->CR & ADC_CR_ADSTART) {
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adcp->adcs->CR |= ADC_CR_ADSTP;
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while (adcp->adcs->CR & ADC_CR_ADSTP)
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;
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}
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#endif
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}
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}
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/**
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/**
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@ -120,9 +209,17 @@ static void adc_lld_serve_interrupt(ADCDriver *adcp, uint32_t isr) {
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to read data fast enough.*/
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to read data fast enough.*/
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_adc_isr_error_code(adcp, ADC_ERR_OVERFLOW);
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_adc_isr_error_code(adcp, ADC_ERR_OVERFLOW);
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}
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}
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if (isr & ADC_ISR_AWD) {
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if (isr & ADC_ISR_AWD1) {
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/* Analog watchdog error.*/
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/* Analog watchdog error.*/
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_adc_isr_error_code(adcp, ADC_ERR_AWD);
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_adc_isr_error_code(adcp, ADC_ERR_AWD1);
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}
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if (isr & ADC_ISR_AWD2) {
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/* Analog watchdog error.*/
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_adc_isr_error_code(adcp, ADC_ERR_AWD2);
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}
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if (isr & ADC_ISR_AWD3) {
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/* Analog watchdog error.*/
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_adc_isr_error_code(adcp, ADC_ERR_AWD3);
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}
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}
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}
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}
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}
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}
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@ -212,27 +309,40 @@ void adc_lld_init(void) {
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#if STM32_ADC_USE_ADC1
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#if STM32_ADC_USE_ADC1
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/* Driver initialization.*/
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/* Driver initialization.*/
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adcObjectInit(&ADCD1);
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adcObjectInit(&ADCD1);
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ADCD1.adc = ADC1;
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ADCD1.adcm = ADC1;
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#if STM32_ADC_DUAL_MODE
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ADCD1.adcs = ADC2;
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#endif
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ADCD1.dmastp = STM32_DMA1_STREAM1;
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ADCD1.dmastp = STM32_DMA1_STREAM1;
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ADCD1.dmamode = STM32_DMA_CR_PL(STM32_ADC_ADC1_DMA_PRIORITY) |
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ADCD1.dmamode = STM32_DMA_CR_PL(STM32_ADC_ADC12_DMA_PRIORITY) |
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STM32_DMA_CR_DIR_P2M |
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STM32_DMA_CR_DIR_P2M |
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STM32_DMA_CR_MSIZE_HWORD | STM32_DMA_CR_PSIZE_HWORD |
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STM32_DMA_CR_MSIZE_HWORD | STM32_DMA_CR_PSIZE_HWORD |
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STM32_DMA_CR_MINC | STM32_DMA_CR_TCIE |
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STM32_DMA_CR_MINC | STM32_DMA_CR_TCIE |
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STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE;
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STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE;
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nvicEnableVector(ADC1_2_IRQn,
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CORTEX_PRIORITY_MASK(STM32_ADC_ADC12_IRQ_PRIORITY));
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#endif /* STM32_ADC_USE_ADC1 */
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#if STM32_ADC_USE_ADC3
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/* Driver initialization.*/
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adcObjectInit(&ADCD1);
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ADCD3.adcm = ADC3;
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#if STM32_ADC_DUAL_MODE
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ADCD3.adcs = ADC4;
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#endif
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#endif
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ADCD3.dmastp = STM32_DMA2_STREAM5;
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/* The shared vector is initialized on driver initialization and never
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ADCD3.dmamode = STM32_DMA_CR_PL(STM32_ADC_ADC12_DMA_PRIORITY) |
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disabled.*/
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STM32_DMA_CR_DIR_P2M |
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nvicEnableVector(ADC1_COMP_IRQn,
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STM32_DMA_CR_MSIZE_HWORD | STM32_DMA_CR_PSIZE_HWORD |
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CORTEX_PRIORITY_MASK(STM32_ADC_IRQ_PRIORITY));
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STM32_DMA_CR_MINC | STM32_DMA_CR_TCIE |
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STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE;
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/* Calibration procedure.*/
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nvicEnableVector(ADC3_IRQn,
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rccEnableADC1(FALSE);
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CORTEX_PRIORITY_MASK(STM32_ADC_ADC34_IRQ_PRIORITY));
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chDbgAssert(ADC1->CR == 0, "adc_lld_init(), #1", "invalid register state");
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#if STM32_ADC_DUAL_MODE
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ADC1->CR |= ADC_CR_ADCAL;
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nvicEnableVector(ADC4_IRQn,
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while (ADC1->CR & ADC_CR_ADCAL)
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CORTEX_PRIORITY_MASK(STM32_ADC_ADC34_IRQ_PRIORITY));
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;
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#endif
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rccDisableADC1(FALSE);
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#endif /* STM32_ADC_USE_ADC3 */
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}
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}
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/**
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/**
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@ -250,30 +360,48 @@ void adc_lld_start(ADCDriver *adcp) {
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if (&ADCD1 == adcp) {
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if (&ADCD1 == adcp) {
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bool_t b;
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bool_t b;
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b = dmaStreamAllocate(adcp->dmastp,
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b = dmaStreamAllocate(adcp->dmastp,
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STM32_ADC_ADC1_DMA_IRQ_PRIORITY,
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STM32_ADC_ADC12_DMA_IRQ_PRIORITY,
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(stm32_dmaisr_t)adc_lld_serve_dma_interrupt,
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(stm32_dmaisr_t)adc_lld_serve_dma_interrupt,
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(void *)adcp);
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(void *)adcp);
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chDbgAssert(!b, "adc_lld_start(), #1", "stream already allocated");
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chDbgAssert(!b, "adc_lld_start(), #1", "stream already allocated");
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#if STM32_ADC_DUAL_MODE
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dmaStreamSetPeripheral(adcp->dmastp, &ADC1_2->CDR);
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#else
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dmaStreamSetPeripheral(adcp->dmastp, &ADC1->DR);
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dmaStreamSetPeripheral(adcp->dmastp, &ADC1->DR);
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rccEnableADC1(FALSE);
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#if STM32_ADCSW == STM32_ADCSW_HSI14
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/* Clock from HSI14, no need for jitter removal.*/
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ADC1->CFGR2 = 0x00001000;
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#else
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#if STM32_ADCPRE == STM32_ADCPRE_DIV2
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ADC1->CFGR2 = 0x00001000 | ADC_CFGR2_JITOFFDIV2;
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#else
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ADC1->CFGR2 = 0x00001000 | ADC_CFGR2_JITOFFDIV4;
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#endif
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#endif
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#endif
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rccEnableADC12(FALSE);
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/* Clock source setting.*/
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ADC1_2->CCR = ADC_CCR_CKMODE_AHB_DIV1;
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}
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}
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#endif /* STM32_ADC_USE_ADC1 */
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#endif /* STM32_ADC_USE_ADC1 */
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/* ADC initial setup, starting the analog part here in order to reduce
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#if STM32_ADC_USE_ADC3
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the latency when starting a conversion.*/
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if (&ADCD3 == adcp) {
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adcp->adc->CR = ADC_CR_ADEN;
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bool_t b;
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while (!(adcp->adc->ISR & ADC_ISR_ADRDY))
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b = dmaStreamAllocate(adcp->dmastp,
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;
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STM32_ADC_ADC34_DMA_IRQ_PRIORITY,
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(stm32_dmaisr_t)adc_lld_serve_dma_interrupt,
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(void *)adcp);
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chDbgAssert(!b, "adc_lld_start(), #2", "stream already allocated");
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#if STM32_ADC_DUAL_MODE
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dmaStreamSetPeripheral(adcp->dmastp, &ADC3_4->CDR);
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#else
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dmaStreamSetPeripheral(adcp->dmastp, &ADC3->DR);
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#endif
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rccEnableADC34(FALSE);
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/* Clock source setting.*/
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ADC3_4->CCR = ADC_CCR_CKMODE_AHB_DIV1;
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}
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#endif /* STM32_ADC_USE_ADC2 */
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/* Master ADC calibration.*/
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adc_lld_vreg_on(adcp);
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adc_lld_calibrate(adcp);
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/* Master ADC enabled here in order to reduce conversions latencies.*/
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adc_lld_analog_on(adcp);
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}
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}
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}
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}
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@ -289,19 +417,27 @@ void adc_lld_stop(ADCDriver *adcp) {
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/* If in ready state then disables the ADC clock and analog part.*/
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/* If in ready state then disables the ADC clock and analog part.*/
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if (adcp->state == ADC_READY) {
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if (adcp->state == ADC_READY) {
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/* Releasing the associated DMA channel.*/
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dmaStreamRelease(adcp->dmastp);
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dmaStreamRelease(adcp->dmastp);
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/* Disabling ADC.*/
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/* Disabling the ADC.*/
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if (adcp->adc->CR & ADC_CR_ADEN) {
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if (adcp->adcm->CR & ADC_CR_ADEN) {
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adc_lld_stop_adc(adcp->adc);
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/* Stopping the ongoing conversion, if any.*/
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adcp->adc->CR |= ADC_CR_ADDIS;
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adc_lld_stop_adc(adcp);
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while (adcp->adc->CR & ADC_CR_ADDIS)
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;
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/* Disabling ADC analog circuit and regulator.*/
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adc_lld_analog_off(adcp);
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adc_lld_vreg_off(adcp);
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}
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}
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#if STM32_ADC_USE_ADC1
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#if STM32_ADC_USE_ADC1
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if (&ADCD1 == adcp)
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if (&ADCD1 == adcp)
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rccDisableADC1(FALSE);
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rccDisableADC12(FALSE);
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#endif
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#if STM32_ADC_USE_ADC3
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if (&ADCD1 == adcp)
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rccDisableADC34(FALSE);
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#endif
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#endif
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}
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}
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}
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}
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#define ADC_CFGR_DISCEN_ENABLED (1 << 16)
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#define ADC_CFGR_DISCEN_ENABLED (1 << 16)
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#define ADC_CFGR_DISCNUM_MASK (7 << 17)
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#define ADC_CFGR_DISCNUM_MASK (7 << 17)
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#define ADC_CFGR_DISCNUM(n) ((n) << 17)
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#define ADC_CFGR_DISCNUM_VAL(n) ((n) << 17)
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#define ADC_CFGR_AWD1_DISABLED 0
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#define ADC_CFGR_AWD1_DISABLED 0
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#define ADC_CFGR_AWD1_ALL (1 << 23)
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#define ADC_CFGR_AWD1_ALL (1 << 23)
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/**
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/**
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* @brief ADC1/ADC2 DMA priority (0..3|lowest..highest).
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* @brief ADC1/ADC2 DMA priority (0..3|lowest..highest).
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*/
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*/
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#if !defined(STM32_ADC_ADC1_DMA_PRIORITY) || defined(__DOXYGEN__)
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#if !defined(STM32_ADC_ADC12_DMA_PRIORITY) || defined(__DOXYGEN__)
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#define STM32_ADC_ADC1_DMA_PRIORITY 2
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#define STM32_ADC_ADC12_DMA_PRIORITY 2
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#endif
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#endif
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/**
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/**
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* @brief ADC3/ADC4 DMA priority (0..3|lowest..highest).
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* @brief ADC3/ADC4 DMA priority (0..3|lowest..highest).
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*/
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*/
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#if !defined(STM32_ADC_ADC3_DMA_PRIORITY) || defined(__DOXYGEN__)
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#if !defined(STM32_ADC_ADC34_DMA_PRIORITY) || defined(__DOXYGEN__)
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#define STM32_ADC_ADC3_DMA_PRIORITY 2
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#define STM32_ADC_ADC34_DMA_PRIORITY 2
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#endif
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#endif
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/**
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/**
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* @brief ADC1/ADC2 interrupt priority level setting.
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* @brief ADC1/ADC2 interrupt priority level setting.
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*/
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*/
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#if !defined(STM32_ADC_ADC1_IRQ_PRIORITY) || defined(__DOXYGEN__)
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#if !defined(STM32_ADC_ADC12_IRQ_PRIORITY) || defined(__DOXYGEN__)
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#define STM32_ADC_ADC1_IRQ_PRIORITY 2
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#define STM32_ADC_ADC12_IRQ_PRIORITY 2
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#endif
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#endif
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/**
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/**
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* @brief ADC3/ADC4 interrupt priority level setting.
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* @brief ADC3/ADC4 interrupt priority level setting.
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*/
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*/
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#if !defined(STM32_ADC3_IRQ_PRIORITY) || defined(__DOXYGEN__)
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#if !defined(STM32_ADC34_IRQ_PRIORITY) || defined(__DOXYGEN__)
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#define STM32_ADC_ADC3_IRQ_PRIORITY 2
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#define STM32_ADC_ADC34_IRQ_PRIORITY 2
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#endif
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#endif
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/**
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/**
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* @brief ADC1/ADC2 DMA interrupt priority level setting.
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* @brief ADC1/ADC2 DMA interrupt priority level setting.
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*/
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*/
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#if !defined(STM32_ADC_ADC1_DMA_IRQ_PRIORITY) || defined(__DOXYGEN__)
|
#if !defined(STM32_ADC_ADC12_DMA_IRQ_PRIORITY) || defined(__DOXYGEN__)
|
||||||
#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 2
|
#define STM32_ADC_ADC12_DMA_IRQ_PRIORITY 2
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* @brief ADC3/ADC4 DMA interrupt priority level setting.
|
* @brief ADC3/ADC4 DMA interrupt priority level setting.
|
||||||
*/
|
*/
|
||||||
#if !defined(STM32_ADC_ADC3_DMA_IRQ_PRIORITY) || defined(__DOXYGEN__)
|
#if !defined(STM32_ADC_ADC34_DMA_IRQ_PRIORITY) || defined(__DOXYGEN__)
|
||||||
#define STM32_ADC_ADC3_DMA_IRQ_PRIORITY 2
|
#define STM32_ADC_ADC34_DMA_IRQ_PRIORITY 2
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* @brief ADC1/ADC2 clock source and mode.
|
* @brief ADC1/ADC2 clock source and mode.
|
||||||
*/
|
*/
|
||||||
#if !defined(STM32_ADC_ADC1_CLOCK_MODE) || defined(__DOXYGEN__)
|
#if !defined(STM32_ADC_ADC12_CLOCK_MODE) || defined(__DOXYGEN__)
|
||||||
#define STM32_ADC_ADC1_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV1
|
#define STM32_ADC_ADC12_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV1
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* @brief ADC3/ADC4 clock source and mode.
|
* @brief ADC3/ADC4 clock source and mode.
|
||||||
*/
|
*/
|
||||||
#if !defined(STM32_ADC_ADC3_CLOCK_MODE) || defined(__DOXYGEN__)
|
#if !defined(STM32_ADC_ADC34_CLOCK_MODE) || defined(__DOXYGEN__)
|
||||||
#define STM32_ADC_ADC3_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV1
|
#define STM32_ADC_ADC34_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV1
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
/**
|
/**
|
||||||
|
@ -238,70 +238,70 @@
|
||||||
#error "ADC3 not present in the selected device"
|
#error "ADC3 not present in the selected device"
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
#if !STM32_ADC_USE_ADC1 ||!STM32_ADC_USE_ADC3
|
#if !STM32_ADC_USE_ADC1 && !STM32_ADC_USE_ADC3
|
||||||
#error "ADC driver activated but no ADC peripheral assigned"
|
#error "ADC driver activated but no ADC peripheral assigned"
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
#if STM32_ADC_USE_ADC1 && \
|
#if STM32_ADC_USE_ADC1 && \
|
||||||
!CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_ADC_ADC1_IRQ_PRIORITY)
|
!CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_ADC_ADC12_IRQ_PRIORITY)
|
||||||
#error "Invalid IRQ priority assigned to ADC1"
|
#error "Invalid IRQ priority assigned to ADC1"
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
#if STM32_ADC_USE_ADC1 && \
|
#if STM32_ADC_USE_ADC1 && \
|
||||||
!CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_ADC_ADC1_DMA_IRQ_PRIORITY)
|
!CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_ADC_ADC12_DMA_IRQ_PRIORITY)
|
||||||
#error "Invalid IRQ priority assigned to ADC1 DMA"
|
#error "Invalid IRQ priority assigned to ADC1 DMA"
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
#if STM32_ADC_USE_ADC1 && \
|
#if STM32_ADC_USE_ADC1 && \
|
||||||
!STM32_DMA_IS_VALID_PRIORITY(STM32_ADC_ADC1_DMA_PRIORITY)
|
!STM32_DMA_IS_VALID_PRIORITY(STM32_ADC_ADC12_DMA_PRIORITY)
|
||||||
#error "Invalid DMA priority assigned to ADC1"
|
#error "Invalid DMA priority assigned to ADC1"
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
#if STM32_ADC_USE_ADC3 && \
|
#if STM32_ADC_USE_ADC3 && \
|
||||||
!CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_ADC_ADC3_IRQ_PRIORITY)
|
!CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_ADC_ADC34_IRQ_PRIORITY)
|
||||||
#error "Invalid IRQ priority assigned to ADC3"
|
#error "Invalid IRQ priority assigned to ADC3"
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
#if STM32_ADC_USE_ADC3 && \
|
#if STM32_ADC_USE_ADC3 && \
|
||||||
!CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_ADC_ADC3_DMA_IRQ_PRIORITY)
|
!CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_ADC_ADC34_DMA_IRQ_PRIORITY)
|
||||||
#error "Invalid IRQ priority assigned to ADC3 DMA"
|
#error "Invalid IRQ priority assigned to ADC3 DMA"
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
#if STM32_ADC_USE_ADC3 && \
|
#if STM32_ADC_USE_ADC3 && \
|
||||||
!STM32_DMA_IS_VALID_PRIORITY(STM32_ADC_ADC3_DMA_PRIORITY)
|
!STM32_DMA_IS_VALID_PRIORITY(STM32_ADC_ADC34_DMA_PRIORITY)
|
||||||
#error "Invalid DMA priority assigned to ADC3"
|
#error "Invalid DMA priority assigned to ADC3"
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
#if STM32_ADC_ADC1_CLOCK_MODE == ADC_CCR_CKMODE_ADCCK
|
#if STM32_ADC_ADC12_CLOCK_MODE == ADC_CCR_CKMODE_ADCCK
|
||||||
#define STM32_ADC1_CLOCK STM32ADC1CLK
|
#define STM32_ADC12_CLOCK STM32ADC1CLK
|
||||||
#elif STM32_ADC_ADC1_CLOCK_MODE == ADC_CCR_CKMODE_AHB_DIV1
|
#elif STM32_ADC_ADC12_CLOCK_MODE == ADC_CCR_CKMODE_AHB_DIV1
|
||||||
#define STM32_ADC1_CLOCK (STM32_HCLK / 1)
|
#define STM32_ADC12_CLOCK (STM32_HCLK / 1)
|
||||||
#elif STM32_ADC_ADC1_CLOCK_MODE == ADC_CCR_CKMODE_AHB_DIV2
|
#elif STM32_ADC_ADC12_CLOCK_MODE == ADC_CCR_CKMODE_AHB_DIV2
|
||||||
#define STM32_ADC1_CLOCK (STM32_HCLK / 2)
|
#define STM32_ADC12_CLOCK (STM32_HCLK / 2)
|
||||||
#elif STM32_ADC_ADC1_CLOCK_MODE == ADC_CCR_CKMODE_AHB_DIV4
|
#elif STM32_ADC_ADC12_CLOCK_MODE == ADC_CCR_CKMODE_AHB_DIV4
|
||||||
#define STM32_ADC1_CLOCK (STM32_HCLK / 4)
|
#define STM32_ADC12_CLOCK (STM32_HCLK / 4)
|
||||||
#else
|
#else
|
||||||
#error "invalid clock mode selected for STM32_ADC_ADC1_CLOCK_MODE"
|
#error "invalid clock mode selected for STM32_ADC_ADC12_CLOCK_MODE"
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
#if STM32_ADC_ADC3_CLOCK_MODE == ADC_CCR_CKMODE_ADCCK
|
#if STM32_ADC_ADC34_CLOCK_MODE == ADC_CCR_CKMODE_ADCCK
|
||||||
#define STM32_ADC3_CLOCK STM32ADC3CLK
|
#define STM32_ADC34_CLOCK STM32ADC3CLK
|
||||||
#elif STM32_ADC_ADC3_CLOCK_MODE == ADC_CCR_CKMODE_AHB_DIV1
|
#elif STM32_ADC_ADC34_CLOCK_MODE == ADC_CCR_CKMODE_AHB_DIV1
|
||||||
#define STM32_ADC3_CLOCK (STM32_HCLK / 1)
|
#define STM32_ADC34_CLOCK (STM32_HCLK / 1)
|
||||||
#elif STM32_ADC_ADC3_CLOCK_MODE == ADC_CCR_CKMODE_AHB_DIV2
|
#elif STM32_ADC_ADC34_CLOCK_MODE == ADC_CCR_CKMODE_AHB_DIV2
|
||||||
#define STM32_ADC3_CLOCK (STM32_HCLK / 2)
|
#define STM32_ADC34_CLOCK (STM32_HCLK / 2)
|
||||||
#elif STM32_ADC_ADC3_CLOCK_MODE == ADC_CCR_CKMODE_AHB_DIV4
|
#elif STM32_ADC_ADC34_CLOCK_MODE == ADC_CCR_CKMODE_AHB_DIV4
|
||||||
#define STM32_ADC3_CLOCK (STM32_HCLK / 4)
|
#define STM32_ADC34_CLOCK (STM32_HCLK / 4)
|
||||||
#else
|
#else
|
||||||
#error "invalid clock mode selected for STM32_ADC_ADC1_CLOCK_MODE"
|
#error "invalid clock mode selected for STM32_ADC_ADC12_CLOCK_MODE"
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
#if STM32_ADC1_CLOCK > 72000000
|
#if STM32_ADC12_CLOCK > 72000000
|
||||||
#error "STM32_ADC1_CLOCK exceeding maximum frequency (72000000)"
|
#error "STM32_ADC12_CLOCK exceeding maximum frequency (72000000)"
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
#if STM32_ADC3_CLOCK > 72000000
|
#if STM32_ADC34_CLOCK > 72000000
|
||||||
#error "STM32_ADC3_CLOCK exceeding maximum frequency (72000000)"
|
#error "STM32_ADC34_CLOCK exceeding maximum frequency (72000000)"
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
#if !defined(STM32_DMA_REQUIRED)
|
#if !defined(STM32_DMA_REQUIRED)
|
||||||
|
@ -330,8 +330,8 @@ typedef uint16_t adc_channels_num_t;
|
||||||
typedef enum {
|
typedef enum {
|
||||||
ADC_ERR_DMAFAILURE = 0, /**< DMA operations failure. */
|
ADC_ERR_DMAFAILURE = 0, /**< DMA operations failure. */
|
||||||
ADC_ERR_OVERFLOW = 1, /**< ADC overflow condition. */
|
ADC_ERR_OVERFLOW = 1, /**< ADC overflow condition. */
|
||||||
ADC_ERR_AWD1 = 2 /**< Watchdog 1 triggered. */
|
ADC_ERR_AWD1 = 2, /**< Watchdog 1 triggered. */
|
||||||
ADC_ERR_AWD2 = 3 /**< Watchdog 2 triggered. */
|
ADC_ERR_AWD2 = 3, /**< Watchdog 2 triggered. */
|
||||||
ADC_ERR_AWD3 = 4 /**< Watchdog 3 triggered. */
|
ADC_ERR_AWD3 = 4 /**< Watchdog 3 triggered. */
|
||||||
} adcerror_t;
|
} adcerror_t;
|
||||||
|
|
||||||
|
|
|
@ -1,6 +1,7 @@
|
||||||
# List of all the STM32F3xx platform files.
|
# List of all the STM32F3xx platform files.
|
||||||
PLATFORMSRC = ${CHIBIOS}/os/hal/platforms/STM32F3xx/stm32_dma.c \
|
PLATFORMSRC = ${CHIBIOS}/os/hal/platforms/STM32F3xx/stm32_dma.c \
|
||||||
${CHIBIOS}/os/hal/platforms/STM32F3xx/hal_lld.c \
|
${CHIBIOS}/os/hal/platforms/STM32F3xx/hal_lld.c \
|
||||||
|
${CHIBIOS}/os/hal/platforms/STM32F3xx/adc_lld.c \
|
||||||
${CHIBIOS}/os/hal/platforms/STM32F3xx/ext_lld_isr.c \
|
${CHIBIOS}/os/hal/platforms/STM32F3xx/ext_lld_isr.c \
|
||||||
${CHIBIOS}/os/hal/platforms/STM32/can_lld.c \
|
${CHIBIOS}/os/hal/platforms/STM32/can_lld.c \
|
||||||
${CHIBIOS}/os/hal/platforms/STM32/ext_lld.c \
|
${CHIBIOS}/os/hal/platforms/STM32/ext_lld.c \
|
||||||
|
|
|
@ -169,29 +169,54 @@
|
||||||
* @{
|
* @{
|
||||||
*/
|
*/
|
||||||
/**
|
/**
|
||||||
* @brief Enables the ADC1 peripheral clock.
|
* @brief Enables the ADC1/ADC2 peripheral clock.
|
||||||
*
|
*
|
||||||
* @param[in] lp low power enable flag
|
* @param[in] lp low power enable flag
|
||||||
*
|
*
|
||||||
* @api
|
* @api
|
||||||
*/
|
*/
|
||||||
#define rccEnableADC1(lp) rccEnableAPB2(RCC_APB2ENR_ADC1EN, lp)
|
#define rccEnableADC12(lp) rccEnableAHB(RCC_AHBENR_ADC12EN, lp)
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* @brief Disables the ADC1 peripheral clock.
|
* @brief Disables the ADC1/ADC2 peripheral clock.
|
||||||
*
|
*
|
||||||
* @param[in] lp low power enable flag
|
* @param[in] lp low power enable flag
|
||||||
*
|
*
|
||||||
* @api
|
* @api
|
||||||
*/
|
*/
|
||||||
#define rccDisableADC1(lp) rccDisableAPB2(RCC_APB2ENR_ADC1EN, lp)
|
#define rccDisableADC12(lp) rccDisableAHB(RCC_AHBENR_ADC12EN, lp)
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* @brief Resets the ADC1 peripheral.
|
* @brief Resets the ADC1/ADC2 peripheral.
|
||||||
*
|
*
|
||||||
* @api
|
* @api
|
||||||
*/
|
*/
|
||||||
#define rccResetADC1() rccResetAPB2(RCC_APB2RSTR_ADC1RST)
|
#define rccResetADC12() rccResetAHB(RCC_AHBRSTR_ADC12RST)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enables the ADC3/ADC4 peripheral clock.
|
||||||
|
*
|
||||||
|
* @param[in] lp low power enable flag
|
||||||
|
*
|
||||||
|
* @api
|
||||||
|
*/
|
||||||
|
#define rccEnableADC34(lp) rccEnableAHB(RCC_AHBENR_ADC34EN, lp)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Disables the ADC3/ADC4 peripheral clock.
|
||||||
|
*
|
||||||
|
* @param[in] lp low power enable flag
|
||||||
|
*
|
||||||
|
* @api
|
||||||
|
*/
|
||||||
|
#define rccDisableADC34(lp) rccDisableAHB(RCC_AHBENR_ADC34EN, lp)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Resets the ADC3/ADC4 peripheral.
|
||||||
|
*
|
||||||
|
* @api
|
||||||
|
*/
|
||||||
|
#define rccResetADC34() rccResetAHB(RCC_AHBRSTR_ADC34RST)
|
||||||
/** @} */
|
/** @} */
|
||||||
|
|
||||||
/**
|
/**
|
||||||
|
|
|
@ -1031,7 +1031,9 @@ typedef struct
|
||||||
/* */
|
/* */
|
||||||
/******************************************************************************/
|
/******************************************************************************/
|
||||||
/******************** Bit definition for ADC_ISR register ********************/
|
/******************** Bit definition for ADC_ISR register ********************/
|
||||||
#define ADC_ISR_ADRD ((uint32_t)0x00000001) /*!< ADC Ready (ADRDY) flag */
|
/* CHIBIOS FIX */
|
||||||
|
//#define ADC_ISR_ADRD ((uint32_t)0x00000001) /*!< ADC Ready (ADRDY) flag */
|
||||||
|
#define ADC_ISR_ADRDY ((uint32_t)0x00000001) /*!< ADC Ready (ADRDY) flag */
|
||||||
#define ADC_ISR_EOSMP ((uint32_t)0x00000002) /*!< ADC End of Sampling flag */
|
#define ADC_ISR_EOSMP ((uint32_t)0x00000002) /*!< ADC End of Sampling flag */
|
||||||
#define ADC_ISR_EOC ((uint32_t)0x00000004) /*!< ADC End of Regular Conversion flag */
|
#define ADC_ISR_EOC ((uint32_t)0x00000004) /*!< ADC End of Regular Conversion flag */
|
||||||
#define ADC_ISR_EOS ((uint32_t)0x00000008) /*!< ADC End of Regular sequence of Conversions flag */
|
#define ADC_ISR_EOS ((uint32_t)0x00000008) /*!< ADC End of Regular sequence of Conversions flag */
|
||||||
|
|
|
@ -70,16 +70,16 @@
|
||||||
/*
|
/*
|
||||||
* ADC driver system settings.
|
* ADC driver system settings.
|
||||||
*/
|
*/
|
||||||
#define STM32_ADC_USE_ADC1 FALSE
|
#define STM32_ADC_USE_ADC1 TRUE
|
||||||
#define STM32_ADC_USE_ADC3 FALSE
|
#define STM32_ADC_USE_ADC3 TRUE
|
||||||
#define STM32_ADC_ADC1_DMA_PRIORITY 2
|
#define STM32_ADC_ADC12_DMA_PRIORITY 2
|
||||||
#define STM32_ADC_ADC3_DMA_PRIORITY 2
|
#define STM32_ADC_ADC34_DMA_PRIORITY 2
|
||||||
#define STM32_ADC_ADC1_IRQ_PRIORITY 2
|
#define STM32_ADC_ADC12_IRQ_PRIORITY 2
|
||||||
#define STM32_ADC_ADC3_IRQ_PRIORITY 2
|
#define STM32_ADC_ADC34_IRQ_PRIORITY 2
|
||||||
#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 2
|
#define STM32_ADC_ADC12_DMA_IRQ_PRIORITY 2
|
||||||
#define STM32_ADC_ADC3_DMA_IRQ_PRIORITY 2
|
#define STM32_ADC_ADC34_DMA_IRQ_PRIORITY 2
|
||||||
#define STM32_ADC_ADC1_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV1
|
#define STM32_ADC_ADC12_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV1
|
||||||
#define STM32_ADC_ADC3_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV1
|
#define STM32_ADC_ADC34_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV1
|
||||||
#define STM32_ADC_DUAL_MODE FALSE
|
#define STM32_ADC_DUAL_MODE FALSE
|
||||||
|
|
||||||
/*
|
/*
|
||||||
|
|
Loading…
Reference in New Issue