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STM32 Ethernet driver added. 

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/branches/stable_2.4.x@4149 35acf78f-673a-0410-8e92-d51de3d6d3f4
This commit is contained in:
gdisirio 2012-04-30 06:35:38 +00:00
parent f9cb7feb20
commit d36aee10c1
10 changed files with 1227 additions and 2 deletions
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670
os/hal/platforms/STM32/mac_lld.c Normal file
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/*
ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
2011,2012 Giovanni Di Sirio.
This file is part of ChibiOS/RT.
ChibiOS/RT is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
ChibiOS/RT is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
---
A special exception to the GPL can be applied should you wish to distribute
a combined work that includes ChibiOS/RT, without being obliged to provide
the source code for any proprietary components. See the file exception.txt
for full details of how and when the exception can be applied.
*/
/**
* @file STM32/mac_lld.c
* @brief STM32 low level MAC driver code.
*
* @addtogroup MAC
* @{
*/
#include <string.h>
#include "ch.h"
#include "hal.h"
#include "mii.h"
#if HAL_USE_MAC || defined(__DOXYGEN__)
/*===========================================================================*/
/* Driver local definitions. */
/*===========================================================================*/
#define BUFFER_SIZE ((((STM32_MAC_BUFFERS_SIZE - 1) | 3) + 1) / 4)
/* MII divider optimal value.*/
#if (STM32_HCLK >= 60000000)
#define MACMIIDR_CR ETH_MACMIIAR_CR_Div42
#elif (STM32_HCLK >= 35000000)
#define MACMIIDR_CR ETH_MACMIIAR_CR_Div26
#elif (STM32_HCLK >= 20000000)
#define MACMIIDR_CR ETH_MACMIIAR_CR_Div16
#else
#error "STM32_HCLK below minimum frequency for ETH operations (20MHz)"
#endif
/*===========================================================================*/
/* Driver exported variables. */
/*===========================================================================*/
/**
* @brief Ethernet driver 1.
*/
MACDriver ETHD1;
/*===========================================================================*/
/* Driver local variables. */
/*===========================================================================*/
static const uint8_t default_mac_address[] = {0xAA, 0x55, 0x13,
0x37, 0x01, 0x10};
static stm32_eth_rx_descriptor_t rd[STM32_MAC_RECEIVE_BUFFERS];
static stm32_eth_tx_descriptor_t td[STM32_MAC_TRANSMIT_BUFFERS];
static uint32_t rb[STM32_MAC_RECEIVE_BUFFERS][BUFFER_SIZE];
static uint32_t tb[STM32_MAC_TRANSMIT_BUFFERS][BUFFER_SIZE];
/*===========================================================================*/
/* Driver local functions. */
/*===========================================================================*/
/**
* @brief Writes a PHY register.
*
* @param[in] macp pointer to the @p MACDriver object
* @param[in] reg register number
* @param[in] value new register value
*/
static void mii_write(MACDriver *macp, uint32_t reg, uint32_t value) {
ETH->MACMIIDR = value;
ETH->MACMIIAR = macp->phyaddr | (reg << 6) | MACMIIDR_CR |
ETH_MACMIIAR_MW | ETH_MACMIIAR_MB;
while ((ETH->MACMIIAR & ETH_MACMIIAR_MB) != 0)
;
}
/**
* @brief Reads a PHY register.
*
* @param[in] macp pointer to the @p MACDriver object
* @param[in] reg register number
*
* @return The PHY register content.
*/
static uint32_t mii_read(MACDriver *macp, uint32_t reg) {
ETH->MACMIIAR = macp->phyaddr | (reg << 6) | MACMIIDR_CR | ETH_MACMIIAR_MB;
while ((ETH->MACMIIAR & ETH_MACMIIAR_MB) != 0)
;
return ETH->MACMIIDR;
}
#if !defined(BOARD_PHY_ADDRESS)
/**
* @brief PHY address detection.
*
* @param[in] macp pointer to the @p MACDriver object
*/
static void mii_find_phy(MACDriver *macp) {
uint32_t i;
#if STM32_MAC_PHY_TIMEOUT > 0
halrtcnt_t start = halGetCounterValue();
halrtcnt_t timeout = start + MS2RTT(STM32_MAC_PHY_TIMEOUT);
while (halIsCounterWithin(start, timeout)) {
#endif
for (i = 0; i < 31; i++) {
macp->phyaddr = i << 11;
ETH->MACMIIDR = (i << 6) | MACMIIDR_CR;
if ((mii_read(macp, MII_PHYSID1) == (BOARD_PHY_ID >> 16)) &&
((mii_read(macp, MII_PHYSID2) & 0xFFF0) == (BOARD_PHY_ID & 0xFFF0))) {
return;
}
}
#if STM32_MAC_PHY_TIMEOUT > 0
}
#endif
/* Wrong or defective board.*/
chSysHalt();
}
#endif
/**
* @brief MAC address setup.
*
* @param[in] p pointer to a six bytes buffer containing the MAC
* address
*/
static void mac_lld_set_address(const uint8_t *p) {
/* MAC address configuration, only a single address comparator is used,
hash table not used.*/
ETH->MACA0HR = ((uint32_t)p[5] << 8) |
((uint32_t)p[4] << 0);
ETH->MACA0LR = ((uint32_t)p[3] << 24) |
((uint32_t)p[2] << 16) |
((uint32_t)p[1] << 8) |
((uint32_t)p[0] << 0);
ETH->MACA1HR = 0x0000FFFF;
ETH->MACA1LR = 0xFFFFFFFF;
ETH->MACA2HR = 0x0000FFFF;
ETH->MACA2LR = 0xFFFFFFFF;
ETH->MACA3HR = 0x0000FFFF;
ETH->MACA3LR = 0xFFFFFFFF;
ETH->MACHTHR = 0;
ETH->MACHTLR = 0;
}
/*===========================================================================*/
/* Driver interrupt handlers. */
/*===========================================================================*/
CH_IRQ_HANDLER(ETH_IRQHandler) {
uint32_t dmasr;
CH_IRQ_PROLOGUE();
dmasr = ETH->DMASR;
ETH->DMASR = dmasr; /* Clear status bits.*/
if (dmasr & ETH_DMASR_RS) {
/* Data Received.*/
chSysLockFromIsr();
chSemResetI(&ETHD1.rdsem, 0);
#if MAC_USE_EVENTS
chEvtBroadcastI(&ETHD1.rdevent);
#endif
chSysUnlockFromIsr();
}
if (dmasr & ETH_DMASR_TS) {
/* Data Transmitted.*/
chSysLockFromIsr();
chSemResetI(&ETHD1.tdsem, 0);
chSysUnlockFromIsr();
}
CH_IRQ_EPILOGUE();
}
/*===========================================================================*/
/* Driver exported functions. */
/*===========================================================================*/
/**
* @brief Low level MAC initialization.
*
* @notapi
*/
void mac_lld_init(void) {
unsigned i;
macObjectInit(&ETHD1);
ETHD1.link_up = FALSE;
/* Descriptor tables are initialized in chained mode, note that the first
word is not initialized here but in mac_lld_start().*/
for (i = 0; i < STM32_MAC_RECEIVE_BUFFERS; i++) {
rd[i].rdes1 = STM32_RDES1_RCH | STM32_MAC_BUFFERS_SIZE;
rd[i].rdes2 = (uint32_t)rb[i];
rd[i].rdes3 = (uint32_t)&rd[(i + 1) % STM32_MAC_RECEIVE_BUFFERS];
}
for (i = 0; i < STM32_MAC_TRANSMIT_BUFFERS; i++) {
td[i].tdes1 = 0;
td[i].tdes2 = (uint32_t)tb[i];
td[i].tdes3 = (uint32_t)&td[(i + 1) % STM32_MAC_TRANSMIT_BUFFERS];
}
/* Selection of the RMII or MII mode based on info exported by board.h.*/
#if defined(STM32F10X_CL)
#if defined(BOARD_PHY_RMII)
AFIO->MAPR |= AFIO_MAPR_MII_RMII_SEL;
#else
AFIO->MAPR &= ~AFIO_MAPR_MII_RMII_SEL;
#endif
#elif defined(STM32F2XX) || defined(STM32F4XX)
#if defined(BOARD_PHY_RMII)
SYSCFG->PMC |= SYSCFG_PMC_MII_RMII_SEL;
#else
SYSCFG->PMC &= ~SYSCFG_PMC_MII_RMII_SEL;
#endif
#else
#error "unsupported STM32 platform for MAC driver"
#endif
/* Reset of the MAC core.*/
rccResetETH();
/* MAC clocks temporary activation.*/
rccEnableETH(FALSE);
/* PHY address setup.*/
#if defined(BOARD_PHY_ADDRESS)
ETHD1.phyaddr = BOARD_PHY_ADDRESS << 11;
#else
mii_find_phy(&ETHD1);
#endif
#if defined(BOARD_PHY_RESET)
/* PHY board-specific reset procedure.*/
BOARD_PHY_RESET();
#else
/* PHY soft reset procedure.*/
mii_write(&ETHD1, MII_BMCR, BMCR_RESET);
while (mii_read(&ETHD1, MII_BMCR) & BMCR_RESET)
;
#endif
/* PHY in power down mode until the driver will be started.*/
mii_write(&ETHD1, MII_BMCR, mii_read(&ETHD1, MII_BMCR) | BMCR_PDOWN);
/* MAC clocks stopped again.*/
rccDisableETH(FALSE);
}
/**
* @brief Configures and activates the MAC peripheral.
*
* @param[in] macp pointer to the @p MACDriver object
*
* @notapi
*/
void mac_lld_start(MACDriver *macp) {
unsigned i;
/* Resets the state of all descriptors.*/
for (i = 0; i < STM32_MAC_RECEIVE_BUFFERS; i++)
rd[i].rdes0 = STM32_RDES0_OWN;
macp->rxptr = (stm32_eth_rx_descriptor_t *)rd;
for (i = 0; i < STM32_MAC_TRANSMIT_BUFFERS; i++)
td[i].tdes0 = STM32_TDES0_TCH;
macp->txptr = (stm32_eth_tx_descriptor_t *)td;
/* MAC clocks activation and commanded reset procedure.*/
rccEnableETH(FALSE);
ETH->DMABMR |= ETH_DMABMR_SR;
while(ETH->DMABMR & ETH_DMABMR_SR)
;
/* ISR vector enabled.*/
nvicEnableVector(ETH_IRQn, CORTEX_PRIORITY_MASK(STM32_ETH1_IRQ_PRIORITY));
/* PHY in power up mode.*/
mii_write(macp, MII_BMCR, mii_read(macp, MII_BMCR) & ~BMCR_PDOWN);
/* MAC configuration.*/
ETH->MACFFR = 0;
ETH->MACFCR = 0;
ETH->MACVLANTR = 0;
/* MAC address setup.*/
if (macp->config->mac_address == NULL)
mac_lld_set_address(default_mac_address);
else
mac_lld_set_address(macp->config->mac_address);
/* Transmitter and receiver enabled.
Note that the complete setup of the MAC is performed when the link
status is detected.*/
#if STM32_IP_CHECKSUM_OFFLOAD
ETH->MACCR = ETH_MACCR_IPCO | ETH_MACCR_RE | ETH_MACCR_TE;
#else
ETH->MACCR = ETH_MACCR_RE | ETH_MACCR_TE;
#endif
/* DMA configuration:
Descriptor chains pointers.*/
ETH->DMARDLAR = (uint32_t)rd;
ETH->DMATDLAR = (uint32_t)td;
/* Enabling required interrupt sources.*/
ETH->DMASR = ETH->DMASR;
ETH->DMAIER = ETH_DMAIER_NISE | ETH_DMAIER_RIE | ETH_DMAIER_TIE;
/* DMA general settings.*/
ETH->DMABMR = ETH_DMABMR_AAB | ETH_DMABMR_RDP_1Beat | ETH_DMABMR_PBL_1Beat;
/* Transmit FIFO flush.*/
ETH->DMAOMR = ETH_DMAOMR_FTF;
while (ETH->DMAOMR & ETH_DMAOMR_FTF)
;
/* DMA final configuration and start.*/
ETH->DMAOMR = ETH_DMAOMR_DTCEFD | ETH_DMAOMR_RSF | ETH_DMAOMR_TSF |
ETH_DMAOMR_ST | ETH_DMAOMR_SR;
}
/**
* @brief Deactivates the MAC peripheral.
*
* @param[in] macp pointer to the @p MACDriver object
*
* @notapi
*/
void mac_lld_stop(MACDriver *macp) {
if (macp->state != MAC_STOP) {
/* PHY in power down mode until the driver will be restarted.*/
mii_write(macp, MII_BMCR, mii_read(macp, MII_BMCR) | BMCR_PDOWN);
/* MAC and DMA stopped.*/
ETH->MACCR = 0;
ETH->DMAOMR = 0;
ETH->DMAIER = 0;
ETH->DMASR = ETH->DMASR;
/* MAC clocks stopped.*/
rccDisableETH(FALSE);
/* ISR vector disabled.*/
nvicDisableVector(ETH_IRQn);
}
}
/**
* @brief Returns a transmission descriptor.
* @details One of the available transmission descriptors is locked and
* returned.
*
* @param[in] macp pointer to the @p MACDriver object
* @param[out] tdp pointer to a @p MACTransmitDescriptor structure
* @return The operation status.
* @retval RDY_OK the descriptor has been obtained.
* @retval RDY_TIMEOUT descriptor not available.
*
* @notapi
*/
msg_t max_lld_get_transmit_descriptor(MACDriver *macp,
MACTransmitDescriptor *tdp) {
stm32_eth_tx_descriptor_t *tdes;
if (!macp->link_up)
return RDY_TIMEOUT;
chSysLock();
/* Get Current TX descriptor.*/
tdes = macp->txptr;
/* Ensure that descriptor isn't owned by the Ethernet DMA or locked by
another thread.*/
if (tdes->tdes0 & (STM32_TDES0_OWN | STM32_TDES0_LOCKED)) {
chSysUnlock();
return RDY_TIMEOUT;
}
/* Marks the current descriptor as locked using a reserved bit.*/
tdes->tdes0 |= STM32_TDES0_LOCKED;
/* Next TX descriptor to use.*/
macp->txptr = (stm32_eth_tx_descriptor_t *)tdes->tdes3;
chSysUnlock();
/* Set the buffer size and configuration.*/
tdp->offset = 0;
tdp->size = STM32_MAC_BUFFERS_SIZE;
tdp->physdesc = tdes;
return RDY_OK;
}
/**
* @brief Writes to a transmit descriptor's stream.
*
* @param[in] tdp pointer to a @p MACTransmitDescriptor structure
* @param[in] buf pointer to the buffer containing the data to be
* written
* @param[in] size number of bytes to be written
* @return The number of bytes written into the descriptor's
* stream, this value can be less than the amount
* specified in the parameter @p size if the maximum
* frame size is reached.
*
* @notapi
*/
size_t mac_lld_write_transmit_descriptor(MACTransmitDescriptor *tdp,
uint8_t *buf,
size_t size) {
chDbgAssert(!(tdp->physdesc->tdes0 & STM32_TDES0_OWN),
"mac_lld_write_transmit_descriptor(), #1",
"attempt to write descriptor already owned by DMA");
if (size > tdp->size - tdp->offset)
size = tdp->size - tdp->offset;
if (size > 0) {
memcpy((uint8_t *)(tdp->physdesc->tdes2) + tdp->offset, buf, size);
tdp->offset += size;
}
return size;
}
/**
* @brief Releases a transmit descriptor and starts the transmission of the
* enqueued data as a single frame.
*
* @param[in] tdp the pointer to the @p MACTransmitDescriptor structure
*
* @notapi
*/
void mac_lld_release_transmit_descriptor(MACTransmitDescriptor *tdp) {
chDbgAssert(!(tdp->physdesc->tdes0 & STM32_TDES0_OWN),
"mac_lld_release_transmit_descriptor(), #1",
"attempt to release descriptor already owned by DMA");
chSysLock();
/* Unlocks the descriptor and returns it to the DMA engine.*/
tdp->physdesc->tdes1 = tdp->offset;
tdp->physdesc->tdes0 = STM32_TDES0_CIC(STM32_IP_CHECKSUM_OFFLOAD) |
STM32_TDES0_IC | STM32_TDES0_LS | STM32_TDES0_FS |
STM32_TDES0_TCH | STM32_TDES0_OWN;
/* If the DMA engine is stalled then a restart request is issued.*/
if ((ETH->DMASR & ETH_DMASR_TPS) == ETH_DMASR_TPS_Suspended) {
ETH->DMASR = ETH_DMASR_TBUS;
ETH->DMATPDR = ETH_DMASR_TBUS; /* Any value is OK.*/
}
chSysUnlock();
}
/**
* @brief Returns a receive descriptor.
*
* @param[in] macp pointer to the @p MACDriver object
* @param[out] rdp pointer to a @p MACReceiveDescriptor structure
* @return The operation status.
* @retval RDY_OK the descriptor has been obtained.
* @retval RDY_TIMEOUT descriptor not available.
*
* @notapi
*/
msg_t max_lld_get_receive_descriptor(MACDriver *macp,
MACReceiveDescriptor *rdp) {
stm32_eth_rx_descriptor_t *rdes;
chSysLock();
/* Get Current RX descriptor.*/
rdes = macp->rxptr;
/* Iterates through received frames until a valid one is found, invalid
frames are discarded.*/
while (!(rdes->rdes0 & STM32_RDES0_OWN)) {
if (!(rdes->rdes0 & (STM32_RDES0_AFM | STM32_RDES0_ES
#if STM32_IP_CHECKSUM_OFFLOAD
| STM32_RDES0_IPHCE | STM32_RDES0_PCE
#endif
)) && (rdes->rdes0 & STM32_RDES0_FS) &&
(rdes->rdes0 & STM32_RDES0_LS)) {
/* Found a valid one.*/
rdp->offset = 0;
rdp->size = ((rdes->rdes0 & STM32_RDES0_FL_MASK) >> 16) - 4;
rdp->physdesc = rdes;
macp->rxptr = (stm32_eth_rx_descriptor_t *)rdes->rdes3;
chSysUnlock();
return RDY_OK;
}
/* Invalid frame found, purging.*/
rdes->rdes0 = STM32_RDES0_OWN;
macp->rxptr = (stm32_eth_rx_descriptor_t *)rdes->rdes3;
}
chSysUnlock();
return RDY_TIMEOUT;
}
/**
* @brief Reads from a receive descriptor's stream.
*
* @param[in] rdp pointer to a @p MACReceiveDescriptor structure
* @param[in] buf pointer to the buffer that will receive the read data
* @param[in] size number of bytes to be read
* @return The number of bytes read from the descriptor's
* stream, this value can be less than the amount
* specified in the parameter @p size if there are
* no more bytes to read.
*
* @notapi
*/
size_t mac_lld_read_receive_descriptor(MACReceiveDescriptor *rdp,
uint8_t *buf,
size_t size) {
chDbgAssert(!(rdp->physdesc->rdes0 & STM32_RDES0_OWN),
"mac_lld_read_receive_descriptor(), #1",
"attempt to read descriptor already owned by DMA");
if (size > rdp->size - rdp->offset)
size = rdp->size - rdp->offset;
if (size > 0) {
memcpy(buf, (uint8_t *)(rdp->physdesc->rdes2) + rdp->offset, size);
rdp->offset += size;
}
return size;
}
/**
* @brief Releases a receive descriptor.
* @details The descriptor and its buffer are made available for more incoming
* frames.
*
* @param[in] rdp the pointer to the @p MACReceiveDescriptor structure
*
* @notapi
*/
void mac_lld_release_receive_descriptor(MACReceiveDescriptor *rdp) {
chDbgAssert(!(rdp->physdesc->rdes0 & STM32_RDES0_OWN),
"mac_lld_release_receive_descriptor(), #1",
"attempt to release descriptor already owned by DMA");
chSysLock();
/* Give buffer back to the Ethernet DMA.*/
rdp->physdesc->rdes0 = STM32_RDES0_OWN;
/* If the DMA engine is stalled then a restart request is issued.*/
if ((ETH->DMASR & ETH_DMASR_RPS) == ETH_DMASR_RPS_Suspended) {
ETH->DMASR = ETH_DMASR_RBUS;
ETH->DMARPDR = ETH_DMASR_RBUS; /* Any value is OK.*/
}
chSysUnlock();
}
/**
* @brief Updates and returns the link status.
*
* @param[in] macp pointer to the @p MACDriver object
* @return The link status.
* @retval TRUE if the link is active.
* @retval FALSE if the link is down.
*
* @notapi
*/
bool_t mac_lld_poll_link_status(MACDriver *macp) {
uint32_t maccr, bmsr, bmcr;
maccr = ETH->MACCR;
/* PHY CR and SR registers read.*/
(void)mii_read(macp, MII_BMSR);
bmsr = mii_read(macp, MII_BMSR);
bmcr = mii_read(macp, MII_BMCR);
/* Check on auto-negotiation mode.*/
if (bmcr & BMCR_ANENABLE) {
uint32_t lpa;
/* Auto-negotiation must be finished without faults and link established.*/
if ((bmsr & (BMSR_LSTATUS | BMSR_RFAULT | BMSR_ANEGCOMPLETE)) !=
(BMSR_LSTATUS | BMSR_ANEGCOMPLETE))
return macp->link_up = FALSE;
/* Auto-negotiation enabled, checks the LPA register.*/
lpa = mii_read(macp, MII_LPA);
/* Check on link speed.*/
if (lpa & (LPA_100HALF | LPA_100FULL | LPA_100BASE4))
maccr |= ETH_MACCR_FES;
else
maccr &= ~ETH_MACCR_FES;
/* Check on link mode.*/
if (lpa & (LPA_10FULL | LPA_100FULL))
maccr |= ETH_MACCR_DM;
else
maccr &= ~ETH_MACCR_DM;
}
else {
/* Link must be established.*/
if (!(bmsr & BMSR_LSTATUS))
return macp->link_up = FALSE;
/* Check on link speed.*/
if (bmcr & BMCR_SPEED100)
maccr |= ETH_MACCR_FES;
else
maccr &= ~ETH_MACCR_FES;
/* Check on link mode.*/
if (bmcr & BMCR_FULLDPLX)
maccr |= ETH_MACCR_DM;
else
maccr &= ~ETH_MACCR_DM;
}
/* Changes the mode in the MAC.*/
ETH->MACCR = maccr;
/* Returns the link status.*/
return macp->link_up = TRUE;
}
#endif /* HAL_USE_MAC */
/** @} */

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os/hal/platforms/STM32/mac_lld.h Normal file
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/*
ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
2011,2012 Giovanni Di Sirio.
This file is part of ChibiOS/RT.
ChibiOS/RT is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
ChibiOS/RT is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
---
A special exception to the GPL can be applied should you wish to distribute
a combined work that includes ChibiOS/RT, without being obliged to provide
the source code for any proprietary components. See the file exception.txt
for full details of how and when the exception can be applied.
*/
/**
* @file STM32/mac_lld.h
* @brief STM32 low level MAC driver header.
*
* @addtogroup MAC
* @{
*/
#ifndef _MAC_LLD_H_
#define _MAC_LLD_H_
#if HAL_USE_MAC || defined(__DOXYGEN__)
/*===========================================================================*/
/* Driver constants. */
/*===========================================================================*/
/**
* @name RDES0 constants
* @{
*/
#define STM32_RDES0_OWN 0x80000000
#define STM32_RDES0_AFM 0x40000000
#define STM32_RDES0_FL_MASK 0x3FFF0000
#define STM32_RDES0_ES 0x00008000
#define STM32_RDES0_DESERR 0x00004000
#define STM32_RDES0_SAF 0x00002000
#define STM32_RDES0_LE 0x00001000
#define STM32_RDES0_OE 0x00000800
#define STM32_RDES0_VLAN 0x00000400
#define STM32_RDES0_FS 0x00000200
#define STM32_RDES0_LS 0x00000100
#define STM32_RDES0_IPHCE 0x00000080
#define STM32_RDES0_LCO 0x00000040
#define STM32_RDES0_FT 0x00000020
#define STM32_RDES0_RWT 0x00000010
#define STM32_RDES0_RE 0x00000008
#define STM32_RDES0_DE 0x00000004
#define STM32_RDES0_CE 0x00000002
#define STM32_RDES0_PCE 0x00000001
/** @} */
/**
* @name RDES1 constants
* @{
*/
#define STM32_RDES1_DIC 0x80000000
#define STM32_RDES1_RBS2_MASK 0x1FFF0000
#define STM32_RDES1_RER 0x00008000
#define STM32_RDES1_RCH 0x00004000
#define STM32_RDES1_RBS1_MASK 0x00001FFF
/** @} */
/**
* @name TDES0 constants
* @{
*/
#define STM32_TDES0_OWN 0x80000000
#define STM32_TDES0_IC 0x40000000
#define STM32_TDES0_LS 0x20000000
#define STM32_TDES0_FS 0x10000000
#define STM32_TDES0_DC 0x08000000
#define STM32_TDES0_DP 0x04000000
#define STM32_TDES0_TTSE 0x02000000
#define STM32_TDES0_LOCKED 0x01000000 /* NOTE: Pseudo flag. */
#define STM32_TDES0_CIC_MASK 0x00C00000
#define STM32_TDES0_CIC(n) ((n) << 22)
#define STM32_TDES0_TER 0x00200000
#define STM32_TDES0_TCH 0x00100000
#define STM32_TDES0_TTSS 0x00020000
#define STM32_TDES0_IHE 0x00010000
#define STM32_TDES0_ES 0x00008000
#define STM32_TDES0_JT 0x00004000
#define STM32_TDES0_FF 0x00002000
#define STM32_TDES0_IPE 0x00001000
#define STM32_TDES0_LCA 0x00000800
#define STM32_TDES0_NC 0x00000400
#define STM32_TDES0_LCO 0x00000200
#define STM32_TDES0_EC 0x00000100
#define STM32_TDES0_VF 0x00000080
#define STM32_TDES0_CC_MASK 0x00000078
#define STM32_TDES0_ED 0x00000004
#define STM32_TDES0_UF 0x00000002
#define STM32_TDES0_DB 0x00000001
/** @} */
/**
* @name TDES1 constants
* @{
*/
#define STM32_TDES1_TBS2_MASK 0x1FFF0000
#define STM32_TDES1_TBS1_MASK 0x00001FFF
/** @} */
/*===========================================================================*/
/* Driver pre-compile time settings. */
/*===========================================================================*/
/**
* @name Configuration options
* @{
*/
/**
* @brief Number of available transmit buffers.
*/
#if !defined(MAC_TRANSMIT_BUFFERS) || defined(__DOXYGEN__)
#define STM32_MAC_TRANSMIT_BUFFERS 2
#endif
/**
* @brief Number of available receive buffers.
*/
#if !defined(MAC_RECEIVE_BUFFERS) || defined(__DOXYGEN__)
#define STM32_MAC_RECEIVE_BUFFERS 4
#endif
/**
* @brief Maximum supported frame size.
*/
#if !defined(MAC_BUFFERS_SIZE) || defined(__DOXYGEN__)
#define STM32_MAC_BUFFERS_SIZE 1518
#endif
/**
* @brief PHY detection timeout.
* @details Timeout, in milliseconds, for PHY address detection, if a PHY
* is not detected within the timeout then the driver halts during
* initialization. This setting applies only if the PHY address is
* not explicitly set in the board header file using
* @p BOARD_PHY_ADDRESS. A zero value disables the timeout and a
* single search path is performed.
*/
#if !defined(STM32_MAC_PHY_TIMEOUT) || defined(__DOXYGEN__)
#define STM32_MAC_PHY_TIMEOUT 100
#endif
/**
* @brief ETHD1 interrupt priority level setting.
*/
#if !defined(STM32_ETH1_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define STM32_ETH1_IRQ_PRIORITY 13
#endif
/**
* @brief IP checksum offload.
* @details The following modes are available:
* - 0 Function disabled.
* - 1 Only IP header checksum calculation and insertion are enabled.
* - 2 IP header checksum and payload checksum calculation and
* insertion are enabled, but pseudo-header checksum is not
* calculated in hardware.
* - 3 IP Header checksum and payload checksum calculation and
* insertion are enabled, and pseudo-header checksum is
* calculated in hardware.
* .
*/
#if !defined(STM32_IP_CHECKSUM_OFFLOAD) || defined(__DOXYGEN__)
#define STM32_IP_CHECKSUM_OFFLOAD 0
#endif
/** @} */
/*===========================================================================*/
/* Derived constants and error checks. */
/*===========================================================================*/
#if (STM32_MAC_PHY_TIMEOUT > 0) && !HAL_IMPLEMENTS_COUNTERS
#error "STM32_MAC_PHY_TIMEOUT requires the realtime counter service"
#endif
/*===========================================================================*/
/* Driver data structures and types. */
/*===========================================================================*/
/**
* @brief Type of an STM32 Ethernet receive descriptor.
*/
typedef struct {
volatile uint32_t rdes0;
volatile uint32_t rdes1;
volatile uint32_t rdes2;
volatile uint32_t rdes3;
} stm32_eth_rx_descriptor_t;
/**
* @brief Type of an STM32 Ethernet transmit descriptor.
*/
typedef struct {
volatile uint32_t tdes0;
volatile uint32_t tdes1;
volatile uint32_t tdes2;
volatile uint32_t tdes3;
} stm32_eth_tx_descriptor_t;
/**
* @brief Driver configuration structure.
*/
typedef struct {
/**
* @brief MAC address.
*/
uint8_t *mac_address;
/* End of the mandatory fields.*/
} MACConfig;
/**
* @brief Structure representing a MAC driver.
*/
struct MACDriver {
/**
* @brief Driver state.
*/
macstate_t state;
/**
* @brief Current configuration data.
*/
const MACConfig *config;
/**
* @brief Transmit semaphore.
*/
Semaphore tdsem;
/**
* @brief Receive semaphore.
*/
Semaphore rdsem;
#if MAC_USE_EVENTS || defined(__DOXYGEN__)
/**
* @brief Receive event.
*/
EventSource rdevent;
#endif
/* End of the mandatory fields.*/
/**
* @brief Link status flag.
*/
bool_t link_up;
/**
* @brief PHY address (pre shifted).
*/
uint32_t phyaddr;
/**
* @brief Receive next frame pointer.
*/
stm32_eth_rx_descriptor_t *rxptr;
/**
* @brief Transmit next frame pointer.
*/
stm32_eth_tx_descriptor_t *txptr;
};
/**
* @brief Structure representing a transmit descriptor.
*/
typedef struct {
/**
* @brief Current write offset.
*/
size_t offset;
/**
* @brief Available space size.
*/
size_t size;
/* End of the mandatory fields.*/
/**
* @brief Pointer to the physical descriptor.
*/
stm32_eth_tx_descriptor_t *physdesc;
} MACTransmitDescriptor;
/**
* @brief Structure representing a receive descriptor.
*/
typedef struct {
/**
* @brief Current read offset.
*/
size_t offset;
/**
* @brief Available data size.
*/
size_t size;
/* End of the mandatory fields.*/
/**
* @brief Pointer to the physical descriptor.
*/
stm32_eth_rx_descriptor_t *physdesc;
} MACReceiveDescriptor;
/*===========================================================================*/
/* Driver macros. */
/*===========================================================================*/
/*===========================================================================*/
/* External declarations. */
/*===========================================================================*/
#if !defined(__DOXYGEN__)
extern MACDriver ETHD1;
#endif
#ifdef __cplusplus
extern "C" {
#endif
void mac_lld_init(void);
void mac_lld_start(MACDriver *macp);
void mac_lld_stop(MACDriver *macp);
msg_t max_lld_get_transmit_descriptor(MACDriver *macp,
MACTransmitDescriptor *tdp);
size_t mac_lld_write_transmit_descriptor(MACTransmitDescriptor *tdp,
uint8_t *buf,
size_t size);
void mac_lld_release_transmit_descriptor(MACTransmitDescriptor *tdp);
msg_t max_lld_get_receive_descriptor(MACDriver *macp,
MACReceiveDescriptor *rdp);
size_t mac_lld_read_receive_descriptor(MACReceiveDescriptor *rdp,
uint8_t *buf,
size_t size);
void mac_lld_release_receive_descriptor(MACReceiveDescriptor *rdp);
bool_t mac_lld_poll_link_status(MACDriver *macp);
#ifdef __cplusplus
}
#endif
#endif /* HAL_USE_MAC */
#endif /* _MAC_LLD_H_ */
/** @} */

15
os/hal/platforms/STM32F2xx/platform.dox
View File

@ -131,6 +131,21 @@
* @ingroup STM32F2xx_DRIVERS
*/
/**
* @defgroup STM32F2xx_MAC STM32F2xx MAC Support
* @details The STM32F2xx MAC driver supports the ETH peripheral.
*
* @section stm32f2xx_mac_1 Supported HW resources
* - ETH.
* - PHY (external).
* .
* @section stm32f2xx_mac_2 STM32F2xx MAC driver implementation features
* - Dedicated DMA operations.
* - Support for checksum off-loading.
* .
* @ingroup STM32F2xx_DRIVERS
*/
/**
* @defgroup STM32F2xx_PAL STM32F2xx PAL Support
* @details The STM32F2xx PAL driver uses the GPIO peripherals.

2
os/hal/platforms/STM32F2xx/platform.mk
View File

@ -6,6 +6,7 @@ PLATFORMSRC = ${CHIBIOS}/os/hal/platforms/STM32F2xx/stm32_dma.c \
${CHIBIOS}/os/hal/platforms/STM32/gpt_lld.c \
${CHIBIOS}/os/hal/platforms/STM32/i2c_lld.c \
${CHIBIOS}/os/hal/platforms/STM32/icu_lld.c \
${CHIBIOS}/os/hal/platforms/STM32/mac_lld.c \
${CHIBIOS}/os/hal/platforms/STM32/pwm_lld.c \
${CHIBIOS}/os/hal/platforms/STM32/serial_lld.c \
${CHIBIOS}/os/hal/platforms/STM32/spi_lld.c \
@ -18,4 +19,3 @@ PLATFORMINC = ${CHIBIOS}/os/hal/platforms/STM32F2xx \
${CHIBIOS}/os/hal/platforms/STM32/GPIOv2 \
${CHIBIOS}/os/hal/platforms/STM32/RTCv2 \

66
os/hal/platforms/STM32F2xx/stm32_rcc.h
View File

@ -429,6 +429,42 @@
#define rccResetPWRInterface() rccResetAPB1(RCC_APB1ENR_BKPRST)
/** @} */
/**
* @name ETH peripheral specific RCC operations
* @{
*/
/**
* @brief Enables the ETH peripheral clock.
* @note The @p lp parameter is ignored in this family.
*
* @param[in] lp low power enable flag
*
* @api
*/
#define rccEnableETH(lp) rccEnableAHB1(RCC_AHB1ENR_ETHMACEN | \
RCC_AHB1ENR_ETHMACTXEN | \
RCC_AHB1ENR_ETHMACRXEN, lp)
/**
* @brief Disables the ETH peripheral clock.
* @note The @p lp parameter is ignored in this family.
*
* @param[in] lp low power enable flag
*
* @api
*/
#define rccDisableETH(lp) rccDisableAHB1(RCC_AHB1ENR_ETHMACEN | \
RCC_AHB1ENR_ETHMACTXEN | \
RCC_AHB1ENR_ETHMACRXEN, lp)
/**
* @brief Resets the ETH peripheral.
*
* @api
*/
#define rccResetETH() rccResetAHB1(RCC_AHB1RSTR_ETHMACRST)
/** @} */
/**
* @name I2C peripherals specific RCC operations
* @{
@ -509,6 +545,36 @@
#define rccResetI2C3() rccResetAPB1(RCC_APB1RSTR_I2C3RST)
/** @} */
/**
* @name OTG peripherals specific RCC operations
* @{
*/
/**
* @brief Enables the OTG_FS peripheral clock.
*
* @param[in] lp low power enable flag
*
* @api
*/
#define rccEnableOTG_FS(lp) rccEnableAHB2(RCC_AHB2LPENR_OTGFSLPEN, lp)
/**
* @brief Disables the OTG_FS peripheral clock.
*
* @param[in] lp low power enable flag
*
* @api
*/
#define rccDisableOTG_FS(lp) rccEnableAHB2(RCC_AHB2LPENR_OTGFSLPEN, lp)
/**
* @brief Resets the OTG_FS peripheral.
*
* @api
*/
#define rccResetOTG_FS() rccResetAHB2(RCC_AHB2RSTR_OTGFSRST)
/** @} */
/**
* @name SPI peripherals specific RCC operations
* @{

6
os/hal/platforms/STM32F2xx/stm32f2xx.h
View File

@ -5707,7 +5707,11 @@ typedef struct
#define SYSCFG_MEMRMP_MEM_MODE_1 ((uint32_t)0x00000002)
/****************** Bit definition for SYSCFG_PMC register ******************/
#define SYSCFG_PMC_MII_RMII ((uint16_t)0x0080) /*!<Ethernet PHY interface selection */
/* CHIBIOS FIX */
#define SYSCFG_PMC_MII_RMII_SEL ((uint32_t)0x00800000) /*!<Ethernet PHY interface selection */
/* Old MII_RMII_SEL bit definition, maintained for legacy purpose */
#define SYSCFG_PMC_MII_RMII SYSCFG_PMC_MII_RMII_SEL
/*#define SYSCFG_PMC_MII_RMII ((uint16_t)0x0080)*/ /*!<Ethernet PHY interface selection */
/***************** Bit definition for SYSCFG_EXTICR1 register ***************/
#define SYSCFG_EXTICR1_EXTI0 ((uint16_t)0x000F) /*!<EXTI 0 configuration */

15
os/hal/platforms/STM32F4xx/platform.dox
View File

@ -131,6 +131,21 @@
* @ingroup STM32F4xx_DRIVERS
*/
/**
* @defgroup STM32F4xx_MAC STM32F4xx MAC Support
* @details The STM32F4xx MAC driver supports the ETH peripheral.
*
* @section stm32f4xx_mac_1 Supported HW resources
* - ETH.
* - PHY (external).
* .
* @section stm32f4xx_mac_2 STM32F4xx MAC driver implementation features
* - Dedicated DMA operations.
* - Support for checksum off-loading.
* .
* @ingroup STM32F4xx_DRIVERS
*/
/**
* @defgroup STM32F4xx_PAL STM32F4xx PAL Support
* @details The STM32F4xx PAL driver uses the GPIO peripherals.

1
os/hal/platforms/STM32F4xx/platform.mk
View File

@ -6,6 +6,7 @@ PLATFORMSRC = ${CHIBIOS}/os/hal/platforms/STM32F4xx/stm32_dma.c \
${CHIBIOS}/os/hal/platforms/STM32/gpt_lld.c \
${CHIBIOS}/os/hal/platforms/STM32/i2c_lld.c \
${CHIBIOS}/os/hal/platforms/STM32/icu_lld.c \
${CHIBIOS}/os/hal/platforms/STM32/mac_lld.c \
${CHIBIOS}/os/hal/platforms/STM32/pwm_lld.c \
${CHIBIOS}/os/hal/platforms/STM32/serial_lld.c \
${CHIBIOS}/os/hal/platforms/STM32/spi_lld.c \

99
os/hal/platforms/STM32F4xx/stm32_rcc.h
View File

@ -429,6 +429,42 @@
#define rccResetPWRInterface() rccResetAPB1(RCC_APB1ENR_BKPRST)
/** @} */
/**
* @name ETH peripheral specific RCC operations
* @{
*/
/**
* @brief Enables the ETH peripheral clock.
* @note The @p lp parameter is ignored in this family.
*
* @param[in] lp low power enable flag
*
* @api
*/
#define rccEnableETH(lp) rccEnableAHB1(RCC_AHB1ENR_ETHMACEN | \
RCC_AHB1ENR_ETHMACTXEN | \
RCC_AHB1ENR_ETHMACRXEN, lp)
/**
* @brief Disables the ETH peripheral clock.
* @note The @p lp parameter is ignored in this family.
*
* @param[in] lp low power enable flag
*
* @api
*/
#define rccDisableETH(lp) rccDisableAHB1(RCC_AHB1ENR_ETHMACEN | \
RCC_AHB1ENR_ETHMACTXEN | \
RCC_AHB1ENR_ETHMACRXEN, lp)
/**
* @brief Resets the ETH peripheral.
*
* @api
*/
#define rccResetETH() rccResetAHB1(RCC_AHB1RSTR_ETHMACRST)
/** @} */
/**
* @name I2C peripherals specific RCC operations
* @{
@ -509,6 +545,69 @@
#define rccResetI2C3() rccResetAPB1(RCC_APB1RSTR_I2C3RST)
/** @} */
/**
* @name OTG peripherals specific RCC operations
* @{
*/
/**
* @brief Enables the OTG_FS peripheral clock.
*
* @param[in] lp low power enable flag
*
* @api
*/
#define rccEnableOTG_FS(lp) rccEnableAHB2(RCC_AHB2LPENR_OTGFSLPEN, lp)
/**
* @brief Disables the OTG_FS peripheral clock.
*
* @param[in] lp low power enable flag
*
* @api
*/
#define rccDisableOTG_FS(lp) rccEnableAHB2(RCC_AHB2LPENR_OTGFSLPEN, lp)
/**
* @brief Resets the OTG_FS peripheral.
*
* @api
*/
#define rccResetOTG_FS() rccResetAHB2(RCC_AHB2RSTR_OTGFSRST)
/** @} */
/**
* @name SDIO peripheral specific RCC operations
* @{
*/
/**
* @brief Enables the SDIO peripheral clock.
* @note The @p lp parameter is ignored in this family.
*
* @param[in] lp low power enable flag
*
* @api
*/
#define rccEnableSDIO(lp) rccEnableAPB2(RCC_APB2ENR_SDIOEN, lp)
/**
* @brief Disables the SDIO peripheral clock.
* @note The @p lp parameter is ignored in this family.
*
* @param[in] lp low power enable flag
*
* @api
*/
#define rccDisableSDIO(lp) rccDisableAPB2(RCC_APB2ENR_SDIOEN, lp)
/**
* @brief Resets the SDIO peripheral.
* @note Not supported in this family, does nothing.
*
* @api
*/
#define rccResetSDIO() rccResetAPB2(RCC_APB2RSTR_SDIORST)
/** @} */
/**
* @name SPI peripherals specific RCC operations
* @{

1
readme.txt
View File

@ -100,6 +100,7 @@
- FIX: Fixed ADC maximum frequency limit in STM32F2/F4 ADC drivers (bug
3484947).
- FIX: Fixed various minor documentation errors (bug 3484942).
- NEW: STM32 Ethernet driver added.
- NEW: Updated the MSP port to work with the latest MSPGCC compiler (4.6.3
LTS 20120406 unpatched), now the old MSPGCC 3.2.3 is no more supported.