From d406508ef0e257b9ba46d2ebc797bf160fabb8ec Mon Sep 17 00:00:00 2001 From: Giovanni Di Sirio Date: Fri, 21 May 2021 17:54:28 +0000 Subject: [PATCH] git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@14413 27425a3e-05d8-49a3-a47f-9c15f0e5edd8 --- os/hal/ports/STM32/STM32L4xx+/hal_lld.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/os/hal/ports/STM32/STM32L4xx+/hal_lld.c b/os/hal/ports/STM32/STM32L4xx+/hal_lld.c index bfa6b7a10..580f53976 100644 --- a/os/hal/ports/STM32/STM32L4xx+/hal_lld.c +++ b/os/hal/ports/STM32/STM32L4xx+/hal_lld.c @@ -36,7 +36,8 @@ /** * @brief FLASH_ACR reset value. */ -#define STM32_FLASH_ACR_RESET 0x00000600U +#define STM32_FLASH_ACR_RESET (FLASH_ACR_DCEN | FLASH_ACR_ICEN | \ + FLASH_ACR_LATENCY_0WS) /** * @brief MSI range array size. @@ -69,8 +70,7 @@ const halclkcfg_t hal_clkcfg_reset = { .rcc_pllsai1cfgr = 0U, .rcc_pllsai2cfgr = 0U, .rcc_crrcr = 0U, - .flash_acr = FLASH_ACR_DCEN | FLASH_ACR_ICEN | - FLASH_ACR_LATENCY_0WS + .flash_acr = STM32_FLASH_ACR_RESET }; /**