From d4bb13cec9478c04d1ac0cc95d3ed0fab5957ba8 Mon Sep 17 00:00:00 2001
From: Giovanni Di Sirio <gdisirio@gmail.com>
Date: Sat, 8 Feb 2020 11:23:54 +0000
Subject: [PATCH] SPI test at maximum speed.

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@13333 27425a3e-05d8-49a3-a47f-9c15f0e5edd8
---
 testhal/STM32/multi/SPI/cfg/stm32h755_nucleo144/mcuconf.h | 2 +-
 testhal/STM32/multi/SPI/cfg/stm32h755_nucleo144/portab.c  | 8 ++++----
 2 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/testhal/STM32/multi/SPI/cfg/stm32h755_nucleo144/mcuconf.h b/testhal/STM32/multi/SPI/cfg/stm32h755_nucleo144/mcuconf.h
index 25afb6e44..ea8447967 100644
--- a/testhal/STM32/multi/SPI/cfg/stm32h755_nucleo144/mcuconf.h
+++ b/testhal/STM32/multi/SPI/cfg/stm32h755_nucleo144/mcuconf.h
@@ -91,7 +91,7 @@
 #define STM32_PLL1_DIVN_VALUE               480
 #define STM32_PLL1_FRACN_VALUE              0
 #define STM32_PLL1_DIVP_VALUE               2
-#define STM32_PLL1_DIVQ_VALUE               20
+#define STM32_PLL1_DIVQ_VALUE               4
 #define STM32_PLL1_DIVR_VALUE               8
 #define STM32_PLL2_ENABLED                  TRUE
 #define STM32_PLL2_P_ENABLED                TRUE
diff --git a/testhal/STM32/multi/SPI/cfg/stm32h755_nucleo144/portab.c b/testhal/STM32/multi/SPI/cfg/stm32h755_nucleo144/portab.c
index 86f9d0948..6e0800570 100644
--- a/testhal/STM32/multi/SPI/cfg/stm32h755_nucleo144/portab.c
+++ b/testhal/STM32/multi/SPI/cfg/stm32h755_nucleo144/portab.c
@@ -37,7 +37,7 @@
 void spi_circular_cb(SPIDriver *spip);
 
 /*
- * Circular SPI configuration (25MHz, CPHA=0, CPOL=0, MSb first).
+ * Circular SPI configuration (30MHz, CPHA=0, CPOL=0, MSb first).
  */
 const SPIConfig c_spicfg = {
   true,
@@ -49,19 +49,19 @@ const SPIConfig c_spicfg = {
 };
 
 /*
- * Maximum speed SPI configuration (25MHz, CPHA=0, CPOL=0, MSb first).
+ * Maximum speed SPI configuration (120MHz, CPHA=0, CPOL=0, MSb first).
  */
 const SPIConfig hs_spicfg = {
   false,
   NULL,
   GPIOD,
   14,
-  SPI_CFG1_MBR_DIV8 | SPI_CFG1_DSIZE_VALUE(7),
+  SPI_CFG1_MBR_DIV2 | SPI_CFG1_DSIZE_VALUE(7),
   0
 };
 
 /*
- * Low speed SPI configuration (1.5625MHz, CPHA=0, CPOL=0, MSb first).
+ * Low speed SPI configuration (1,875MHz, CPHA=0, CPOL=0, MSb first).
  */
 const SPIConfig ls_spicfg = {
   false,