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git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@13536 27425a3e-05d8-49a3-a47f-9c15f0e5edd8

This commit is contained in:
Giovanni Di Sirio 2020-04-16 08:04:24 +00:00
parent 84370eb21a
commit d4dba0c3cb
9 changed files with 105 additions and 56 deletions
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2
demos/STM32/RT-STM32L552ZE-NUCLEO144-TZ_HOST/Makefile
View File

@ -154,9 +154,11 @@ CPPWARN = -Wall -Wextra -Wundef
UDEFS =
UDEFS += -D__ARM_FEATURE_CMSE=3 # It is already intrinsic because -mcmse, added
# again to make it discoverable by Eclipse.
UDEFS += -DPORT_KERNEL_MODE=PORT_KERNEL_MODE_HOST
# Define ASM defines here
UADEFS =
UADEFS += -DPORT_KERNEL_MODE=PORT_KERNEL_MODE_HOST
# List all user directories here
UINCDIR =

21
os/common/ports/ARMv8-M-ML/chcore.h
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@ -160,7 +160,7 @@
* @brief Kernel mode selection.
*/
#if !defined(PORT_KERNEL_MODE) || defined(__DOXYGEN__)
#define PORT_KERNEL_MODE PORT_KERNEL_MODE_HOST
#define PORT_KERNEL_MODE PORT_KERNEL_MODE_NORMAL
#endif
/**
@ -285,6 +285,12 @@
*/
#define CORTEX_PRIORITY_PENDSV (CORTEX_MINIMUM_PRIORITY)
/**
* @brief Maximum usable priority for normal ISRs.
* @note Must be lower than @p CORTEX_PRIORITY_SVCALL.
*/
#define CORTEX_MAX_KERNEL_PRIORITY (CORTEX_PRIORITY_SVCALL + 1)
#elif PORT_KERNEL_MODE == PORT_KERNEL_MODE_HOST
#define PORT_EXC_RETURN 0xFFFFFFFD
#if CORTEX_USE_FPU == TRUE
@ -299,25 +305,22 @@
#define CORTEX_PRIORITY_SVCALL (CORTEX_MAXIMUM_PRIORITY + \
CORTEX_FAST_PRIORITIES)
#define CORTEX_PRIORITY_PENDSV (CORTEX_MINIMUM_PRIORITY / 2)
#define CORTEX_MAX_KERNEL_PRIORITY (CORTEX_PRIORITY_SVCALL + 1)
#elif PORT_KERNEL_MODE == PORT_KERNEL_MODE_GUEST
#define PORT_EXC_RETURN 0xFFFFFFBC
#define PORT_CONTEXT_RESERVED_SIZE (sizeof (struct port_intctx))
#define PORT_INFO "Non-secure guest mode"
#define CORTEX_BASEPRI_DISABLED CORTEX_PRIO_MASK(0)
#define CORTEX_PRIORITY_SVCALL ((CORTEX_MAXIMUM_PRIORITY + \
#define CORTEX_PRIORITY_SVCALL (CORTEX_MAXIMUM_PRIORITY + \
CORTEX_FAST_PRIORITIES)
#define CORTEX_PRIORITY_PENDSV (CORTEX_MINIMUM_PRIORITY & 0xFFFFFFFE)
#define CORTEX_MAX_KERNEL_PRIORITY ((CORTEX_PRIORITY_SVCALL | 1) + 1)
#else
#error "invalid kernel security mode"
#endif
/**
* @brief Maximum usable priority for normal ISRs.
* @note Must be lower than @p CORTEX_PRIORITY_SVCALL.
*/
#define CORTEX_MAX_KERNEL_PRIORITY (CORTEX_PRIORITY_SVCALL + 1)
/**
* @brief BASEPRI level within kernel lock.
*/
@ -491,7 +494,7 @@ struct port_context {
* @brief Priority level verification macro.
*/
#define PORT_IRQ_IS_VALID_KERNEL_PRIORITY(n) \
(((n) > CORTEX_PRIORITY_SVCALL) && ((n) <= CORTEX_PRIORITY_PENDSV))
(((n) >= CORTEX_MAX_KERNEL_PRIORITY) && ((n) <= CORTEX_PRIORITY_PENDSV))
/**
* @brief Initialization of stack check part of thread context.

87
os/common/ports/ARMv8-M-ML/compilers/GCC/chcoreasm.S
View File

@ -71,7 +71,7 @@
.syntax unified
.cpu cortex-m33
#if CORTEX_USE_FPU
.fpu fpv4-sp-d16
.fpu fpv5-sp-d16
#else
.fpu softvfp
#endif
@ -84,26 +84,24 @@
*--------------------------------------------------------------------------*/
#if !CH_DBG_ENABLE_STACK_CHECK
.macro PORT_STORE_INTEGER_CONTEXT_R1
mrs r2, PSP
.macro PORT_STORE_INTEGER_CONTEXT
mrs r3, BASEPRI
stmia r1!, {r2-r11,lr}
.endm
.macro PORT_RESTORE_INTEGER_CONTEXT_R0
.macro PORT_RESTORE_INTEGER_CONTEXT
ldmia r0!, {r2-r11, lr}
msr PSP, r2
msr BASEPRI, r3
.endm
#else /* CH_DBG_ENABLE_STACK_CHECK */
.macro PORT_STORE_INTEGER_CONTEXT_R1
mrs r2, PSP
.macro PORT_STORE_INTEGER_CONTEXT
mrs r3, BASEPRI
mrs r12, PSPLIM
stmia r1!, {r2-r12,lr}
.endm
.macro PORT_RESTORE_INTEGER_CONTEXT_R0
.macro PORT_RESTORE_INTEGER_CONTEXT
ldmia r0!, {r2-r12, lr}
/* Note the following is not required because this sentence
in the ARMv8-M architecture manual:
@ -121,18 +119,18 @@
#endif
#if CORTEX_USE_FPU
.macro PORT_STORE_FLOAT_CONTEXT_R1
.macro PORT_STORE_FLOAT_CONTEXT
vstmia r1!, {s16-s31}
.endm
.macro PORT_RESTORE_FLOAT_CONTEXT_R0
.macro PORT_RESTORE_FLOAT_CONTEXT
vldmia r0!, {s16-s31}
.endm
#else
.macro PORT_STORE_FLOAT_CONTEXT_R1
.macro PORT_STORE_FLOAT_CONTEXT
.endm
.macro PORT_RESTORE_FLOAT_CONTEXT_R0
.macro PORT_RESTORE_FLOAT_CONTEXT
.endm
#endif
@ -143,22 +141,25 @@
.globl SVC_Handler
SVC_Handler:
/* Saving callee context of thread being swapped out.*/
mrs r2, PSP
ldr r1, [r2, #4] /* R1 on SVC entry (otp). */
adds r1, #CONTEXT_OFFSET
/* Storing integer and control context through R1.*/
PORT_STORE_INTEGER_CONTEXT_R1
/* Storing integer and control context.*/
PORT_STORE_INTEGER_CONTEXT
/* Storing float context through R1.*/
PORT_STORE_FLOAT_CONTEXT_R1
/* Storing float context.*/
PORT_STORE_FLOAT_CONTEXT
/* Restoring calle context of thread being swapped in.*/
ldr r0, [r2, #0] /* R0 on SVC entry (ntp). */
adds r0, #CONTEXT_OFFSET
/* Restoring integer and control context through R0.*/
PORT_RESTORE_INTEGER_CONTEXT_R0
PORT_RESTORE_INTEGER_CONTEXT
/* Restoring float context through R0.*/
PORT_RESTORE_FLOAT_CONTEXT_R0
/* Restoring float context.*/
PORT_RESTORE_FLOAT_CONTEXT
bx lr
@ -177,11 +178,12 @@ PendSV_Handler:
/* Saving callee context of thread being swapped out.*/
adds r1, #CONTEXT_OFFSET
/* Storing integer and control context through R1.*/
PORT_STORE_INTEGER_CONTEXT_R1
/* Storing integer and control context.*/
mrs r2, PSP
PORT_STORE_INTEGER_CONTEXT
/* Storing float context through R1.*/
PORT_STORE_FLOAT_CONTEXT_R1
/* Storing float context.*/
PORT_STORE_FLOAT_CONTEXT
/* Selecting the thread to be swapped in, R0 points to it.*/
bl port_schedule_next
@ -189,11 +191,11 @@ PendSV_Handler:
/* Restoring calle context of thread being swapped in.*/
adds r0, #CONTEXT_OFFSET
/* Restoring integer and control context through R0.*/
PORT_RESTORE_INTEGER_CONTEXT_R0
/* Restoring integer and control context.*/
PORT_RESTORE_INTEGER_CONTEXT
/* Restoring float context through R0.*/
PORT_RESTORE_FLOAT_CONTEXT_R0
/* Restoring float context.*/
PORT_RESTORE_FLOAT_CONTEXT
bx lr
@ -238,23 +240,24 @@ __port_ns_boot:
movs r12, #0
movs lr, #0
#if CORTEX_USE_FPU
vldr.64 d0, =0
vldr.64 d1, =0
vldr.64 d2, =0
vldr.64 d3, =0
vldr.64 d4, =0
vldr.64 d5, =0
vldr.64 d6, =0
vldr.64 d7, =0
vldr.64 d8, =0
vldr.64 d9, =0
vldr.64 d10, =0
vldr.64 d11, =0
vldr.64 d12, =0
vldr.64 d13, =0
vldr.64 d14, =0
vldr.64 d15, =0
vmov s0, s1, r3, r3
vmov s2, s3, r3, r3
vmov s4, s5, r3, r3
vmov s6, s7, r3, r3
vmov s8, s9, r3, r3
vmov s10, s11, r3, r3
vmov s12, s13, r3, r3
vmov s14, s15, r3, r3
vmov s16, s17, r3, r3
vmov s18, s19, r3, r3
vmov s20, s21, r3, r3
vmov s22, s23, r3, r3
vmov s24, s25, r3, r3
vmov s26, s27, r3, r3
vmov s28, s29, r3, r3
vmov s30, s31, r3, r3
#endif
msr APSR_nzcvqg, r3
msr BASEPRI, r3 /* Allowing NS-PendSV in NS state.*/
msr PSPLIM_NS, r3
msr MSPLIM_NS, r3

4
os/hal/ports/STM32/STM32L5xx/hal_lld.c
View File

@ -46,7 +46,7 @@ uint32_t SystemCoreClock = STM32_HCLK;
/* Driver local functions. */
/*===========================================================================*/
static inline void bd_init(void) {
__STATIC_INLINE void bd_init(void) {
/* Reset BKP domain if different clock source selected.*/
if ((RCC->BDCR & STM32_RTCSEL_MASK) != STM32_RTCSEL) {
@ -73,7 +73,7 @@ static inline void bd_init(void) {
RCC->BDCR |= STM32_LSCOSEL;
}
static void flash_ws_init(uint32_t bits) {
__STATIC_INLINE void flash_ws_init(uint32_t bits) {
FLASH->ACR = (FLASH->ACR & ~FLASH_ACR_LATENCY_Msk) | bits;
while ((FLASH->ACR & FLASH_ACR_LATENCY_Msk) != (bits & FLASH_ACR_LATENCY_Msk)) {

6
os/hal/ports/STM32/STM32L5xx/hal_lld.h
View File

@ -806,9 +806,6 @@
#include "stm32_hsi48.inc"
#include "stm32_hse.inc"
/* Secure mode handler.*/
#include "stm32_secure.inc"
/*
* Platform HSI16-related checks.
*/
@ -1783,6 +1780,9 @@
#include "stm32_rcc.h"
#include "stm32_tim.h"
/* Secure mode handler.*/
#include "stm32_secure.inc"
#ifdef __cplusplus
extern "C" {
#endif

29
os/hal/ports/STM32/STM32L5xx/stm32_rcc.h
View File

@ -498,6 +498,35 @@
* @api
*/
#define rccResetFDCAN1() rccResetAPB1R2(RCC_APB1RSTR2_FDCAN1RST)
/** @} */
/**
* @name GTZC specific RCC operations
* @{
*/
/**
* @brief Enables the GTZC peripheral clock.
*
* @param[in] lp low power enable flag
*
* @api
*/
#define rccEnableGTZC(lp) rccEnableAHB1(RCC_AHB1ENR_GTZCEN, lp)
/**
* @brief Disables the GTZC peripheral clock.
*
* @api
*/
#define rccDisableGTZC() rccDisableAHB1(RCC_AHB1ENR_GTZCEN)
/**
* @brief Resets the GTZC peripheral.
*
* @api
*/
#define rccResetGTZC() /*rccResetAHB1(RCC_AHB1RST_GTZCRST)*/
/** @} */
/**
* @name I2C peripherals specific RCC operations

2
os/hal/ports/STM32/STM32L5xx/stm32_secure.inc
View File

@ -244,6 +244,8 @@
static inline void secure_init(void) {
#if STM32_SECURE_MODE
rccEnableGTZC(false);
FLASH->SECBB1R1 = STM32_FLASH_SECBB1R1;
FLASH->SECBB1R2 = STM32_FLASH_SECBB1R2;
FLASH->SECBB1R3 = STM32_FLASH_SECBB1R3;

5
os/hal/ports/common/ARMCMx/sau.c
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@ -24,6 +24,9 @@
#include "hal.h"
#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) || \
defined(__DOXYGEN__)
/*===========================================================================*/
/* Driver local definitions. */
/*===========================================================================*/
@ -106,4 +109,6 @@ void sauDisableRegion(uint32_t region) {
SAU->RBAR = 0U;
}
#endif /* defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3) */
/** @} */

5
os/hal/ports/common/ARMCMx/sau.h
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@ -25,6 +25,9 @@
#ifndef SAU_H
#define SAU_H
#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) || \
defined(__DOXYGEN__)
/*===========================================================================*/
/* Driver constants. */
/*===========================================================================*/
@ -69,6 +72,8 @@ extern "C" {
}
#endif
#endif /* defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3) */
#endif /* SAU_H */
/** @} */