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git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@12625 110e8d01-0319-4d1e-a829-52ad28d1bb01

This commit is contained in:
Giovanni Di Sirio 2019-02-02 12:32:04 +00:00
parent 84757ac8a2
commit d4e670fc44
3 changed files with 4694 additions and 0 deletions
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505
os/hal/ports/STM32/STM32F4xx/stm32_isr.c Normal file
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/*
ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
/**
* @file STM32F4xx/stm32_isr.c
* @brief STM32F4xx ISR handler code.
*
* @addtogroup STM32F4xx_ISR
* @{
*/
#include "hal.h"
/*===========================================================================*/
/* Driver local definitions. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver exported variables. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver local variables. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver local functions. */
/*===========================================================================*/
#define exti_serve_irq(pr, channel) { \
\
if ((pr) & (1U << (channel))) { \
_pal_isr_code(channel); \
} \
}
/*===========================================================================*/
/* Driver interrupt handlers. */
/*===========================================================================*/
#if (HAL_USE_PAL && (PAL_USE_WAIT || PAL_USE_CALLBACKS)) || defined(__DOXYGEN__)
#if !defined(STM32_DISABLE_EXTI0_HANDLER)
/**
* @brief EXTI[0] interrupt handler.
*
* @isr
*/
OSAL_IRQ_HANDLER(Vector58) {
uint32_t pr;
OSAL_IRQ_PROLOGUE();
pr = EXTI->PR;
pr &= EXTI->IMR & (1U << 0);
EXTI->PR = pr;
exti_serve_irq(pr, 0);
OSAL_IRQ_EPILOGUE();
}
#endif
#if !defined(STM32_DISABLE_EXTI1_HANDLER)
/**
* @brief EXTI[1] interrupt handler.
*
* @isr
*/
OSAL_IRQ_HANDLER(Vector5C) {
uint32_t pr;
OSAL_IRQ_PROLOGUE();
pr = EXTI->PR;
pr &= EXTI->IMR & (1U << 1);
EXTI->PR = pr;
exti_serve_irq(pr, 1);
OSAL_IRQ_EPILOGUE();
}
#endif
#if !defined(STM32_DISABLE_EXTI2_HANDLER)
/**
* @brief EXTI[2] interrupt handler.
*
* @isr
*/
OSAL_IRQ_HANDLER(Vector60) {
uint32_t pr;
OSAL_IRQ_PROLOGUE();
pr = EXTI->PR;
pr &= EXTI->IMR & (1U << 2);
EXTI->PR = pr;
exti_serve_irq(pr, 2);
OSAL_IRQ_EPILOGUE();
}
#endif
#if !defined(STM32_DISABLE_EXTI3_HANDLER)
/**
* @brief EXTI[3] interrupt handler.
*
* @isr
*/
OSAL_IRQ_HANDLER(Vector64) {
uint32_t pr;
OSAL_IRQ_PROLOGUE();
pr = EXTI->PR;
pr &= EXTI->IMR & (1U << 3);
EXTI->PR = pr;
exti_serve_irq(pr, 3);
OSAL_IRQ_EPILOGUE();
}
#endif
#if !defined(STM32_DISABLE_EXTI4_HANDLER)
/**
* @brief EXTI[4] interrupt handler.
*
* @isr
*/
OSAL_IRQ_HANDLER(Vector68) {
uint32_t pr;
OSAL_IRQ_PROLOGUE();
pr = EXTI->PR;
pr &= EXTI->IMR & (1U << 4);
EXTI->PR = pr;
exti_serve_irq(pr, 4);
OSAL_IRQ_EPILOGUE();
}
#endif
#if !defined(STM32_DISABLE_EXTI5_9_HANDLER)
/**
* @brief EXTI[5]...EXTI[9] interrupt handler.
*
* @isr
*/
OSAL_IRQ_HANDLER(Vector9C) {
uint32_t pr;
OSAL_IRQ_PROLOGUE();
pr = EXTI->PR;
pr &= EXTI->IMR & ((1U << 5) | (1U << 6) | (1U << 7) | (1U << 8) |
(1U << 9));
EXTI->PR = pr;
exti_serve_irq(pr, 5);
exti_serve_irq(pr, 6);
exti_serve_irq(pr, 7);
exti_serve_irq(pr, 8);
exti_serve_irq(pr, 9);
OSAL_IRQ_EPILOGUE();
}
#endif
#if !defined(STM32_DISABLE_EXTI10_15_HANDLER)
/**
* @brief EXTI[10]...EXTI[15] interrupt handler.
*
* @isr
*/
OSAL_IRQ_HANDLER(VectorE0) {
uint32_t pr;
OSAL_IRQ_PROLOGUE();
pr = EXTI->PR;
pr &= EXTI->IMR & ((1U << 10) | (1U << 11) | (1U << 12) | (1U << 13) |
(1U << 14) | (1U << 15));
EXTI->PR = pr;
exti_serve_irq(pr, 10);
exti_serve_irq(pr, 11);
exti_serve_irq(pr, 12);
exti_serve_irq(pr, 13);
exti_serve_irq(pr, 14);
exti_serve_irq(pr, 15);
OSAL_IRQ_EPILOGUE();
}
#endif
#endif /* HAL_USE_PAL && (PAL_USE_WAIT || PAL_USE_CALLBACKS) */
#if HAL_USE_GPT || HAL_USE_ICU || HAL_USE_PWM || defined(__DOXYGEN__)
/**
* @brief TIM1-BRK, TIM9 interrupt handler.
*
* @isr
*/
OSAL_IRQ_HANDLER(VectorA0) {
OSAL_IRQ_PROLOGUE();
#if HAL_USE_GPT
#if STM32_GPT_USE_TIM9
gpt_lld_serve_interrupt(&GPTD9);
#endif
#endif
#if HAL_USE_ICU
#if STM32_ICU_USE_TIM9
icu_lld_serve_interrupt(&ICUD9);
#endif
#endif
#if HAL_USE_PWM
#if STM32_PWM_USE_TIM9
pwm_lld_serve_interrupt(&PWMD9);
#endif
#endif
OSAL_IRQ_EPILOGUE();
}
/**
* @brief TIM1-UP, TIM10 interrupt handler.
*
* @isr
*/
OSAL_IRQ_HANDLER(VectorA4) {
OSAL_IRQ_PROLOGUE();
#if HAL_USE_GPT
#if STM32_GPT_USE_TIM1
gpt_lld_serve_interrupt(&GPTD1);
#endif
#if STM32_GPT_USE_TIM10
gpt_lld_serve_interrupt(&GPTD10);
#endif
#endif
#if HAL_USE_ICU
#if STM32_ICU_USE_TIM1
icu_lld_serve_interrupt(&ICUD1);
#endif
#endif
#if HAL_USE_PWM
#if STM32_PWM_USE_TIM1
pwm_lld_serve_interrupt(&PWMD1);
#endif
#if STM32_PWM_USE_TIM10
pwm_lld_serve_interrupt(&PWMD10);
#endif
#endif
OSAL_IRQ_EPILOGUE();
}
/**
* @brief TIM1-TRG-COM, TIM11 interrupt handler.
*
* @isr
*/
OSAL_IRQ_HANDLER(VectorA8) {
OSAL_IRQ_PROLOGUE();
#if HAL_USE_GPT
#if STM32_GPT_USE_TIM11
gpt_lld_serve_interrupt(&GPTD11);
#endif
#endif
#if HAL_USE_ICU
/* Not used by ICU.*/
#endif
#if HAL_USE_PWM
#if STM32_PWM_USE_TIM11
pwm_lld_serve_interrupt(&PWMD11);
#endif
#endif
OSAL_IRQ_EPILOGUE();
}
/**
* @brief TIM1-CC interrupt handler.
*
* @isr
*/
OSAL_IRQ_HANDLER(VectorAC) {
OSAL_IRQ_PROLOGUE();
#if HAL_USE_GPT
/* Not used by GPT.*/
#endif
#if HAL_USE_ICU
#if STM32_ICU_USE_TIM1
icu_lld_serve_interrupt(&ICUD1);
#endif
#endif
#if HAL_USE_PWM
#if STM32_PWM_USE_TIM1
pwm_lld_serve_interrupt(&PWMD1);
#endif
#endif
OSAL_IRQ_EPILOGUE();
}
/**
* @brief TIM8-BRK, TIM12 interrupt handler.
*
* @isr
*/
OSAL_IRQ_HANDLER(VectorEC) {
OSAL_IRQ_PROLOGUE();
#if HAL_USE_GPT
#if STM32_GPT_USE_TIM12
gpt_lld_serve_interrupt(&GPTD12);
#endif
#endif
#if HAL_USE_ICU
#if STM32_ICU_USE_TIM12
icu_lld_serve_interrupt(&ICUD12);
#endif
#endif
#if HAL_USE_PWM
#if STM32_PWM_USE_TIM12
pwm_lld_serve_interrupt(&PWMD12);
#endif
#endif
OSAL_IRQ_EPILOGUE();
}
/**
* @brief TIM8-UP, TIM13 interrupt handler.
*
* @isr
*/
OSAL_IRQ_HANDLER(VectorF0) {
OSAL_IRQ_PROLOGUE();
#if HAL_USE_GPT
#if STM32_GPT_USE_TIM8
gpt_lld_serve_interrupt(&GPTD8);
#endif
#if STM32_GPT_USE_TIM13
gpt_lld_serve_interrupt(&GPTD13);
#endif
#endif
#if HAL_USE_ICU
#if STM32_ICU_USE_TIM8
icu_lld_serve_interrupt(&ICUD8);
#endif
#endif
#if HAL_USE_PWM
#if STM32_PWM_USE_TIM8
pwm_lld_serve_interrupt(&PWMD8);
#endif
#if STM32_PWM_USE_TIM13
pwm_lld_serve_interrupt(&PWMD13);
#endif
#endif
OSAL_IRQ_EPILOGUE();
}
/**
* @brief TIM8-TRG-COM, TIM14 interrupt handler.
*
* @isr
*/
OSAL_IRQ_HANDLER(VectorF4) {
OSAL_IRQ_PROLOGUE();
#if HAL_USE_GPT
#if STM32_GPT_USE_TIM14
gpt_lld_serve_interrupt(&GPTD14);
#endif
#endif
#if HAL_USE_ICU
/* Not used by ICU.*/
#endif
#if HAL_USE_PWM
#if STM32_PWM_USE_TIM14
pwm_lld_serve_interrupt(&PWMD14);
#endif
#endif
OSAL_IRQ_EPILOGUE();
}
/**
* @brief TIM8-CC interrupt handler.
*
* @isr
*/
OSAL_IRQ_HANDLER(VectorF8) {
OSAL_IRQ_PROLOGUE();
#if HAL_USE_GPT
/* Not used by GPT.*/
#endif
#if HAL_USE_ICU
#if STM32_ICU_USE_TIM8
icu_lld_serve_interrupt(&ICUD8);
#endif
#endif
#if HAL_USE_PWM
#if STM32_PWM_USE_TIM8
pwm_lld_serve_interrupt(&PWMD8);
#endif
#endif
OSAL_IRQ_EPILOGUE();
}
#endif /* HAL_USE_GPT || HAL_USE_ICU || HAL_USE_PWM */
/*===========================================================================*/
/* Driver exported functions. */
/*===========================================================================*/
/**
* @brief Enables IRQ sources.
*
* @notapi
*/
void irqInit(void) {
#if HAL_USE_PAL
nvicEnableVector(EXTI0_IRQn, STM32_IRQ_EXTI0_PRIORITY);
nvicEnableVector(EXTI1_IRQn, STM32_IRQ_EXTI1_PRIORITY);
nvicEnableVector(EXTI2_IRQn, STM32_IRQ_EXTI2_PRIORITY);
nvicEnableVector(EXTI3_IRQn, STM32_IRQ_EXTI3_PRIORITY);
nvicEnableVector(EXTI4_IRQn, STM32_IRQ_EXTI4_PRIORITY);
nvicEnableVector(EXTI9_5_IRQn, STM32_IRQ_EXTI5_9_PRIORITY);
nvicEnableVector(EXTI15_10_IRQn, STM32_IRQ_EXTI10_15_PRIORITY);
#endif
#if HAL_USE_GPT || HAL_USE_ICU || HAL_USE_PWM || defined(__DOXYGEN__)
nvicEnableVector(TIM1_BRK_TIM9_IRQn, STM32_IRQ_TIM1_BRK_TIM9_PRIORITY);
nvicEnableVector(TIM1_UP_TIM10_IRQn, STM32_IRQ_TIM1_UP_TIM10_PRIORITY);
nvicEnableVector(TIM1_TRG_COM_TIM11_IRQn, STM32_IRQ_TIM1_TRGCO_TIM11_PRIORITY);
nvicEnableVector(TIM1_CC_IRQn, STM32_IRQ_TIM1_CC_PRIORITY);
nvicEnableVector(TIM8_BRK_TIM12_IRQn, STM32_IRQ_TIM8_BRK_TIM12_PRIORITY);
nvicEnableVector(TIM8_UP_TIM13_IRQn, STM32_IRQ_TIM8_UP_TIM13_PRIORITY);
nvicEnableVector(TIM8_TRG_COM_TIM14_IRQn, STM32_IRQ_TIM8_TRGCO_TIM14_PRIORITY);
nvicEnableVector(TIM8_CC_IRQn, STM32_IRQ_TIM8_CC_PRIORITY);
#endif
}
/**
* @brief Disables IRQ sources.
*
* @notapi
*/
void irqDeinit(void) {
#if HAL_USE_PAL
nvicDisableVector(EXTI0_IRQn);
nvicDisableVector(EXTI1_IRQn);
nvicDisableVector(EXTI2_IRQn);
nvicDisableVector(EXTI3_IRQn);
nvicDisableVector(EXTI4_IRQn);
nvicDisableVector(EXTI9_5_IRQn);
nvicDisableVector(EXTI15_10_IRQn);
#endif
#if HAL_USE_GPT || HAL_USE_ICU || HAL_USE_PWM || defined(__DOXYGEN__)
nvicDisableVector(TIM1_BRK_TIM9_IRQn);
nvicDisableVector(TIM1_UP_TIM10_IRQn);
nvicDisableVector(TIM1_TRG_COM_TIM11_IRQn);
nvicDisableVector(TIM1_CC_IRQn);
nvicDisableVector(TIM8_BRK_TIM12_IRQn);
nvicDisableVector(TIM8_UP_TIM13_IRQn);
nvicDisableVector(TIM8_TRG_COM_TIM14_IRQn);
nvicDisableVector(TIM8_CC_IRQn);
#endif
}
/** @} */

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/*
ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
/**
* @file STM32F4xx/stm32_isr.h
* @brief STM32F4xx ISR handler header.
*
* @addtogroup STM32F4xx_ISR
* @{
*/
#ifndef STM32_ISR_H
#define STM32_ISR_H
/*===========================================================================*/
/* Driver constants. */
/*===========================================================================*/
/**
* @name ISR names and numbers remapping
* @{
*/
#define STM32_TIM1_SUPPRESS_ISR
#define STM32_TIM9_SUPPRESS_ISR
#define STM32_TIM10_SUPPRESS_ISR
#define STM32_TIM11_SUPPRESS_ISR
#define STM32_TIM8_SUPPRESS_ISR
#define STM32_TIM12_SUPPRESS_ISR
#define STM32_TIM13_SUPPRESS_ISR
#define STM32_TIM14_SUPPRESS_ISR
/** @} */
/*===========================================================================*/
/* Driver pre-compile time settings. */
/*===========================================================================*/
/**
* @name Configuration options
* @{
*/
/**
* @brief EXTI0 interrupt priority level setting.
*/
#if !defined(STM32_IRQ_EXTI0_PRIORITY) || defined(__DOXYGEN__)
#define STM32_IRQ_EXTI0_PRIORITY 6
#endif
/**
* @brief EXTI1 interrupt priority level setting.
*/
#if !defined(STM32_IRQ_EXTI1_PRIORITY) || defined(__DOXYGEN__)
#define STM32_IRQ_EXTI1_PRIORITY 6
#endif
/**
* @brief EXTI2 interrupt priority level setting.
*/
#if !defined(STM32_IRQ_EXTI2_PRIORITY) || defined(__DOXYGEN__)
#define STM32_IRQ_EXTI2_PRIORITY 6
#endif
/**
* @brief EXTI3 interrupt priority level setting.
*/
#if !defined(STM32_IRQ_EXTI3_PRIORITY) || defined(__DOXYGEN__)
#define STM32_IRQ_EXTI3_PRIORITY 6
#endif
/**
* @brief EXTI4 interrupt priority level setting.
*/
#if !defined(STM32_IRQ_EXTI4_PRIORITY) || defined(__DOXYGEN__)
#define STM32_IRQ_EXTI4_PRIORITY 6
#endif
/**
* @brief EXTI5..9 interrupt priority level setting.
*/
#if !defined(STM32_IRQ_EXTI5_9_PRIORITY) || defined(__DOXYGEN__)
#define STM32_IRQ_EXTI5_9_PRIORITY 6
#endif
/**
* @brief EXTI10..15 interrupt priority level setting.
*/
#if !defined(STM32_IRQ_EXTI10_15_PRIORITY) || defined(__DOXYGEN__)
#define STM32_IRQ_EXTI10_15_PRIORITY 6
#endif
/**
* @brief EXTI16 interrupt priority level setting.
*/
#if !defined(STM32_IRQ_EXTI16_PRIORITY) || defined(__DOXYGEN__)
#define STM32_IRQ_EXTI16_PRIORITY 6
#endif
/**
* @brief EXTI17 interrupt priority level setting.
*/
#if !defined(STM32_IRQ_EXTI17_PRIORITY) || defined(__DOXYGEN__)
#define STM32_IRQ_EXTI17_PRIORITY 6
#endif
/**
* @brief EXTI18 interrupt priority level setting.
*/
#if !defined(STM32_IRQ_EXTI18_PRIORITY) || defined(__DOXYGEN__)
#define STM32_IRQ_EXTI18_PRIORITY 6
#endif
/**
* @brief EXTI21 interrupt priority level setting.
*/
#if !defined(STM32_IRQ_EXTI21_PRIORITY) || defined(__DOXYGEN__)
#define STM32_IRQ_EXTI21_PRIORITY 6
#endif
/**
* @brief EXTI22 interrupt priority level setting.
*/
#if !defined(STM32_IRQ_EXTI22_PRIORITY) || defined(__DOXYGEN__)
#define STM32_IRQ_EXTI22_PRIORITY 6
#endif
/**
* @brief EXTI23 interrupt priority level setting.
*/
#if !defined(STM32_IRQ_EXTI23_PRIORITY) || defined(__DOXYGEN__)
#define STM32_IRQ_EXTI23_PRIORITY 6
#endif
/** @} */
/*===========================================================================*/
/* Derived constants and error checks. */
/*===========================================================================*/
/* IRQ priority checks.*/
#if !OSAL_IRQ_IS_VALID_PRIORITY(STM32_IRQ_EXTI0_PRIORITY)
#error "Invalid IRQ priority assigned to STM32_IRQ_EXTI0_PRIORITY"
#endif
#if !OSAL_IRQ_IS_VALID_PRIORITY(STM32_IRQ_EXTI1_PRIORITY)
#error "Invalid IRQ priority assigned to STM32_IRQ_EXTI1_PRIORITY"
#endif
#if !OSAL_IRQ_IS_VALID_PRIORITY(STM32_IRQ_EXTI2_PRIORITY)
#error "Invalid IRQ priority assigned to STM32_IRQ_EXTI2_PRIORITY"
#endif
#if !OSAL_IRQ_IS_VALID_PRIORITY(STM32_IRQ_EXTI3_PRIORITY)
#error "Invalid IRQ priority assigned to STM32_IRQ_EXTI3_PRIORITY"
#endif
#if !OSAL_IRQ_IS_VALID_PRIORITY(STM32_IRQ_EXTI4_PRIORITY)
#error "Invalid IRQ priority assigned to STM32_IRQ_EXTI4_PRIORITY"
#endif
#if !OSAL_IRQ_IS_VALID_PRIORITY(STM32_IRQ_EXTI5_9_PRIORITY)
#error "Invalid IRQ priority assigned to STM32_IRQ_EXTI5_9_PRIORITY"
#endif
#if !OSAL_IRQ_IS_VALID_PRIORITY(STM32_IRQ_EXTI10_15_PRIORITY)
#error "Invalid IRQ priority assigned to STM32_IRQ_EXTI10_15_PRIORITY"
#endif
#if !OSAL_IRQ_IS_VALID_PRIORITY(STM32_IRQ_EXTI16_PRIORITY)
#error "Invalid IRQ priority assigned to STM32_IRQ_EXTI16_PRIORITY"
#endif
#if !OSAL_IRQ_IS_VALID_PRIORITY(STM32_IRQ_EXTI17_PRIORITY)
#error "Invalid IRQ priority assigned to STM32_IRQ_EXTI17_PRIORITY"
#endif
#if !OSAL_IRQ_IS_VALID_PRIORITY(STM32_IRQ_EXTI18_PRIORITY)
#error "Invalid IRQ priority assigned to STM32_IRQ_EXTI18_PRIORITY"
#endif
#if !OSAL_IRQ_IS_VALID_PRIORITY(STM32_IRQ_EXTI21_PRIORITY)
#error "Invalid IRQ priority assigned to STM32_IRQ_EXTI21_PRIORITY"
#endif
#if !OSAL_IRQ_IS_VALID_PRIORITY(STM32_IRQ_EXTI22_PRIORITY)
#error "Invalid IRQ priority assigned to STM32_IRQ_EXTI22_PRIORITY"
#endif
#if !OSAL_IRQ_IS_VALID_PRIORITY(STM32_IRQ_EXTI23_PRIORITY)
#error "Invalid IRQ priority assigned to STM32_IRQ_EXTI23_PRIORITY"
#endif
#if !OSAL_IRQ_IS_VALID_PRIORITY(STM32_IRQ_TIM1_BRK_TIM9_PRIORITY)
#error "Invalid IRQ priority assigned to STM32_IRQ_TIM1_BRK_TIM9_PRIORITY"
#endif
#if !OSAL_IRQ_IS_VALID_PRIORITY(STM32_IRQ_TIM1_UP_TIM10_PRIORITY)
#error "Invalid IRQ priority assigned to STM32_IRQ_TIM1_UP_TIM10_PRIORITY"
#endif
#if !OSAL_IRQ_IS_VALID_PRIORITY(STM32_IRQ_TIM1_TRGCO_TIM11_PRIORITY)
#error "Invalid IRQ priority assigned to STM32_IRQ_TIM1_TRGCO_TIM11_PRIORITY"
#endif
#if !OSAL_IRQ_IS_VALID_PRIORITY(STM32_IRQ_TIM1_CC_PRIORITY)
#error "Invalid IRQ priority assigned to STM32_IRQ_TIM1_CC_PRIORITY"
#endif
#if !OSAL_IRQ_IS_VALID_PRIORITY(STM32_IRQ_TIM8_BRK_TIM12_PRIORITY)
#error "Invalid IRQ priority assigned to STM32_IRQ_TIM1_BRK_TIM12_PRIORITY"
#endif
#if !OSAL_IRQ_IS_VALID_PRIORITY(STM32_IRQ_TIM8_UP_TIM13_PRIORITY)
#error "Invalid IRQ priority assigned to STM32_IRQ_TIM1_UP_TIM13_PRIORITY"
#endif
#if !OSAL_IRQ_IS_VALID_PRIORITY(STM32_IRQ_TIM8_TRGCO_TIM14_PRIORITY)
#error "Invalid IRQ priority assigned to STM32_IRQ_TIM1_TRGCO_TIM14_PRIORITY"
#endif
#if !OSAL_IRQ_IS_VALID_PRIORITY(STM32_IRQ_TIM8_CC_PRIORITY)
#error "Invalid IRQ priority assigned to STM32_IRQ_TIM8_CC_PRIORITY"
#endif
/*===========================================================================*/
/* Driver data structures and types. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver macros. */
/*===========================================================================*/
/*===========================================================================*/
/* External declarations. */
/*===========================================================================*/
#ifdef __cplusplus
extern "C" {
#endif
void irqInit(void);
void irqDeinit(void);
#ifdef __cplusplus
}
#endif
#endif /* STM32_ISR_H */
/** @} */

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os/hal/ports/STM32/STM32F4xx/stm32_registry.h Normal file
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