diff --git a/demos/STM32/RT-STM32H563ZI-NUCLEO144/cfg/mcuconf.h b/demos/STM32/RT-STM32H563ZI-NUCLEO144/cfg/mcuconf.h
index fe736a1d3..cbe176087 100644
--- a/demos/STM32/RT-STM32H563ZI-NUCLEO144/cfg/mcuconf.h
+++ b/demos/STM32/RT-STM32H563ZI-NUCLEO144/cfg/mcuconf.h
@@ -37,11 +37,20 @@
 #define STM32H573_MCUCONF
 
 /*
- * HAL driver system settings.
+ * HAL driver general settings.
  */
 #define STM32_NO_INIT                       FALSE
 #define STM32_CLOCK_DYNAMIC                 FALSE
 
+/*
+ * ICache settings.
+ */
+#define STM32_ICACHE_CR                     (ICACHE_CR_EN)
+#define STM32_ICACHE_CRR0                   (0U)
+#define STM32_ICACHE_CRR1                   (0U)
+#define STM32_ICACHE_CRR2                   (0U)
+#define STM32_ICACHE_CRR3                   (0U)
+
 /*
  * PWR settings.
  */
diff --git a/os/hal/ports/STM32/STM32H5xx/hal_lld.c b/os/hal/ports/STM32/STM32H5xx/hal_lld.c
index 18dbc0a78..d2e86a499 100644
--- a/os/hal/ports/STM32/STM32H5xx/hal_lld.c
+++ b/os/hal/ports/STM32/STM32H5xx/hal_lld.c
@@ -772,6 +772,9 @@ void stm32_clock_init(void) {
   }
 #endif
 
+  /* Cache enable.*/
+  icache_init();
+
 #endif /* STM32_NO_INIT */
 }
 #endif /* !defined(HAL_LLD_USE_CLOCK_MANAGEMENT) */
diff --git a/os/hal/ports/STM32/STM32H5xx/hal_lld.h b/os/hal/ports/STM32/STM32H5xx/hal_lld.h
index bf225cdb1..b6f56d5c6 100644
--- a/os/hal/ports/STM32/STM32H5xx/hal_lld.h
+++ b/os/hal/ports/STM32/STM32H5xx/hal_lld.h
@@ -1336,6 +1336,9 @@
 /* Device limits.*/
 #include "stm32_limits.h"
 
+/* ICache handler.*/
+#include "stm32_icache.inc"
+
 /* Clock handlers.*/
 #include "stm32_lsi.inc"
 #include "stm32_csi.inc"
diff --git a/os/hal/ports/STM32/STM32H5xx/platform.mk b/os/hal/ports/STM32/STM32H5xx/platform.mk
index da0ec3233..cfc610529 100644
--- a/os/hal/ports/STM32/STM32H5xx/platform.mk
+++ b/os/hal/ports/STM32/STM32H5xx/platform.mk
@@ -27,6 +27,7 @@ endif
 # Drivers compatible with the platform.
 include $(CHIBIOS)/os/hal/ports/STM32/LLD/EXTIv1/driver.mk
 include $(CHIBIOS)/os/hal/ports/STM32/LLD/GPIOv2/driver.mk
+include $(CHIBIOS)/os/hal/ports/STM32/LLD/ICACHEv1/driver.mk
 include $(CHIBIOS)/os/hal/ports/STM32/LLD/RCCv1/driver.mk
 include $(CHIBIOS)/os/hal/ports/STM32/LLD/SYSTICKv1/driver.mk
 include $(CHIBIOS)/os/hal/ports/STM32/LLD/TIMv1/driver.mk
diff --git a/os/hal/ports/STM32/STM32H5xx/stm32_registry.h b/os/hal/ports/STM32/STM32H5xx/stm32_registry.h
index 2fa88256e..607b550cb 100644
--- a/os/hal/ports/STM32/STM32H5xx/stm32_registry.h
+++ b/os/hal/ports/STM32/STM32H5xx/stm32_registry.h
@@ -38,6 +38,9 @@
 /* Common.                                                                   */
 /*===========================================================================*/
 
+/* Cache attributes.*/
+#define STM32_HAS_ICACHE                    TRUE
+
 /* DAC attributes.*/
 #define STM32_DAC_HAS_MCR                   TRUE
 
diff --git a/tools/ftl/processors/conf/mcuconf_stm32h563xx/mcuconf.h.ftl b/tools/ftl/processors/conf/mcuconf_stm32h563xx/mcuconf.h.ftl
index 5af01af84..d74327aa3 100644
--- a/tools/ftl/processors/conf/mcuconf_stm32h563xx/mcuconf.h.ftl
+++ b/tools/ftl/processors/conf/mcuconf_stm32h563xx/mcuconf.h.ftl
@@ -48,11 +48,20 @@
 #define STM32H573_MCUCONF
 
 /*
- * HAL driver system settings.
+ * HAL driver general settings.
  */
 #define STM32_NO_INIT                       ${doc.STM32_NO_INIT!"FALSE"}
 #define STM32_CLOCK_DYNAMIC                 ${doc.STM32_CLOCK_DYNAMIC!"FALSE"}
 
+/*
+ * ICache settings.
+ */
+#define STM32_ICACHE_CR                     ${doc.STM32_ICACHE_CR!"(ICACHE_CR_EN)"}
+#define STM32_ICACHE_CRR0                   ${doc.STM32_ICACHE_CRR0!"(0U)"}
+#define STM32_ICACHE_CRR1                   ${doc.STM32_ICACHE_CRR1!"(0U)"}
+#define STM32_ICACHE_CRR2                   ${doc.STM32_ICACHE_CRR2!"(0U)"}
+#define STM32_ICACHE_CRR3                   ${doc.STM32_ICACHE_CRR3!"(0U)"}
+
 /*
  * PWR settings.
  */