andreika-git
/
ChibiOS
mirror of https://github.com/andreika-git/ChibiOS.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

Mass update of all drivers to use the new DMA API. What could possibly go wrong? 

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@12521 110e8d01-0319-4d1e-a829-52ad28d1bb01
This commit is contained in:
Giovanni Di Sirio 2019-01-02 11:43:13 +00:00
parent 60c04d66ec
commit d5635adecc
60 changed files with 1693 additions and 2957 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

82
demos/STM32/RT-STM32H743I-NUCLEO144/cfg/mcuconf.h
View File

@ -185,8 +185,8 @@
#define STM32_ADC_COMPACT_SAMPLES FALSE
#define STM32_ADC_USE_ADC12 FALSE
#define STM32_ADC_USE_ADC3 FALSE
#define STM32_ADC_ADC12_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY
#define STM32_ADC_ADC3_BDMA_CHANNEL STM32_BDMA_STREAM_ID_ANY
#define STM32_ADC_ADC12_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_ADC_ADC3_BDMA_STREAM STM32_BDMA_STREAM_ID_ANY
#define STM32_ADC_ADC12_DMA_PRIORITY 2
#define STM32_ADC_ADC3_DMA_PRIORITY 2
#define STM32_ADC_ADC12_IRQ_PRIORITY 5
@ -214,8 +214,8 @@
#define STM32_DAC_DAC1_CH2_IRQ_PRIORITY 10
#define STM32_DAC_DAC1_CH1_DMA_PRIORITY 2
#define STM32_DAC_DAC1_CH2_DMA_PRIORITY 2
#define STM32_DAC_DAC1_CH1_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY
#define STM32_DAC_DAC1_CH2_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY
#define STM32_DAC_DAC1_CH1_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_DAC_DAC1_CH2_DMA_STREAM STM32_DMA_STREAM_ID_ANY
/*
* GPT driver system settings.
@ -253,14 +253,14 @@
#define STM32_I2C_USE_I2C3 FALSE
#define STM32_I2C_USE_I2C4 FALSE
#define STM32_I2C_BUSY_TIMEOUT 50
#define STM32_I2C_I2C1_RX_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY
#define STM32_I2C_I2C1_TX_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY
#define STM32_I2C_I2C2_RX_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY
#define STM32_I2C_I2C2_TX_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY
#define STM32_I2C_I2C3_RX_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY
#define STM32_I2C_I2C3_TX_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY
#define STM32_I2C_I2C4_RX_BDMA_CHANNEL STM32_BDMA_STREAM_ID_ANY
#define STM32_I2C_I2C4_TX_BDMA_CHANNEL STM32_BDMA_STREAM_ID_ANY
#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_I2C_I2C4_RX_BDMA_STREAM STM32_BDMA_STREAM_ID_ANY
#define STM32_I2C_I2C4_TX_BDMA_STREAM STM32_BDMA_STREAM_ID_ANY
#define STM32_I2C_I2C1_IRQ_PRIORITY 5
#define STM32_I2C_I2C2_IRQ_PRIORITY 5
#define STM32_I2C_I2C3_IRQ_PRIORITY 5
@ -335,7 +335,7 @@
#define STM32_SDC_SDMMC_WRITE_TIMEOUT 1000
#define STM32_SDC_SDMMC_READ_TIMEOUT 1000
#define STM32_SDC_SDMMC_CLOCK_DELAY 10
#define STM32_SDC_SDMMC1_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY
#define STM32_SDC_SDMMC1_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_SDC_SDMMC1_DMA_PRIORITY 3
#define STM32_SDC_SDMMC1_IRQ_PRIORITY 9
@ -368,18 +368,18 @@
#define STM32_SPI_USE_SPI4 FALSE
#define STM32_SPI_USE_SPI5 FALSE
#define STM32_SPI_USE_SPI6 FALSE
#define STM32_SPI_SPI1_RX_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY
#define STM32_SPI_SPI1_TX_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY
#define STM32_SPI_SPI2_RX_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY
#define STM32_SPI_SPI2_TX_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY
#define STM32_SPI_SPI3_RX_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY
#define STM32_SPI_SPI3_TX_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY
#define STM32_SPI_SPI4_RX_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY
#define STM32_SPI_SPI4_TX_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY
#define STM32_SPI_SPI5_RX_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY
#define STM32_SPI_SPI5_TX_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY
#define STM32_SPI_SPI6_RX_BDMA_CHANNEL STM32_BDMA_STREAM_ID_ANY
#define STM32_SPI_SPI6_TX_BDMA_CHANNEL STM32_BDMA_STREAM_ID_ANY
#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_SPI_SPI4_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_SPI_SPI4_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_SPI_SPI5_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_SPI_SPI5_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_SPI_SPI6_RX_BDMA_STREAM STM32_BDMA_STREAM_ID_ANY
#define STM32_SPI_SPI6_TX_BDMA_STREAM STM32_BDMA_STREAM_ID_ANY
#define STM32_SPI_SPI1_DMA_PRIORITY 1
#define STM32_SPI_SPI2_DMA_PRIORITY 1
#define STM32_SPI_SPI3_DMA_PRIORITY 1
@ -411,22 +411,22 @@
#define STM32_UART_USE_USART6 FALSE
#define STM32_UART_USE_UART7 FALSE
#define STM32_UART_USE_UART8 FALSE
#define STM32_UART_USART1_RX_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY
#define STM32_UART_USART1_TX_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY
#define STM32_UART_USART2_RX_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY
#define STM32_UART_USART2_TX_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY
#define STM32_UART_USART3_RX_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY
#define STM32_UART_USART3_TX_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY
#define STM32_UART_UART4_RX_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY
#define STM32_UART_UART4_TX_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY
#define STM32_UART_UART5_RX_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY
#define STM32_UART_UART5_TX_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY
#define STM32_UART_USART6_RX_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY
#define STM32_UART_USART6_TX_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY
#define STM32_UART_UART7_RX_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY
#define STM32_UART_UART7_TX_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY
#define STM32_UART_UART8_RX_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY
#define STM32_UART_UART8_TX_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY
#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_UART4_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_UART4_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_UART5_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_UART5_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_UART7_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_UART7_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_UART8_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_UART8_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_USART1_IRQ_PRIORITY 12
#define STM32_UART_USART2_IRQ_PRIORITY 12
#define STM32_UART_USART3_IRQ_PRIORITY 12

54
demos/STM32/RT-STM32L4R5ZI-NUCLEO144/cfg/mcuconf.h
View File

@ -128,7 +128,7 @@
*/
#define STM32_ADC_COMPACT_SAMPLES FALSE
#define STM32_ADC_USE_ADC1 FALSE
#define STM32_ADC_ADC1_DMA_CHANNEL 10
#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_ADC_ADC1_DMA_PRIORITY 2
#define STM32_ADC_ADC12_IRQ_PRIORITY 5
#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 5
@ -150,8 +150,8 @@
#define STM32_DAC_DAC1_CH2_IRQ_PRIORITY 10
#define STM32_DAC_DAC1_CH1_DMA_PRIORITY 2
#define STM32_DAC_DAC1_CH2_DMA_PRIORITY 2
#define STM32_DAC_DAC1_CH1_DMA_CHANNEL 11
#define STM32_DAC_DAC1_CH2_DMA_CHANNEL 12
#define STM32_DAC_DAC1_CH1_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_DAC_DAC1_CH2_DMA_STREAM STM32_DMA_STREAM_ID_ANY
/*
* GPT driver system settings.
@ -180,12 +180,12 @@
#define STM32_I2C_USE_I2C2 FALSE
#define STM32_I2C_USE_I2C3 FALSE
#define STM32_I2C_BUSY_TIMEOUT 50
#define STM32_I2C_I2C1_RX_DMA_CHANNEL 6
#define STM32_I2C_I2C1_TX_DMA_CHANNEL 7
#define STM32_I2C_I2C2_RX_DMA_CHANNEL 8
#define STM32_I2C_I2C2_TX_DMA_CHANNEL 9
#define STM32_I2C_I2C3_RX_DMA_CHANNEL 8
#define STM32_I2C_I2C3_TX_DMA_CHANNEL 9
#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_I2C_I2C1_IRQ_PRIORITY 5
#define STM32_I2C_I2C2_IRQ_PRIORITY 5
#define STM32_I2C_I2C3_IRQ_PRIORITY 5
@ -261,12 +261,12 @@
#define STM32_SPI_USE_SPI1 FALSE
#define STM32_SPI_USE_SPI2 FALSE
#define STM32_SPI_USE_SPI3 FALSE
#define STM32_SPI_SPI1_RX_DMA_CHANNEL 0
#define STM32_SPI_SPI1_TX_DMA_CHANNEL 1
#define STM32_SPI_SPI2_RX_DMA_CHANNEL 2
#define STM32_SPI_SPI2_TX_DMA_CHANNEL 3
#define STM32_SPI_SPI3_RX_DMA_CHANNEL 4
#define STM32_SPI_SPI3_TX_DMA_CHANNEL 5
#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_SPI_SPI1_DMA_PRIORITY 1
#define STM32_SPI_SPI2_DMA_PRIORITY 1
#define STM32_SPI_SPI3_DMA_PRIORITY 1
@ -294,16 +294,16 @@
#define STM32_UART_USE_USART3 FALSE
#define STM32_UART_USE_UART4 FALSE
#define STM32_UART_USE_UART5 FALSE
#define STM32_UART_USART1_RX_DMA_CHANNEL 13
#define STM32_UART_USART1_TX_DMA_CHANNEL 0
#define STM32_UART_USART2_RX_DMA_CHANNEL 1
#define STM32_UART_USART2_TX_DMA_CHANNEL 2
#define STM32_UART_USART3_RX_DMA_CHANNEL 3
#define STM32_UART_USART3_TX_DMA_CHANNEL 4
#define STM32_UART_UART4_RX_DMA_CHANNEL 5
#define STM32_UART_UART4_TX_DMA_CHANNEL 6
#define STM32_UART_UART5_RX_DMA_CHANNEL 7
#define STM32_UART_UART5_TX_DMA_CHANNEL 8
#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_UART4_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_UART4_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_UART5_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_UART5_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_USART1_IRQ_PRIORITY 12
#define STM32_UART_USART2_IRQ_PRIORITY 12
#define STM32_UART_USART3_IRQ_PRIORITY 12
@ -337,8 +337,8 @@
#define STM32_WSPI_OCTOSPI2_PRESCALER_VALUE 1
#define STM32_WSPI_OCTOSPI1_IRQ_PRIORITY 10
#define STM32_WSPI_OCTOSPI2_IRQ_PRIORITY 10
#define STM32_WSPI_OCTOSPI1_DMA_CHANNEL 9
#define STM32_WSPI_OCTOSPI2_DMA_CHANNEL 10
#define STM32_WSPI_OCTOSPI1_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_WSPI_OCTOSPI2_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_WSPI_OCTOSPI1_DMA_PRIORITY 1
#define STM32_WSPI_OCTOSPI2_DMA_PRIORITY 1
#define STM32_WSPI_OCTOSPI1_DMA_IRQ_PRIORITY 10

54
demos/STM32/RT-STM32L4R9-DISCOVERY/cfg/mcuconf.h
View File

@ -128,7 +128,7 @@
*/
#define STM32_ADC_COMPACT_SAMPLES FALSE
#define STM32_ADC_USE_ADC1 FALSE
#define STM32_ADC_ADC1_DMA_CHANNEL 10
#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_ADC_ADC1_DMA_PRIORITY 2
#define STM32_ADC_ADC12_IRQ_PRIORITY 5
#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 5
@ -150,8 +150,8 @@
#define STM32_DAC_DAC1_CH2_IRQ_PRIORITY 10
#define STM32_DAC_DAC1_CH1_DMA_PRIORITY 2
#define STM32_DAC_DAC1_CH2_DMA_PRIORITY 2
#define STM32_DAC_DAC1_CH1_DMA_CHANNEL 11
#define STM32_DAC_DAC1_CH2_DMA_CHANNEL 12
#define STM32_DAC_DAC1_CH1_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_DAC_DAC1_CH2_DMA_STREAM STM32_DMA_STREAM_ID_ANY
/*
* GPT driver system settings.
@ -180,12 +180,12 @@
#define STM32_I2C_USE_I2C2 FALSE
#define STM32_I2C_USE_I2C3 FALSE
#define STM32_I2C_BUSY_TIMEOUT 50
#define STM32_I2C_I2C1_RX_DMA_CHANNEL 6
#define STM32_I2C_I2C1_TX_DMA_CHANNEL 7
#define STM32_I2C_I2C2_RX_DMA_CHANNEL 8
#define STM32_I2C_I2C2_TX_DMA_CHANNEL 9
#define STM32_I2C_I2C3_RX_DMA_CHANNEL 8
#define STM32_I2C_I2C3_TX_DMA_CHANNEL 9
#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_I2C_I2C1_IRQ_PRIORITY 5
#define STM32_I2C_I2C2_IRQ_PRIORITY 5
#define STM32_I2C_I2C3_IRQ_PRIORITY 5
@ -261,12 +261,12 @@
#define STM32_SPI_USE_SPI1 FALSE
#define STM32_SPI_USE_SPI2 FALSE
#define STM32_SPI_USE_SPI3 FALSE
#define STM32_SPI_SPI1_RX_DMA_CHANNEL 0
#define STM32_SPI_SPI1_TX_DMA_CHANNEL 1
#define STM32_SPI_SPI2_RX_DMA_CHANNEL 2
#define STM32_SPI_SPI2_TX_DMA_CHANNEL 3
#define STM32_SPI_SPI3_RX_DMA_CHANNEL 4
#define STM32_SPI_SPI3_TX_DMA_CHANNEL 5
#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_SPI_SPI1_DMA_PRIORITY 1
#define STM32_SPI_SPI2_DMA_PRIORITY 1
#define STM32_SPI_SPI3_DMA_PRIORITY 1
@ -294,16 +294,16 @@
#define STM32_UART_USE_USART3 FALSE
#define STM32_UART_USE_UART4 FALSE
#define STM32_UART_USE_UART5 FALSE
#define STM32_UART_USART1_RX_DMA_CHANNEL 13
#define STM32_UART_USART1_TX_DMA_CHANNEL 0
#define STM32_UART_USART2_RX_DMA_CHANNEL 1
#define STM32_UART_USART2_TX_DMA_CHANNEL 2
#define STM32_UART_USART3_RX_DMA_CHANNEL 3
#define STM32_UART_USART3_TX_DMA_CHANNEL 4
#define STM32_UART_UART4_RX_DMA_CHANNEL 5
#define STM32_UART_UART4_TX_DMA_CHANNEL 6
#define STM32_UART_UART5_RX_DMA_CHANNEL 7
#define STM32_UART_UART5_TX_DMA_CHANNEL 8
#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_UART4_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_UART4_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_UART5_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_UART5_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_USART1_IRQ_PRIORITY 12
#define STM32_UART_USART2_IRQ_PRIORITY 12
#define STM32_UART_USART3_IRQ_PRIORITY 12
@ -337,8 +337,8 @@
#define STM32_WSPI_OCTOSPI2_PRESCALER_VALUE 1
#define STM32_WSPI_OCTOSPI1_IRQ_PRIORITY 10
#define STM32_WSPI_OCTOSPI2_IRQ_PRIORITY 10
#define STM32_WSPI_OCTOSPI1_DMA_CHANNEL 9
#define STM32_WSPI_OCTOSPI2_DMA_CHANNEL 10
#define STM32_WSPI_OCTOSPI1_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_WSPI_OCTOSPI2_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_WSPI_OCTOSPI1_DMA_PRIORITY 1
#define STM32_WSPI_OCTOSPI2_DMA_PRIORITY 1
#define STM32_WSPI_OCTOSPI1_DMA_IRQ_PRIORITY 10

10
os/hal/ports/STM32/LLD/ADCv1/hal_adc_lld.c
View File

@ -137,7 +137,7 @@ void adc_lld_init(void) {
/* Driver initialization.*/
adcObjectInit(&ADCD1);
ADCD1.adc = ADC1;
ADCD1.dmastp = STM32_DMA_STREAM(STM32_ADC_ADC1_DMA_STREAM);
ADCD1.dmastp = NULL;
ADCD1.dmamode = STM32_DMA_CR_CHSEL(ADC1_DMA_CHANNEL) |
STM32_DMA_CR_PL(STM32_ADC_ADC1_DMA_PRIORITY) |
STM32_DMA_CR_DIR_P2M |
@ -183,12 +183,11 @@ void adc_lld_start(ADCDriver *adcp) {
if (adcp->state == ADC_STOP) {
#if STM32_ADC_USE_ADC1
if (&ADCD1 == adcp) {
bool b;
b = dmaStreamAllocate(adcp->dmastp,
adcp->dmastp = dmaStreamAllocI(STM32_ADC_ADC1_DMA_STREAM,
STM32_ADC_ADC1_DMA_IRQ_PRIORITY,
(stm32_dmaisr_t)adc_lld_serve_rx_interrupt,
(void *)adcp);
osalDbgAssert(!b, "stream already allocated");
osalDbgAssert(adcp->dmastp != NULL, "unable to allocate stream");
dmaStreamSetPeripheral(adcp->dmastp, &ADC1->DR);
rccEnableADC1(true);
@ -217,7 +216,8 @@ void adc_lld_stop(ADCDriver *adcp) {
/* If in ready state then disables the ADC clock and analog part.*/
if (adcp->state == ADC_READY) {
dmaStreamRelease(adcp->dmastp);
dmaStreamFreeI(adcp->dmastp);
adcp->dmastp = NULL;
/* Restoring CCR default.*/
#if STM32_ADC_SUPPORTS_PRESCALER

26
os/hal/ports/STM32/LLD/ADCv2/hal_adc_lld.c
View File

@ -195,7 +195,7 @@ void adc_lld_init(void) {
/* Driver initialization.*/
adcObjectInit(&ADCD1);
ADCD1.adc = ADC1;
ADCD1.dmastp = STM32_DMA_STREAM(STM32_ADC_ADC1_DMA_STREAM);
ADCD1.dmastp = NULL;
ADCD1.dmamode = STM32_DMA_CR_CHSEL(ADC1_DMA_CHANNEL) |
STM32_DMA_CR_PL(STM32_ADC_ADC1_DMA_PRIORITY) |
STM32_DMA_CR_DIR_P2M |
@ -208,7 +208,7 @@ void adc_lld_init(void) {
/* Driver initialization.*/
adcObjectInit(&ADCD2);
ADCD2.adc = ADC2;
ADCD2.dmastp = STM32_DMA_STREAM(STM32_ADC_ADC2_DMA_STREAM);
ADCD2.dmastp = NULL;
ADCD2.dmamode = STM32_DMA_CR_CHSEL(ADC2_DMA_CHANNEL) |
STM32_DMA_CR_PL(STM32_ADC_ADC2_DMA_PRIORITY) |
STM32_DMA_CR_DIR_P2M |
@ -221,7 +221,7 @@ void adc_lld_init(void) {
/* Driver initialization.*/
adcObjectInit(&ADCD3);
ADCD3.adc = ADC3;
ADCD3.dmastp = STM32_DMA_STREAM(STM32_ADC_ADC3_DMA_STREAM);
ADCD3.dmastp = NULL;
ADCD3.dmamode = STM32_DMA_CR_CHSEL(ADC3_DMA_CHANNEL) |
STM32_DMA_CR_PL(STM32_ADC_ADC3_DMA_PRIORITY) |
STM32_DMA_CR_DIR_P2M |
@ -248,12 +248,11 @@ void adc_lld_start(ADCDriver *adcp) {
if (adcp->state == ADC_STOP) {
#if STM32_ADC_USE_ADC1
if (&ADCD1 == adcp) {
bool b;
b = dmaStreamAllocate(adcp->dmastp,
adcp->dmastp = dmaStreamAllocI(STM32_ADC_ADC1_DMA_STREAM,
STM32_ADC_ADC1_DMA_IRQ_PRIORITY,
(stm32_dmaisr_t)adc_lld_serve_rx_interrupt,
(void *)adcp);
osalDbgAssert(!b, "stream already allocated");
osalDbgAssert(adcp->dmastp != NULL, "unable to allocate stream");
dmaStreamSetPeripheral(adcp->dmastp, &ADC1->DR);
rccEnableADC1(true);
}
@ -261,12 +260,11 @@ void adc_lld_start(ADCDriver *adcp) {
#if STM32_ADC_USE_ADC2
if (&ADCD2 == adcp) {
bool b;
b = dmaStreamAllocate(adcp->dmastp,
adcp->dmastp = dmaStreamAllocI(STM32_ADC_ADC2_DMA_STREAM,
STM32_ADC_ADC2_DMA_IRQ_PRIORITY,
(stm32_dmaisr_t)adc_lld_serve_rx_interrupt,
(void *)adcp);
osalDbgAssert(!b, "stream already allocated");
osalDbgAssert(adcp->dmastp != NULL, "unable to allocate stream");
dmaStreamSetPeripheral(adcp->dmastp, &ADC2->DR);
rccEnableADC2(true);
}
@ -274,12 +272,11 @@ void adc_lld_start(ADCDriver *adcp) {
#if STM32_ADC_USE_ADC3
if (&ADCD3 == adcp) {
bool b;
b = dmaStreamAllocate(adcp->dmastp,
adcp->dmastp = dmaStreamAllocI(STM32_ADC_ADC3_DMA_STREAM,
STM32_ADC_ADC3_DMA_IRQ_PRIORITY,
(stm32_dmaisr_t)adc_lld_serve_rx_interrupt,
(void *)adcp);
osalDbgAssert(!b, "stream already allocated");
osalDbgAssert(adcp->dmastp != NULL, "unable to allocate stream");
dmaStreamSetPeripheral(adcp->dmastp, &ADC3->DR);
rccEnableADC3(true);
}
@ -309,7 +306,10 @@ void adc_lld_stop(ADCDriver *adcp) {
/* If in ready state then disables the ADC clock.*/
if (adcp->state == ADC_READY) {
dmaStreamRelease(adcp->dmastp);
dmaStreamFreeI(adcp->dmastp);
adcp->dmastp = NULL;
adcp->adc->CR1 = 0;
adcp->adc->CR2 = 0;

31
os/hal/ports/STM32/LLD/ADCv3/hal_adc_lld.c
View File

@ -458,7 +458,7 @@ void adc_lld_init(void) {
ADCD1.adcs = ADC2;
#endif
#if STM32_DMA_SUPPORTS_DMAMUX
ADCD1.dmastp = STM32_DMA_STREAM(STM32_ADC_ADC1_DMA_CHANNEL);
ADCD1.dmastp = NULL;
#else
ADCD1.dmastp = STM32_DMA_STREAM(STM32_ADC_ADC1_DMA_STREAM);
#endif
@ -479,7 +479,7 @@ void adc_lld_init(void) {
#endif
ADCD2.adcm = ADC2;
#if STM32_DMA_SUPPORTS_DMAMUX
ADCD2.dmastp = STM32_DMA_STREAM(STM32_ADC_ADC2_DMA_CHANNEL);
ADCD2.dmastp = NULL;
#else
ADCD2.dmastp = STM32_DMA_STREAM(STM32_ADC_ADC2_DMA_STREAM);
#endif
@ -505,7 +505,7 @@ void adc_lld_init(void) {
ADCD3.adcs = ADC4;
#endif
#if STM32_DMA_SUPPORTS_DMAMUX
ADCD3.dmastp = STM32_DMA_STREAM(STM32_ADC_ADC3_DMA_CHANNEL);
ADCD3.dmastp = NULL;
#else
ADCD3.dmastp = STM32_DMA_STREAM(STM32_ADC_ADC3_DMA_STREAM);
#endif
@ -522,7 +522,7 @@ void adc_lld_init(void) {
ADCD4.adcc = ADC3_4_COMMON;
ADCD4.adcm = ADC4;
#if STM32_DMA_SUPPORTS_DMAMUX
ADCD4.dmastp = STM32_DMA_STREAM(STM32_ADC_ADC4_DMA_CHANNEL);
ADCD4.dmastp = NULL;
#else
ADCD4.dmastp = STM32_DMA_STREAM(STM32_ADC_ADC4_DMA_STREAM);
#endif
@ -605,12 +605,11 @@ void adc_lld_start(ADCDriver *adcp) {
if (adcp->state == ADC_STOP) {
#if STM32_ADC_USE_ADC1
if (&ADCD1 == adcp) {
bool b;
b = dmaStreamAllocate(adcp->dmastp,
adcp->dmastp = dmaStreamAllocI(STM32_ADC_ADC1_DMA_STREAM,
STM32_ADC_ADC1_DMA_IRQ_PRIORITY,
(stm32_dmaisr_t)adc_lld_serve_dma_interrupt,
(void *)adcp);
osalDbgAssert(!b, "stream already allocated");
osalDbgAssert(adcp->dmastp != NULL, "unable to allocate stream");
clkmask |= (1 << 0);
#if defined(STM32F3XX)
@ -627,12 +626,11 @@ void adc_lld_start(ADCDriver *adcp) {
#if STM32_ADC_USE_ADC2
if (&ADCD2 == adcp) {
bool b;
b = dmaStreamAllocate(adcp->dmastp,
adcp->dmastp = dmaStreamAllocI(STM32_ADC_ADC2_DMA_STREAM,
STM32_ADC_ADC2_DMA_IRQ_PRIORITY,
(stm32_dmaisr_t)adc_lld_serve_dma_interrupt,
(void *)adcp);
osalDbgAssert(!b, "stream already allocated");
osalDbgAssert(adcp->dmastp != NULL, "unable to allocate stream");
clkmask |= (1 << 1);
#if defined(STM32F3XX)
@ -649,12 +647,11 @@ void adc_lld_start(ADCDriver *adcp) {
#if STM32_ADC_USE_ADC3
if (&ADCD3 == adcp) {
bool b;
b = dmaStreamAllocate(adcp->dmastp,
adcp->dmastp = dmaStreamAllocI(STM32_ADC_ADC3_DMA_STREAM,
STM32_ADC_ADC3_DMA_IRQ_PRIORITY,
(stm32_dmaisr_t)adc_lld_serve_dma_interrupt,
(void *)adcp);
osalDbgAssert(!b, "stream already allocated");
osalDbgAssert(adcp->dmastp != NULL, "unable to allocate stream");
clkmask |= (1 << 2);
#if defined(STM32F3XX)
@ -671,12 +668,11 @@ void adc_lld_start(ADCDriver *adcp) {
#if STM32_ADC_USE_ADC4
if (&ADCD4 == adcp) {
bool b;
b = dmaStreamAllocate(adcp->dmastp,
adcp->dmastp = dmaStreamAllocI(STM32_ADC_ADC4_DMA_STREAM,
STM32_ADC_ADC4_DMA_IRQ_PRIORITY,
(stm32_dmaisr_t)adc_lld_serve_dma_interrupt,
(void *)adcp);
osalDbgAssert(!b, "stream already allocated");
osalDbgAssert(adcp->dmastp != NULL, "unable to allocate stream");
clkmask |= (1 << 3);
#if defined(STM32F3XX)
@ -728,7 +724,8 @@ void adc_lld_stop(ADCDriver *adcp) {
if (adcp->state == ADC_READY) {
/* Releasing the associated DMA channel.*/
dmaStreamRelease(adcp->dmastp);
dmaStreamFreeI(adcp->dmastp);
adcp->dmastp = NULL;
/* Stopping the ongoing conversion, if any.*/
adc_lld_stop_adc(adcp);

24
os/hal/ports/STM32/LLD/ADCv3/hal_adc_lld.h
View File

@ -492,26 +492,6 @@
#endif
/* Check on the presence of the DMA streams settings in mcuconf.h.*/
#if STM32_DMA_SUPPORTS_DMAMUX
#if STM32_ADC_USE_ADC1 && !defined(STM32_ADC_ADC1_DMA_CHANNEL)
#error "ADC1 DMA channel not defined"
#endif
#if STM32_ADC_USE_ADC2 && !defined(STM32_ADC_ADC2_DMA_CHANNEL)
#error "ADC2 DMA channel not defined"
#endif
#if STM32_ADC_USE_ADC3 && !defined(STM32_ADC_ADC3_DMA_CHANNEL)
#error "ADC3 DMA channel not defined"
#endif
#if STM32_ADC_USE_ADC4 && !defined(STM32_ADC_ADC4_DMA_CHANNEL)
#error "ADC4 DMA channel not defined"
#endif
#else /* !STM32_DMA_SUPPORTS_DMAMUX */
#if STM32_ADC_USE_ADC1 && !defined(STM32_ADC_ADC1_DMA_STREAM)
#error "ADC1 DMA stream not defined"
#endif
@ -528,6 +508,10 @@
#error "ADC4 DMA stream not defined"
#endif
#if STM32_DMA_SUPPORTS_DMAMUX
#else /* !STM32_DMA_SUPPORTS_DMAMUX */
/* Check on the validity of the assigned DMA channels.*/
#if STM32_ADC_USE_ADC1 && \
!STM32_DMA_IS_VALID_ID(STM32_ADC_ADC1_DMA_STREAM, STM32_ADC1_DMA_MSK)

8
os/hal/ports/STM32/LLD/ADCv4/hal_adc_lld.c
View File

@ -410,7 +410,7 @@ void adc_lld_start(ADCDriver *adcp) {
if (adcp->state == ADC_STOP) {
#if STM32_ADC_USE_ADC12 == TRUE
if (&ADCD1 == adcp) {
adcp->data.dma = dmaStreamAllocI(STM32_ADC_ADC12_DMA_CHANNEL,
adcp->data.dma = dmaStreamAllocI(STM32_ADC_ADC12_DMA_STREAM,
STM32_ADC_ADC12_IRQ_PRIORITY,
(stm32_dmaisr_t)adc_lld_serve_dma_interrupt,
(void *)adcp);
@ -422,7 +422,7 @@ void adc_lld_start(ADCDriver *adcp) {
#if STM32_ADC_USE_ADC3 == TRUE
if (&ADCD3 == adcp) {
adcp->data.bdma = bdmaStreamAllocI(STM32_ADC_ADC3_BDMA_CHANNEL,
adcp->data.bdma = bdmaStreamAllocI(STM32_ADC_ADC3_BDMA_STREAM,
STM32_ADC_ADC3_IRQ_PRIORITY,
(stm32_dmaisr_t)adc_lld_serve_bdma_interrupt,
(void *)adcp);
@ -479,7 +479,7 @@ void adc_lld_stop(ADCDriver *adcp) {
if (&ADCD1 == adcp) {
/* Releasing the associated DMA channel.*/
dmaStreamRelease(adcp->data.dma);
dmaStreamFreeI(adcp->data.dma);
adcp->data.dma = NULL;
/* Resetting CCR options except default ones.*/
@ -492,7 +492,7 @@ void adc_lld_stop(ADCDriver *adcp) {
if (&ADCD3 == adcp) {
/* Releasing the associated BDMA channel.*/
bdmaStreamRelease(adcp->data.bdma);
bdmaStreamFreeI(adcp->data.bdma);
adcp->data.bdma = NULL;
/* Resetting CCR options except default ones.*/

27
os/hal/ports/STM32/LLD/ADCv4/hal_adc_lld.h
View File

@ -192,20 +192,6 @@
#define STM32_ADC_USE_ADC3 FALSE
#endif
/**
* @brief ADC1/ADC2 DMA channel.
*/
#if !defined(STM32_ADC_ADC12_DMA_CHANNEL) || defined(__DOXYGEN__)
#define STM32_ADC_ADC12_DMA_CHANNEL 0
#endif
/**
* @brief ADC3 DMA channel.
*/
#if !defined(STM32_ADC_ADC3_BDMA_CHANNEL) || defined(__DOXYGEN__)
#define STM32_ADC_ADC3_BDMA_CHANNEL 1
#endif
/**
* @brief ADC1/ADC2 DMA priority (0..3|lowest..highest).
*/
@ -313,14 +299,23 @@
#error "ADC driver activated but no ADC peripheral assigned"
#endif
/* Check on the presence of the DMA streams settings in mcuconf.h.*/
#if STM32_ADC_USE_ADC12 && !defined(STM32_ADC_ADC12_DMA_STREAM)
#error "STM32_ADC_ADC12_DMA_STREAM not defined"
#endif
#if STM32_ADC_USE_ADC3 && !defined(STM32_ADC_ADC3_BDMA_STREAM)
#error "STM32_ADC_ADC3_BDMA_STREAM not defined"
#endif
/* DMA channel range tests.*/
#if STM32_ADC_USE_ADC12 && \
!STM32_DMA_IS_VALID_CHANNEL(STM32_ADC_ADC12_DMA_CHANNEL)
!STM32_DMA_IS_VALID_STREAM(STM32_ADC_ADC12_DMA_STREAM)
#error "Invalid DMA channel assigned to ADC12"
#endif
#if STM32_ADC_USE_ADC3 && \
!STM32_BDMA_IS_VALID_CHANNEL(STM32_ADC_ADC3_BDMA_CHANNEL)
!STM32_BDMA_IS_VALID_STREAM(STM32_ADC_ADC3_BDMA_STREAM)
#error "Invalid DMA channel assigned to ADC3"
#endif

60
os/hal/ports/STM32/LLD/BDMAv1/stm32_bdma.c
View File

@ -279,13 +279,6 @@ void bdmaInit(void) {
* @details The stream is allocated and, if required, the BDMA clock enabled.
* The function also enables the IRQ vector associated to the stream
* and initializes its priority.
* @pre The stream must not be already in use or an error is returned.
* @post The stream is allocated and the default ISR handler redirected
* to the specified function.
* @post The stream ISR vector is enabled and its priority configured.
* @post The stream must be freed using @p dmaStreamRelease() before it can
* be reused with another peripheral.
* @post The stream is in its post-reset state.
*
* @param[in] id numeric identifiers of a specific stream or:
* - @p STM32_BDMA_STREAM_ID_ANY for any stream.
@ -363,31 +356,30 @@ const stm32_bdma_stream_t *bdmaStreamAllocI(uint32_t id,
* @details The stream is allocated and, if required, the BDMA clock enabled.
* The function also enables the IRQ vector associated to the stream
* and initializes its priority.
* @pre The stream must not be already in use or an error is returned.
* @post The stream is allocated and the default ISR handler redirected
* to the specified function.
* @post The stream ISR vector is enabled and its priority configured.
* @post The stream must be freed using @p bdmaStreamRelease() before it can
* be reused with another peripheral.
* @post The stream is in its post-reset state.
* @note This function can be invoked in both ISR or thread context.
*
* @param[in] stp pointer to an @p stm32_bdma_stream_t structure
* @param[in] id numeric identifiers of a specific stream or:
* - @p STM32_BDMA_STREAM_ID_ANY for any stream.
* .
* @param[in] priority IRQ priority for the BDMA stream
* @param[in] func handling function pointer, can be @p NULL
* @param[in] param a parameter to be passed to the handling function
* @return The operation status.
* @retval false no error, stream taken.
* @retval true error, stream already taken.
* @return Pointer to the allocated @p stm32_bdma_stream_t
* structure.
* @retval NULL if a/the stream is not available.
*
* @special
* @api
*/
bool bdmaStreamAllocate(const stm32_bdma_stream_t *stp,
const stm32_bdma_stream_t *bdmaStreamAlloc(uint32_t id,
uint32_t priority,
stm32_bdmaisr_t func,
void *param) {
const stm32_bdma_stream_t *stp;
return bdmaStreamAllocI(stp->selfindex, priority, func, param) == NULL;
osalSysLock();
stp = bdmaStreamAllocI(id, priority, func, param);
osalSysUnlock();
return stp;
}
/**
@ -395,15 +387,12 @@ bool bdmaStreamAllocate(const stm32_bdma_stream_t *stp,
* @details The stream is freed and, if required, the BDMA clock disabled.
* Trying to release a unallocated stream is an illegal operation
* and is trapped if assertions are enabled.
* @pre The stream must have been allocated using @p bdmaStreamAllocate().
* @post The stream is again available.
* @note This function can be invoked in both ISR or thread context.
*
* @param[in] stp pointer to an @p stm32_bdma_stream_t structure
*
* @special
* @iclass
*/
void bdmaStreamRelease(const stm32_bdma_stream_t *stp) {
void bdmaStreamFreeI(const stm32_bdma_stream_t *stp) {
osalDbgCheck(stp != NULL);
@ -427,6 +416,23 @@ void bdmaStreamRelease(const stm32_bdma_stream_t *stp) {
}
}
/**
* @brief Releases a BDMA stream.
* @details The stream is freed and, if required, the BDMA clock disabled.
* Trying to release a unallocated stream is an illegal operation
* and is trapped if assertions are enabled.
*
* @param[in] stp pointer to an @p stm32_bdma_stream_t structure
*
* @api
*/
void bdmaStreamFree(const stm32_bdma_stream_t *stp) {
osalSysLock();
bdmaStreamFreeI(stp);
osalSysUnlock();
}
/**
* @brief Associates a peripheral request to a BDMA stream.
* @note This function can be invoked in both ISR or thread context.

17
os/hal/ports/STM32/LLD/BDMAv1/stm32_bdma.h
View File

@ -53,15 +53,15 @@
#define STM32_BDMA_IS_VALID_PRIORITY(prio) (((prio) >= 0U) && ((prio) <= 3U))
/**
* @brief Checks if a BDMA channel is within the valid range.
* @brief Checks if a BDMA stream id is within the valid range.
*
* @param[in] ch BDMA channel
* @param[in] id BDMA stream id
* @retval The check result.
* @retval FALSE invalid DMA channel.
* @retval TRUE correct DMA channel.
* @retval false invalid DMA stream.
* @retval true correct DMA stream.
*/
#define STM32_BDMA_IS_VALID_CHANNEL(ch) (((ch) >= 0U) && \
((ch) <= STM32_BDMA_STREAMS))
#define STM32_BDMA_IS_VALID_STREAM(id) (((id) >= 0U) && \
((id) <= STM32_BDMA_STREAMS))
/**
* @name Special stream identifiers
@ -421,11 +421,12 @@ extern "C" {
uint32_t priority,
stm32_bdmaisr_t func,
void *param);
bool bdmaStreamAllocate(const stm32_bdma_stream_t *stp,
const stm32_bdma_stream_t *bdmaStreamAlloc(uint32_t id,
uint32_t priority,
stm32_bdmaisr_t func,
void *param);
void bdmaStreamRelease(const stm32_bdma_stream_t *stp);
void bdmaStreamFreeI(const stm32_bdma_stream_t *stp);
void bdmaStreamFree(const stm32_bdma_stream_t *stp);
void bdmaSetRequestSource(const stm32_bdma_stream_t *stp, uint32_t per);
#ifdef __cplusplus
}

14
os/hal/ports/STM32/LLD/CRYPv1/hal_crypto_lld.c
View File

@ -157,11 +157,7 @@ void cry_lld_init(void) {
#if STM32_CRY_USE_HASH1
#if STM32_CRY_HASH_SIZE_THRESHOLD != 0
CRYD1.hash_tr = NULL;
#if STM32_DMA_SUPPORTS_DMAMUX
CRYD1.dma_hash = STM32_DMA_STREAM(STM32_CRY_HASH1_DMA_CHANNEL);
#else
CRYD1.dma_hash = STM32_DMA_STREAM(STM32_CRY_HASH1_DMA_STREAM);
#endif
CRYD1.dma_hash = NULL;
#endif /* STM32_CRY_HASH_SIZE_THRESHOLD != 0 */
#endif /* STM32_CRY_USE_HASH1 */
@ -187,12 +183,11 @@ void cry_lld_start(CRYDriver *cryp) {
#if STM32_CRY_USE_HASH1
#if STM32_CRY_HASH_SIZE_THRESHOLD != 0
bool b;
b = dmaStreamAllocate(cryp->dma_hash,
cryp->dma_hash = dmaStreamAllocI(STM32_CRY_HASH1_DMA_STREAM,
STM32_CRY_HASH1_IRQ_PRIORITY,
(stm32_dmaisr_t)cry_lld_serve_hash_interrupt,
(void *)cryp);
osalDbgAssert(!b, "stream already allocated");
osalDbgAssert(cryp->dma_hash != NULL, "unable to allocate stream");
/* Preparing the DMA channel.*/
dmaStreamSetMode(cryp->dma_hash,
@ -241,7 +236,8 @@ void cry_lld_stop(CRYDriver *cryp) {
#if STM32_CRY_USE_HASH1
#if STM32_CRY_HASH_SIZE_THRESHOLD != 0
dmaStreamRelease(cryp->dma_hash);
dmaStreamFreeI(cryp->dma_hash);
cryp->dma_hash = NULL;
#endif
rccDisableHASH();
#endif

38
os/hal/ports/STM32/LLD/CRYPv1/hal_crypto_lld.h
View File

@ -138,37 +138,29 @@
#error "Invalid IRQ priority assigned to CRYP1"
#endif
/* Devices with DMAMUX require a different kind of check.*/
#if STM32_DMA_SUPPORTS_DMAMUX
#if STM32_CRY_USE_HASH1
#if !defined(STM32_CRY_HASH1_DMA_CHANNEL)
#error "HASH1 DMA channel not defined"
#endif
#if !STM32_DMA_IS_VALID_CHANNEL(STM32_CRY_HASH1_DMA_CHANNEL)
#error "Invalid DMA channel assigned to HASH1"
#endif
#if !STM32_DMA_IS_VALID_PRIORITY(STM32_CRY_HASH1_DMA_PRIORITY)
#error "Invalid DMA priority assigned to HASH1"
#endif
#endif /* !STM32_CRY_USE_HASH1 */
#else /* !STM32_DMA_SUPPORTS_DMAMUX */
/* Sanity checks on DMA streams settings in mcuconf.h.*/
#if STM32_CRY_USE_HASH1
/* Check on the presence of the DMA streams settings in mcuconf.h.*/
#if !defined(STM32_CRY_HASH1_DMA_STREAM)
#error "HASH1 DMA streams not defined"
#endif
#if !STM32_DMA_IS_VALID_ID(STM32_CRY_HASH1_DMA_STREAM, STM32_HASH1_DMA_MSK)
/* Sanity checks on DMA streams settings in mcuconf.h.*/
#if STM32_CRY_USE_HASH1 && \
!STM32_DMA_IS_VALID_STREAM(STM32_CRY_HASH1_DMA_STREAM)
#error "Invalid DMA stream assigned to HASH1"
#endif
/* Devices without DMAMUX require an additional check.*/
#if !STM32_DMA_SUPPORTS_DMAMUX
#if STM32_CRY_USE_HASH1 && \
!STM32_DMA_IS_VALID_ID(STM32_CRY_HASH1_DMA_STREAM, STM32_HASH1_DMA_MSK)
#error "invalid DMA stream associated to HASH1"
#endif
#endif /* !STM32_DMA_SUPPORTS_DMAMUX */
/* DMA priority check.*/
#if !STM32_DMA_IS_VALID_PRIORITY(STM32_CRY_HASH1_DMA_PRIORITY)
#error "Invalid DMA priority assigned to HASH1"
#endif
#endif /* !STM32_CRY_USE_HASH1 */
#endif /* !STM32_DMA_SUPPORTS_DMAMUX */
#if !defined(STM32_DMA_REQUIRED)
#define STM32_DMA_REQUIRED

20
os/hal/ports/STM32/LLD/DACv1/hal_dac_lld.c
View File

@ -87,11 +87,9 @@ static const dacparams_t dma1_ch1_params = {
.dataoffset = 0U,
.regshift = 0U,
.regmask = 0xFFFF0000U,
.dmastream = STM32_DAC_DAC1_CH1_DMA_STREAM,
#if STM32_DMA_SUPPORTS_DMAMUX
.dmachannel = STM32_DAC_DAC1_CH1_DMA_CHANNEL,
.peripheral = STM32_DMAMUX1_DAC1_CH1,
#else
.dmachannel = STM32_DAC_DAC1_CH1_DMA_STREAM,
#endif
.dmamode = STM32_DMA_CR_CHSEL(DAC1_CH1_DMA_CHANNEL) |
STM32_DMA_CR_PL(STM32_DAC_DAC1_CH1_DMA_PRIORITY) |
@ -108,11 +106,9 @@ static const dacparams_t dma1_ch2_params = {
.dataoffset = CHANNEL_DATA_OFFSET,
.regshift = 16U,
.regmask = 0x0000FFFFU,
.dmastream = STM32_DAC_DAC1_CH2_DMA_STREAM,
#if STM32_DMA_SUPPORTS_DMAMUX
.dmachannel = STM32_DAC_DAC1_CH2_DMA_CHANNEL,
.peripheral = STM32_DMAMUX1_DAC1_CH2,
#else
.dmachannel = STM32_DAC_DAC1_CH2_DMA_STREAM,
#endif
.dmamode = STM32_DMA_CR_CHSEL(DAC1_CH2_DMA_CHANNEL) |
STM32_DMA_CR_PL(STM32_DAC_DAC1_CH2_DMA_PRIORITY) |
@ -129,11 +125,9 @@ static const dacparams_t dma2_ch1_params = {
.dataoffset = 0U,
.regshift = 0U,
.regmask = 0xFFFF0000U,
.dmastream = STM32_DAC_DAC2_CH1_DMA_STREAM,
#if STM32_DMA_SUPPORTS_DMAMUX
.dmachannel = STM32_DAC_DAC2_CH1_DMA_CHANNEL,
.peripheral = STM32_DMAMUX1_DAC2_CH1,
#else
.dmachannel = STM32_DAC_DAC2_CH1_DMA_STREAM,
#endif
.dmamode = STM32_DMA_CR_CHSEL(DAC2_CH1_DMA_CHANNEL) |
STM32_DMA_CR_PL(STM32_DAC_DAC2_CH1_DMA_PRIORITY) |
@ -150,11 +144,9 @@ static const dacparams_t dma1_ch2_params = {
.dataoffset = CHANNEL_DATA_OFFSET,
.regshift = 16U,
.regmask = 0x0000FFFFU,
.dmastream = STM32_DAC_DAC2_CH2_DMA_STREAM,
#if STM32_DMA_SUPPORTS_DMAMUX
.dmachannel = STM32_DAC_DAC2_CH2_DMA_CHANNEL,
.peripheral = STM32_DMAMUX1_DAC2_CH2,
#else
.dmachannel = STM32_DAC_DAC2_CH2_DMA_STREAM,
#endif
.dmamode = STM32_DMA_CR_CHSEL(DAC2_CH2_DMA_CHANNEL) |
STM32_DMA_CR_PL(STM32_DAC_DAC2_CH2_DMA_PRIORITY) |
@ -437,7 +429,7 @@ void dac_lld_start_conversion(DACDriver *dacp) {
n = dacp->depth * dacp->grpp->num_channels;
/* Allocating the DMA channel.*/
dacp->dma = dmaStreamAllocI(dacp->params->dmachannel,
dacp->dma = dmaStreamAllocI(dacp->params->dmastream,
dacp->params->dmairqprio,
(stm32_dmaisr_t)dac_lld_serve_tx_interrupt,
(void *)dacp);
@ -542,7 +534,7 @@ void dac_lld_stop_conversion(DACDriver *dacp) {
/* DMA channel disabled and released.*/
dmaStreamDisable(dacp->dma);
dmaStreamRelease(dacp->dma);
dmaStreamFreeI(dacp->dma);
dacp->dma = NULL;
#if STM32_DAC_DUAL_MODE == FALSE

31
os/hal/ports/STM32/LLD/DACv1/hal_dac_lld.h
View File

@ -201,27 +201,6 @@
reassign streams to different channels.*/
#if STM32_ADVANCED_DMA
#if STM32_DMA_SUPPORTS_DMAMUX
/* Check on the presence of the DMA channel settings in mcuconf.h.*/
#if STM32_DAC_USE_DAC1_CH1 && !defined(STM32_DAC_DAC1_CH1_DMA_CHANNEL)
#error "DAC1 CH1 DMA channel not defined"
#endif
#if STM32_DAC_USE_DAC1_CH2 && !defined(STM32_DAC_DAC1_CH2_DMA_CHANNEL)
#error "DAC1 CH2 DMA channel not defined"
#endif
#if STM32_DAC_USE_DAC2_CH1 && !defined(STM32_DAC_DAC2_CH1_DMA_CHANNEL)
#error "DAC2 CH1 DMA channel not defined"
#endif
#if STM32_DAC_USE_DAC2_CH2 && !defined(STM32_DAC_DAC2_CH2_DMA_CHANNEL)
#error "DAC2 CH2 DMA channel not defined"
#endif
#else /* !STM32_DMA_SUPPORTS_DMAMUX */
/* Check on the presence of the DMA streams settings in mcuconf.h.*/
#if STM32_DAC_USE_DAC1_CH1 && !defined(STM32_DAC_DAC1_CH1_DMA_STREAM)
#error "DAC1 CH1 DMA stream not defined"
@ -239,7 +218,11 @@
#error "DAC2 CH2 DMA stream not defined"
#endif
/* Check on the validity of the assigned DMA channels.*/
#if STM32_DMA_SUPPORTS_DMAMUX
#else /* !STM32_DMA_SUPPORTS_DMAMUX */
/* Check on the validity of the assigned DMA streams.*/
#if STM32_DAC_USE_DAC1_CH1 && \
!STM32_DMA_IS_VALID_ID(STM32_DAC_DAC1_CH1_DMA_STREAM, STM32_DAC1_CH1_DMA_MSK)
#error "invalid DMA stream associated to DAC1 CH1"
@ -332,9 +315,9 @@ typedef struct {
*/
uint32_t regmask;
/**
* @brief Associated DMA channel.
* @brief Associated DMA stream.
*/
uint32_t dmachannel;
uint32_t dmastream;
/**
* @brief Mode bits for the DMA.
*/

65
os/hal/ports/STM32/LLD/DMAv1/stm32_dma.c
View File

@ -504,13 +504,6 @@ void dmaInit(void) {
* @details The stream is allocated and, if required, the DMA clock enabled.
* The function also enables the IRQ vector associated to the stream
* and initializes its priority.
* @pre The stream must not be already in use or an error is returned.
* @post The stream is allocated and the default ISR handler redirected
* to the specified function.
* @post The stream ISR vector is enabled and its priority configured.
* @post The stream must be freed using @p dmaStreamRelease() before it can
* be reused with another peripheral.
* @post The stream is in its post-reset state.
*
* @param[in] id numeric identifiers of a specific stream or:
* - @p STM32_DMA_STREAM_ID_ANY for any stream.
@ -612,32 +605,34 @@ const stm32_dma_stream_t *dmaStreamAllocI(uint32_t id,
* @details The stream is allocated and, if required, the DMA clock enabled.
* The function also enables the IRQ vector associated to the stream
* and initializes its priority.
* @pre The stream must not be already in use or an error is returned.
* @post The stream is allocated and the default ISR handler redirected
* to the specified function.
* @post The stream ISR vector is enabled and its priority configured.
* @post The stream must be freed using @p dmaStreamRelease() before it can
* be reused with another peripheral.
* @post The stream is in its post-reset state.
* @note This function can be invoked in both ISR or thread context.
*
* @param[in] dmastp pointer to a stm32_dma_stream_t structure
* @param[in] id numeric identifiers of a specific stream or:
* - @p STM32_DMA_STREAM_ID_ANY for any stream.
* - @p STM32_DMA_STREAM_ID_ANY_DMA1 for any stream
* on DMA1.
* - @p STM32_DMA_STREAM_ID_ANY_DMA2 for any stream
* on DMA2.
* .
* @param[in] priority IRQ priority for the DMA stream
* @param[in] func handling function pointer, can be @p NULL
* @param[in] param a parameter to be passed to the handling function
* @return The operation status.
* @retval false no error, stream taken.
* @retval true error, stream already taken.
* @return Pointer to the allocated @p stm32_dma_stream_t
* structure.
* @retval NULL if a/the stream is not available.
*
* @iclass
* @deprecated
* @api
*/
bool dmaStreamAllocate(const stm32_dma_stream_t *dmastp,
const stm32_dma_stream_t *dmaStreamAlloc(uint32_t id,
uint32_t priority,
stm32_dmaisr_t func,
void *param) {
const stm32_dma_stream_t *dmastp;
return dmaStreamAllocI(dmastp->selfindex, priority, func, param) == NULL;
osalSysLock();
dmastp = dmaStreamAllocI(id, priority, func, param);
osalSysUnlock();
return dmastp;
}
/**
@ -645,15 +640,12 @@ bool dmaStreamAllocate(const stm32_dma_stream_t *dmastp,
* @details The stream is freed and, if required, the DMA clock disabled.
* Trying to release a unallocated stream is an illegal operation
* and is trapped if assertions are enabled.
* @pre The stream must have been allocated using @p dmaStreamAllocate().
* @post The stream is again available.
* @note This function can be invoked in both ISR or thread context.
*
* @param[in] dmastp pointer to a stm32_dma_stream_t structure
*
* @special
* @iclass
*/
void dmaStreamRelease(const stm32_dma_stream_t *dmastp) {
void dmaStreamFreeI(const stm32_dma_stream_t *dmastp) {
osalDbgCheck(dmastp != NULL);
@ -692,6 +684,23 @@ void dmaStreamRelease(const stm32_dma_stream_t *dmastp) {
#endif
}
/**
* @brief Releases a DMA stream.
* @details The stream is freed and, if required, the DMA clock disabled.
* Trying to release a unallocated stream is an illegal operation
* and is trapped if assertions are enabled.
*
* @param[in] dmastp pointer to a stm32_dma_stream_t structure
*
* @api
*/
void dmaStreamFree(const stm32_dma_stream_t *dmastp) {
osalSysLock();
dmaStreamFreeI(dmastp);
osalSysUnlock();
}
/**
* @brief Serves a DMA IRQ.
*

25
os/hal/ports/STM32/LLD/DMAv1/stm32_dma.h
View File

@ -79,22 +79,22 @@
#if (STM32_DMA_SUPPORTS_DMAMUX == FALSE) || defined(_DOXYGEN__)
/**
* @brief Checks if a DMA channel is within the valid range.
* @brief Checks if a DMA stream id is within the valid range.
*
* @param[in] ch DMA channel
* @param[in] id DMA stream id
* @retval The check result.
* @retval FALSE invalid DMA channel.
* @retval TRUE correct DMA channel.
* @retval false invalid DMA channel.
* @retval true correct DMA channel.
*/
#define STM32_DMA_IS_VALID_CHANNEL(ch) (((ch) >= 0U) && \
((ch) < STM32_DMA_STREAMS))
#define STM32_DMA_IS_VALID_STREAM(id) (((id) >= 0U) && \
((id) < STM32_DMA_STREAMS))
#else /* STM32_DMA_SUPPORTS_DMAMUX == FALSE */
#if STM32_DMA2_NUM_CHANNELS > 0
#define STM32_DMA_IS_VALID_CHANNEL(ch) (((ch) >= 0U) && \
((ch) <= (STM32_DMA_STREAMS + 2)))
#define STM32_DMA_IS_VALID_STREAM(id) (((id) >= 0U) && \
((id) <= (STM32_DMA_STREAMS + 2)))
#else
#define STM32_DMA_IS_VALID_CHANNEL(ch) (((ch) >= 0U) && \
((ch) <= (STM32_DMA_STREAMS + 1)))
#define STM32_DMA_IS_VALID_STREAM(id) (((id) >= 0U) && \
((id) <= (STM32_DMA_STREAMS + 1)))
#endif
#endif /* STM32_DMA_SUPPORTS_DMAMUX == FALSE */
@ -500,11 +500,12 @@ extern "C" {
uint32_t priority,
stm32_dmaisr_t func,
void *param);
bool dmaStreamAllocate(const stm32_dma_stream_t *dmastp,
const stm32_dma_stream_t *dmaStreamAlloc(uint32_t id,
uint32_t priority,
stm32_dmaisr_t func,
void *param);
void dmaStreamRelease(const stm32_dma_stream_t *dmastp);
void dmaStreamFreeI(const stm32_dma_stream_t *dmastp);
void dmaStreamFree(const stm32_dma_stream_t *dmastp);
void dmaServeInterrupt(const stm32_dma_stream_t *dmastp);
#if STM32_DMA_SUPPORTS_DMAMUX == TRUE
void dmaSetRequestSource(const stm32_dma_stream_t *dmastp, uint32_t per);

65
os/hal/ports/STM32/LLD/DMAv2/stm32_dma.c
View File

@ -471,13 +471,6 @@ void dmaInit(void) {
* @details The stream is allocated and, if required, the DMA clock enabled.
* The function also enables the IRQ vector associated to the stream
* and initializes its priority.
* @pre The stream must not be already in use or an error is returned.
* @post The stream is allocated and the default ISR handler redirected
* to the specified function.
* @post The stream ISR vector is enabled and its priority configured.
* @post The stream must be freed using @p dmaStreamRelease() before it can
* be reused with another peripheral.
* @post The stream is in its post-reset state.
*
* @param[in] id numeric identifiers of a specific stream or:
* - @p STM32_DMA_STREAM_ID_ANY for any stream.
@ -572,32 +565,34 @@ const stm32_dma_stream_t *dmaStreamAllocI(uint32_t id,
* @details The stream is allocated and, if required, the DMA clock enabled.
* The function also enables the IRQ vector associated to the stream
* and initializes its priority.
* @pre The stream must not be already in use or an error is returned.
* @post The stream is allocated and the default ISR handler redirected
* to the specified function.
* @post The stream ISR vector is enabled and its priority configured.
* @post The stream must be freed using @p dmaStreamRelease() before it can
* be reused with another peripheral.
* @post The stream is in its post-reset state.
* @note This function can be invoked in both ISR or thread context.
*
* @param[in] dmastp pointer to a stm32_dma_stream_t structure
* @param[in] id numeric identifiers of a specific stream or:
* - @p STM32_DMA_STREAM_ID_ANY for any stream.
* - @p STM32_DMA_STREAM_ID_ANY_DMA1 for any stream
* on DMA1.
* - @p STM32_DMA_STREAM_ID_ANY_DMA2 for any stream
* on DMA2.
* .
* @param[in] priority IRQ priority for the DMA stream
* @param[in] func handling function pointer, can be @p NULL
* @param[in] param a parameter to be passed to the handling function
* @return The operation status.
* @retval false no error, stream taken.
* @retval true error, stream already taken.
* @return Pointer to the allocated @p stm32_dma_stream_t
* structure.
* @retval NULL if a/the stream is not available.
*
* @special
* @deprecated
* @api
*/
bool dmaStreamAllocate(const stm32_dma_stream_t *dmastp,
const stm32_dma_stream_t *dmaStreamAlloc(uint32_t id,
uint32_t priority,
stm32_dmaisr_t func,
void *param) {
const stm32_dma_stream_t *dmastp;
return dmaStreamAllocI(dmastp->selfindex, priority, func, param) == NULL;
osalSysLock();
dmastp = dmaStreamAllocI(id, priority, func, param);
osalSysUnlock();
return dmastp;
}
/**
@ -605,15 +600,12 @@ bool dmaStreamAllocate(const stm32_dma_stream_t *dmastp,
* @details The stream is freed and, if required, the DMA clock disabled.
* Trying to release a unallocated stream is an illegal operation
* and is trapped if assertions are enabled.
* @pre The stream must have been allocated using @p dmaStreamAllocate().
* @post The stream is again available.
* @note This function can be invoked in both ISR or thread context.
*
* @param[in] dmastp pointer to a stm32_dma_stream_t structure
*
* @special
* @iclass
*/
void dmaStreamRelease(const stm32_dma_stream_t *dmastp) {
void dmaStreamFreeI(const stm32_dma_stream_t *dmastp) {
osalDbgCheck(dmastp != NULL);
@ -643,6 +635,23 @@ void dmaStreamRelease(const stm32_dma_stream_t *dmastp) {
#endif
}
/**
* @brief Releases a DMA stream.
* @details The stream is freed and, if required, the DMA clock disabled.
* Trying to release a unallocated stream is an illegal operation
* and is trapped if assertions are enabled.
*
* @param[in] dmastp pointer to a stm32_dma_stream_t structure
*
* @api
*/
void dmaStreamFree(const stm32_dma_stream_t *dmastp) {
osalSysLock();
dmaStreamFreeI(dmastp);
osalSysUnlock();
}
#if (STM32_DMA_SUPPORTS_DMAMUX == TRUE) || defined(__DOXYGEN__)
/**
* @brief Associates a peripheral request to a DMA stream.

33
os/hal/ports/STM32/LLD/DMAv2/stm32_dma.h
View File

@ -62,29 +62,29 @@
* @param[in] prio DMA priority
*
* @retval The check result.
* @retval FALSE invalid DMA priority.
* @retval TRUE correct DMA priority.
* @retval false invalid DMA priority.
* @retval true correct DMA priority.
*/
#define STM32_DMA_IS_VALID_PRIORITY(prio) (((prio) >= 0U) && ((prio) <= 3U))
#if (STM32_DMA_SUPPORTS_DMAMUX == FALSE) || defined(_DOXYGEN__)
/**
* @brief Checks if a DMA channel is within the valid range.
* @brief Checks if a DMA stream id is within the valid range.
*
* @param[in] ch DMA channel
* @param[in] id DMA stream id
* @retval The check result.
* @retval FALSE invalid DMA channel.
* @retval TRUE correct DMA channel.
* @retval false invalid DMA stream.
* @retval true correct DMA stream.
*/
#define STM32_DMA_IS_VALID_CHANNEL(ch) (((ch) >= 0U) && \
((ch) <= STM32_DMA_STREAMS))
#define STM32_DMA_IS_VALID_STREAM(id) (((id) >= 0U) && \
((id) <= STM32_DMA_STREAMS))
#else /* STM32_DMA_SUPPORTS_DMAMUX == FALSE */
#if STM32_HAS_DMA2 == TRUE
#define STM32_DMA_IS_VALID_CHANNEL(ch) (((ch) >= 0U) && \
((ch) <= (STM32_DMA_STREAMS + 2)))
#define STM32_DMA_IS_VALID_STREAM(id) (((id) >= 0U) && \
((id) <= (STM32_DMA_STREAMS + 2)))
#else
#define STM32_DMA_IS_VALID_CHANNEL(ch) (((ch) >= 0U) && \
((ch) <= (STM32_DMA_STREAMS + 1)))
#define STM32_DMA_IS_VALID_STREAM(id) (((id) >= 0U) && \
((id) <= (STM32_DMA_STREAMS + 1)))
#endif
#endif /* STM32_DMA_SUPPORTS_DMAMUX == FALSE */
@ -114,8 +114,8 @@
* @param[in] mask the stream numeric identifiers mask
*
* @retval The check result.
* @retval FALSE id does not belong to the mask.
* @retval TRUE id belongs to the mask.
* @retval false id does not belong to the mask.
* @retval true id belongs to the mask.
*/
#define STM32_DMA_IS_VALID_ID(id, mask) (((1U << (id)) & (mask)))
@ -664,11 +664,12 @@ extern "C" {
uint32_t priority,
stm32_dmaisr_t func,
void *param);
bool dmaStreamAllocate(const stm32_dma_stream_t *dmastp,
const stm32_dma_stream_t *dmaStreamAlloc(uint32_t id,
uint32_t priority,
stm32_dmaisr_t func,
void *param);
void dmaStreamRelease(const stm32_dma_stream_t *dmastp);
void dmaStreamFreeI(const stm32_dma_stream_t *dmastp);
void dmaStreamFree(const stm32_dma_stream_t *dmastp);
#if STM32_DMA_SUPPORTS_DMAMUX == TRUE
void dmaSetRequestSource(const stm32_dma_stream_t *dmastp, uint32_t per);
#endif

54
os/hal/ports/STM32/LLD/I2Cv1/hal_i2c_lld.c
View File

@ -506,24 +506,24 @@ void i2c_lld_init(void) {
i2cObjectInit(&I2CD1);
I2CD1.thread = NULL;
I2CD1.i2c = I2C1;
I2CD1.dmarx = STM32_DMA_STREAM(STM32_I2C_I2C1_RX_DMA_STREAM);
I2CD1.dmatx = STM32_DMA_STREAM(STM32_I2C_I2C1_TX_DMA_STREAM);
I2CD1.dmarx = NULL;
I2CD1.dmatx = NULL;
#endif /* STM32_I2C_USE_I2C1 */
#if STM32_I2C_USE_I2C2
i2cObjectInit(&I2CD2);
I2CD2.thread = NULL;
I2CD2.i2c = I2C2;
I2CD2.dmarx = STM32_DMA_STREAM(STM32_I2C_I2C2_RX_DMA_STREAM);
I2CD2.dmatx = STM32_DMA_STREAM(STM32_I2C_I2C2_TX_DMA_STREAM);
I2CD2.dmarx = NULL;
I2CD2.dmatx = NULL;
#endif /* STM32_I2C_USE_I2C2 */
#if STM32_I2C_USE_I2C3
i2cObjectInit(&I2CD3);
I2CD3.thread = NULL;
I2CD3.i2c = I2C3;
I2CD3.dmarx = STM32_DMA_STREAM(STM32_I2C_I2C3_RX_DMA_STREAM);
I2CD3.dmatx = STM32_DMA_STREAM(STM32_I2C_I2C3_TX_DMA_STREAM);
I2CD3.dmarx = NULL;
I2CD3.dmatx = NULL;
#endif /* STM32_I2C_USE_I2C3 */
}
@ -551,19 +551,19 @@ void i2c_lld_start(I2CDriver *i2cp) {
#if STM32_I2C_USE_I2C1
if (&I2CD1 == i2cp) {
bool b;
rccResetI2C1();
b = dmaStreamAllocate(i2cp->dmarx,
i2cp->dmarx = dmaStreamAllocI(STM32_I2C_I2C1_RX_DMA_STREAM,
STM32_I2C_I2C1_IRQ_PRIORITY,
(stm32_dmaisr_t)i2c_lld_serve_rx_end_irq,
(void *)i2cp);
osalDbgAssert(!b, "stream already allocated");
b = dmaStreamAllocate(i2cp->dmatx,
osalDbgAssert(i2cp->dmarx != NULL, "unable to allocate stream");
i2cp->dmatx = dmaStreamAllocI(STM32_I2C_I2C1_TX_DMA_STREAM,
STM32_I2C_I2C1_IRQ_PRIORITY,
(stm32_dmaisr_t)i2c_lld_serve_tx_end_irq,
(void *)i2cp);
osalDbgAssert(!b, "stream already allocated");
osalDbgAssert(i2cp->dmatx != NULL, "unable to allocate stream");
rccEnableI2C1(true);
nvicEnableVector(I2C1_EV_IRQn, STM32_I2C_I2C1_IRQ_PRIORITY);
nvicEnableVector(I2C1_ER_IRQn, STM32_I2C_I2C1_IRQ_PRIORITY);
@ -577,19 +577,19 @@ void i2c_lld_start(I2CDriver *i2cp) {
#if STM32_I2C_USE_I2C2
if (&I2CD2 == i2cp) {
bool b;
rccResetI2C2();
b = dmaStreamAllocate(i2cp->dmarx,
i2cp->dmarx = dmaStreamAllocI(STM32_I2C_I2C2_RX_DMA_STREAM,
STM32_I2C_I2C2_IRQ_PRIORITY,
(stm32_dmaisr_t)i2c_lld_serve_rx_end_irq,
(void *)i2cp);
osalDbgAssert(!b, "stream already allocated");
b = dmaStreamAllocate(i2cp->dmatx,
osalDbgAssert(i2cp->dmarx != NULL, "unable to allocate stream");
i2cp->dmatx = dmaStreamAllocI(STM32_I2C_I2C2_TX_DMA_STREAM,
STM32_I2C_I2C2_IRQ_PRIORITY,
(stm32_dmaisr_t)i2c_lld_serve_tx_end_irq,
(void *)i2cp);
osalDbgAssert(!b, "stream already allocated");
osalDbgAssert(i2cp->dmatx != NULL, "unable to allocate stream");
rccEnableI2C2(true);
nvicEnableVector(I2C2_EV_IRQn, STM32_I2C_I2C2_IRQ_PRIORITY);
nvicEnableVector(I2C2_ER_IRQn, STM32_I2C_I2C2_IRQ_PRIORITY);
@ -603,19 +603,19 @@ void i2c_lld_start(I2CDriver *i2cp) {
#if STM32_I2C_USE_I2C3
if (&I2CD3 == i2cp) {
bool b;
rccResetI2C3();
b = dmaStreamAllocate(i2cp->dmarx,
i2cp->dmarx = dmaStreamAllocI(STM32_I2C_I2C3_RX_DMA_STREAM,
STM32_I2C_I2C3_IRQ_PRIORITY,
(stm32_dmaisr_t)i2c_lld_serve_rx_end_irq,
(void *)i2cp);
osalDbgAssert(!b, "stream already allocated");
b = dmaStreamAllocate(i2cp->dmatx,
osalDbgAssert(i2cp->dmarx != NULL, "unable to allocate stream");
i2cp->dmatx = dmaStreamAllocI(STM32_I2C_I2C3_TX_DMA_STREAM,
STM32_I2C_I2C3_IRQ_PRIORITY,
(stm32_dmaisr_t)i2c_lld_serve_tx_end_irq,
(void *)i2cp);
osalDbgAssert(!b, "stream already allocated");
osalDbgAssert(i2cp->dmatx != NULL, "unable to allocate stream");
rccEnableI2C3(true);
nvicEnableVector(I2C3_EV_IRQn, STM32_I2C_I2C3_IRQ_PRIORITY);
nvicEnableVector(I2C3_ER_IRQn, STM32_I2C_I2C3_IRQ_PRIORITY);
@ -659,8 +659,10 @@ void i2c_lld_stop(I2CDriver *i2cp) {
/* I2C disable.*/
i2c_lld_abort_operation(i2cp);
dmaStreamRelease(i2cp->dmatx);
dmaStreamRelease(i2cp->dmarx);
dmaStreamFreeI(i2cp->dmatx);
dmaStreamFreeI(i2cp->dmarx);
i2cp->dmatx = NULL;
i2cp->dmarx = NULL;
#if STM32_I2C_USE_I2C1
if (&I2CD1 == i2cp) {

62
os/hal/ports/STM32/LLD/I2Cv2/hal_i2c_lld.c
View File

@ -626,8 +626,8 @@ void i2c_lld_init(void) {
I2CD1.thread = NULL;
I2CD1.i2c = I2C1;
#if STM32_I2C_USE_DMA == TRUE
I2CD1.dmarx = STM32_DMA_STREAM(STM32_I2C_I2C1_RX_DMA_STREAM);
I2CD1.dmatx = STM32_DMA_STREAM(STM32_I2C_I2C1_TX_DMA_STREAM);
I2CD1.dmarx = NULL;
I2CD1.dmatx = NULL;
#endif
#endif /* STM32_I2C_USE_I2C1 */
@ -636,8 +636,8 @@ void i2c_lld_init(void) {
I2CD2.thread = NULL;
I2CD2.i2c = I2C2;
#if STM32_I2C_USE_DMA == TRUE
I2CD2.dmarx = STM32_DMA_STREAM(STM32_I2C_I2C2_RX_DMA_STREAM);
I2CD2.dmatx = STM32_DMA_STREAM(STM32_I2C_I2C2_TX_DMA_STREAM);
I2CD2.dmarx = NULL;
I2CD2.dmatx = NULL;
#endif
#endif /* STM32_I2C_USE_I2C2 */
@ -646,8 +646,8 @@ void i2c_lld_init(void) {
I2CD3.thread = NULL;
I2CD3.i2c = I2C3;
#if STM32_I2C_USE_DMA == TRUE
I2CD3.dmarx = STM32_DMA_STREAM(STM32_I2C_I2C3_RX_DMA_STREAM);
I2CD3.dmatx = STM32_DMA_STREAM(STM32_I2C_I2C3_TX_DMA_STREAM);
I2CD3.dmarx = NULL;
I2CD3.dmatx = NULL;
#endif
#endif /* STM32_I2C_USE_I2C3 */
@ -656,8 +656,8 @@ void i2c_lld_init(void) {
I2CD4.thread = NULL;
I2CD4.i2c = I2C4;
#if STM32_I2C_USE_DMA == TRUE
I2CD4.dmarx = STM32_DMA_STREAM(STM32_I2C_I2C4_RX_DMA_STREAM);
I2CD4.dmatx = STM32_DMA_STREAM(STM32_I2C_I2C4_TX_DMA_STREAM);
I2CD4.dmarx = NULL;
I2CD4.dmatx = NULL;
#endif
#endif /* STM32_I2C_USE_I2C4 */
}
@ -691,18 +691,16 @@ void i2c_lld_start(I2CDriver *i2cp) {
rccEnableI2C1(true);
#if STM32_I2C_USE_DMA == TRUE
{
bool b;
b = dmaStreamAllocate(i2cp->dmarx,
i2cp->dmarx = dmaStreamAllocI(STM32_I2C_I2C1_RX_DMA_STREAM,
STM32_I2C_I2C1_IRQ_PRIORITY,
NULL,
(void *)i2cp);
osalDbgAssert(!b, "stream already allocated");
b = dmaStreamAllocate(i2cp->dmatx,
osalDbgAssert(i2cp->dmarx != NULL, "unable to allocate stream");
i2cp->dmatx = dmaStreamAllocI(STM32_I2C_I2C1_TX_DMA_STREAM,
STM32_I2C_I2C1_IRQ_PRIORITY,
NULL,
(void *)i2cp);
osalDbgAssert(!b, "stream already allocated");
osalDbgAssert(i2cp->dmatx != NULL, "unable to allocate stream");
i2cp->rxdmamode |= STM32_DMA_CR_CHSEL(I2C1_RX_DMA_CHANNEL) |
STM32_DMA_CR_PL(STM32_I2C_I2C1_DMA_PRIORITY);
@ -729,18 +727,16 @@ void i2c_lld_start(I2CDriver *i2cp) {
rccEnableI2C2(true);
#if STM32_I2C_USE_DMA == TRUE
{
bool b;
b = dmaStreamAllocate(i2cp->dmarx,
i2cp->dmarx = dmaStreamAllocI(STM32_I2C_I2C2_RX_DMA_STREAM,
STM32_I2C_I2C2_IRQ_PRIORITY,
NULL,
(void *)i2cp);
osalDbgAssert(!b, "stream already allocated");
b = dmaStreamAllocate(i2cp->dmatx,
osalDbgAssert(i2cp->dmarx != NULL, "unable to allocate stream");
i2cp->dmatx = dmaStreamAllocI(STM32_I2C_I2C2_TX_DMA_STREAM,
STM32_I2C_I2C2_IRQ_PRIORITY,
NULL,
(void *)i2cp);
osalDbgAssert(!b, "stream already allocated");
osalDbgAssert(i2cp->dmatx != NULL, "unable to allocate stream");
i2cp->rxdmamode |= STM32_DMA_CR_CHSEL(I2C2_RX_DMA_CHANNEL) |
STM32_DMA_CR_PL(STM32_I2C_I2C2_DMA_PRIORITY);
@ -767,18 +763,16 @@ void i2c_lld_start(I2CDriver *i2cp) {
rccEnableI2C3(true);
#if STM32_I2C_USE_DMA == TRUE
{
bool b;
b = dmaStreamAllocate(i2cp->dmarx,
i2cp->dmarx = dmaStreamAllocI(STM32_I2C_I2C3_RX_DMA_STREAM,
STM32_I2C_I2C3_IRQ_PRIORITY,
NULL,
(void *)i2cp);
osalDbgAssert(!b, "stream already allocated");
b = dmaStreamAllocate(i2cp->dmatx,
osalDbgAssert(i2cp->dmarx != NULL, "unable to allocate stream");
i2cp->dmatx = dmaStreamAllocI(STM32_I2C_I2C3_TX_DMA_STREAM,
STM32_I2C_I2C3_IRQ_PRIORITY,
NULL,
(void *)i2cp);
osalDbgAssert(!b, "stream already allocated");
osalDbgAssert(i2cp->dmatx != NULL, "unable to allocate stream");
i2cp->rxdmamode |= STM32_DMA_CR_CHSEL(I2C3_RX_DMA_CHANNEL) |
STM32_DMA_CR_PL(STM32_I2C_I2C3_DMA_PRIORITY);
@ -805,18 +799,16 @@ void i2c_lld_start(I2CDriver *i2cp) {
rccEnableI2C4(true);
#if STM32_I2C_USE_DMA == TRUE
{
bool b;
b = dmaStreamAllocate(i2cp->dmarx,
i2cp->dmarx = dmaStreamAllocI(STM32_I2C_I2C4_RX_DMA_STREAM,
STM32_I2C_I2C4_IRQ_PRIORITY,
NULL,
(void *)i2cp);
osalDbgAssert(!b, "stream already allocated");
b = dmaStreamAllocate(i2cp->dmatx,
osalDbgAssert(i2cp->dmarx != NULL, "unable to allocate stream");
i2cp->dmatx = dmaStreamAllocI(STM32_I2C_I2C4_TX_DMA_STREAM,
STM32_I2C_I2C4_IRQ_PRIORITY,
NULL,
(void *)i2cp);
osalDbgAssert(!b, "stream already allocated");
osalDbgAssert(i2cp->dmatx != NULL, "unable to allocate stream");
i2cp->rxdmamode |= STM32_DMA_CR_CHSEL(I2C4_RX_DMA_CHANNEL) |
STM32_DMA_CR_PL(STM32_I2C_I2C4_DMA_PRIORITY);
@ -872,8 +864,10 @@ void i2c_lld_stop(I2CDriver *i2cp) {
/* I2C disable.*/
i2c_lld_abort_operation(i2cp);
#if STM32_I2C_USE_DMA == TRUE
dmaStreamRelease(i2cp->dmatx);
dmaStreamRelease(i2cp->dmarx);
dmaStreamFreeI(i2cp->dmatx);
dmaStreamFreeI(i2cp->dmarx);
i2cp->dmatx = NULL;
i2cp->dmarx = NULL;
#endif
#if STM32_I2C_USE_I2C1

16
os/hal/ports/STM32/LLD/I2Cv3/hal_i2c_lld.c
View File

@ -823,12 +823,12 @@ void i2c_lld_start(I2CDriver *i2cp) {
rccEnableI2C1(true);
#if STM32_I2C_USE_DMA == TRUE
{
i2cp->rx.dma = dmaStreamAllocI(STM32_I2C_I2C1_RX_DMA_CHANNEL,
i2cp->rx.dma = dmaStreamAllocI(STM32_I2C_I2C1_RX_DMA_STREAM,
STM32_I2C_I2C1_IRQ_PRIORITY,
NULL,
NULL);
osalDbgAssert(i2cp->rx.dma != NULL, "unable to allocate stream");
i2cp->tx.dma = dmaStreamAllocI(STM32_I2C_I2C1_TX_DMA_CHANNEL,
i2cp->tx.dma = dmaStreamAllocI(STM32_I2C_I2C1_TX_DMA_STREAM,
STM32_I2C_I2C1_IRQ_PRIORITY,
NULL,
NULL);
@ -850,12 +850,12 @@ void i2c_lld_start(I2CDriver *i2cp) {
rccEnableI2C2(true);
#if STM32_I2C_USE_DMA == TRUE
{
i2cp->rx.dma = dmaStreamAllocI(STM32_I2C_I2C2_RX_DMA_CHANNEL,
i2cp->rx.dma = dmaStreamAllocI(STM32_I2C_I2C2_RX_DMA_STREAM,
STM32_I2C_I2C2_IRQ_PRIORITY,
NULL,
NULL);
osalDbgAssert(i2cp->rx.dma != NULL, "unable to allocate stream");
i2cp->tx.dma = dmaStreamAllocI(STM32_I2C_I2C2_TX_DMA_CHANNEL,
i2cp->tx.dma = dmaStreamAllocI(STM32_I2C_I2C2_TX_DMA_STREAM,
STM32_I2C_I2C2_IRQ_PRIORITY,
NULL,
NULL);
@ -877,12 +877,12 @@ void i2c_lld_start(I2CDriver *i2cp) {
rccEnableI2C3(true);
#if STM32_I2C_USE_DMA == TRUE
{
i2cp->rx.dma = dmaStreamAllocI(STM32_I2C_I2C3_RX_DMA_CHANNEL,
i2cp->rx.dma = dmaStreamAllocI(STM32_I2C_I2C3_RX_DMA_STREAM,
STM32_I2C_I2C3_IRQ_PRIORITY,
NULL,
NULL);
osalDbgAssert(i2cp->rx.dma != NULL, "unable to allocate stream");
i2cp->tx.dma = dmaStreamAllocI(STM32_I2C_I2C3_TX_DMA_CHANNEL,
i2cp->tx.dma = dmaStreamAllocI(STM32_I2C_I2C3_TX_DMA_STREAM,
STM32_I2C_I2C3_IRQ_PRIORITY,
NULL,
NULL);
@ -904,12 +904,12 @@ void i2c_lld_start(I2CDriver *i2cp) {
rccEnableI2C4(true);
#if STM32_I2C_USE_DMA == TRUE
{
i2cp->rx.bdma = bdmaStreamAllocI(STM32_I2C_I2C4_RX_BDMA_CHANNEL,
i2cp->rx.bdma = bdmaStreamAllocI(STM32_I2C_I2C4_RX_BDMA_STREAM,
STM32_I2C_I2C4_IRQ_PRIORITY,
NULL,
NULL);
osalDbgAssert(i2cp->rx.bdma != NULL, "unable to allocate stream");
i2cp->tx.bdma = bdmaStreamAllocI(STM32_I2C_I2C4_TX_BDMA_CHANNEL,
i2cp->tx.bdma = bdmaStreamAllocI(STM32_I2C_I2C4_TX_BDMA_STREAM,
STM32_I2C_I2C4_IRQ_PRIORITY,
NULL,
NULL);

120
os/hal/ports/STM32/LLD/I2Cv3/hal_i2c_lld.h
View File

@ -137,62 +137,6 @@
#define STM32_I2C_USE_DMA TRUE
#endif
/**
* @brief I2C1 RX DMA channel setting.
*/
#if !defined(STM32_I2C_I2C1_RX_DMA_CHANNEL) || defined(__DOXYGEN__)
#define STM32_I2C_I2C1_RX_DMA_CHANNEL 6
#endif
/**
* @brief I2C1 TX DMA channel setting.
*/
#if !defined(STM32_I2C_I2C1_TX_DMA_CHANNEL) || defined(__DOXYGEN__)
#define STM32_I2C_I2C1_TX_DMA_CHANNEL 7
#endif
/**
* @brief I2C2 RX DMA channel setting.
*/
#if !defined(STM32_I2C_I2C2_RX_DMA_CHANNEL) || defined(__DOXYGEN__)
#define STM32_I2C_I2C2_RX_DMA_CHANNEL 8
#endif
/**
* @brief I2C2 TX DMA channel setting.
*/
#if !defined(STM32_I2C_I2C2_TX_DMA_CHANNEL) || defined(__DOXYGEN__)
#define STM32_I2C_I2C2_TX_DMA_CHANNEL 9
#endif
/**
* @brief I2C3 RX DMA channel setting.
*/
#if !defined(STM32_I2C_I2C3_RX_DMA_CHANNEL) || defined(__DOXYGEN__)
#define STM32_I2C_I2C3_RX_DMA_CHANNEL 8
#endif
/**
* @brief I2C3 TX DMA channel setting.
*/
#if !defined(STM32_I2C_I2C3_TX_DMA_CHANNEL) || defined(__DOXYGEN__)
#define STM32_I2C_I2C3_TX_DMA_CHANNEL 9
#endif
/**
* @brief I2C4 RX DMA channel setting.
*/
#if !defined(STM32_I2C_I2C4_RX_BDMA_CHANNEL) || defined(__DOXYGEN__)
#define STM32_I2C_I2C4_RX_BDMA_CHANNEL 0
#endif
/**
* @brief I2C4 TX DMA channel setting.
*/
#if !defined(STM32_I2C_I2C4_TX_BDMA_CHANNEL) || defined(__DOXYGEN__)
#define STM32_I2C_I2C4_TX_BDMA_CHANNEL 1
#endif
/**
* @brief I2C1 DMA priority (0..3|lowest..highest).
* @note The priority level is used for both the TX and RX DMA streams but
@ -292,12 +236,20 @@
#if STM32_I2C_USE_DMA == TRUE
#if STM32_I2C_USE_I2C1
#if !STM32_DMA_IS_VALID_CHANNEL(STM32_I2C_I2C1_RX_DMA_CHANNEL)
#error "Invalid DMA channel assigned to I2C1 RX"
#if !defined(STM32_I2C_I2C1_RX_DMA_STREAM)
#error "STM32_I2C_I2C1_RX_DMA_STREAM not defined"
#endif
#if !STM32_DMA_IS_VALID_CHANNEL(STM32_I2C_I2C1_TX_DMA_CHANNEL)
#error "Invalid DMA channel assigned to I2C1 TX"
#if !defined(STM32_I2C_I2C1_TX_DMA_STREAM)
#error "STM32_I2C_I2C1_TX_DMA_STREAM not defined"
#endif
#if !STM32_DMA_IS_VALID_STREAM(STM32_I2C_I2C1_RX_DMA_STREAM)
#error "Invalid DMA stream assigned to I2C1 RX"
#endif
#if !STM32_DMA_IS_VALID_STREAM(STM32_I2C_I2C1_TX_DMA_STREAM)
#error "Invalid DMA stream assigned to I2C1 TX"
#endif
#if !STM32_DMA_IS_VALID_PRIORITY(STM32_I2C_I2C1_DMA_PRIORITY)
@ -306,12 +258,20 @@
#endif
#if STM32_I2C_USE_I2C2
#if !STM32_DMA_IS_VALID_CHANNEL(STM32_I2C_I2C2_RX_DMA_CHANNEL)
#error "Invalid DMA channel assigned to I2C2 RX"
#if !defined(STM32_I2C_I2C2_RX_DMA_STREAM)
#error "STM32_I2C_I2C2_RX_DMA_STREAM not defined"
#endif
#if !STM32_DMA_IS_VALID_CHANNEL(STM32_I2C_I2C2_TX_DMA_CHANNEL)
#error "Invalid DMA channel assigned to I2C2 TX"
#if !defined(STM32_I2C_I2C2_TX_DMA_STREAM)
#error "STM32_I2C_I2C2_TX_DMA_STREAM not defined"
#endif
#if !STM32_DMA_IS_VALID_STREAM(STM32_I2C_I2C2_RX_DMA_STREAM)
#error "Invalid DMA stream assigned to I2C2 RX"
#endif
#if !STM32_DMA_IS_VALID_STREAM(STM32_I2C_I2C2_TX_DMA_STREAM)
#error "Invalid DMA stream assigned to I2C2 TX"
#endif
#if !STM32_DMA_IS_VALID_PRIORITY(STM32_I2C_I2C2_DMA_PRIORITY)
@ -320,12 +280,20 @@
#endif
#if STM32_I2C_USE_I2C3
#if !STM32_DMA_IS_VALID_CHANNEL(STM32_I2C_I2C3_RX_DMA_CHANNEL)
#error "Invalid DMA channel assigned to I2C3 RX"
#if !defined(STM32_I2C_I2C3_RX_DMA_STREAM)
#error "STM32_I2C_I2C3_RX_DMA_STREAM not defined"
#endif
#if !STM32_DMA_IS_VALID_CHANNEL(STM32_I2C_I2C3_TX_DMA_CHANNEL)
#error "Invalid DMA channel assigned to I2C3 TX"
#if !defined(STM32_I2C_I2C3_TX_DMA_STREAM)
#error "STM32_I2C_I2C3_TX_DMA_STREAM not defined"
#endif
#if !STM32_DMA_IS_VALID_STREAM(STM32_I2C_I2C3_RX_DMA_STREAM)
#error "Invalid DMA stream assigned to I2C3 RX"
#endif
#if !STM32_DMA_IS_VALID_STREAM(STM32_I2C_I2C3_TX_DMA_STREAM)
#error "Invalid DMA stream assigned to I2C3 TX"
#endif
#if !STM32_DMA_IS_VALID_PRIORITY(STM32_I2C_I2C3_DMA_PRIORITY)
@ -334,12 +302,20 @@
#endif
#if STM32_I2C_USE_I2C4
#if !STM32_BDMA_IS_VALID_CHANNEL(STM32_I2C_I2C4_RX_BDMA_CHANNEL)
#error "Invalid BDMA channel assigned to I2C4 RX"
#if !defined(STM32_I2C_I2C4_RX_BDMA_STREAM)
#error "STM32_I2C_I2C4_RX_BDMA_STREAM not defined"
#endif
#if !STM32_BDMA_IS_VALID_CHANNEL(STM32_I2C_I2C4_TX_BDMA_CHANNEL)
#error "Invalid BDMA channel assigned to I2C4 TX"
#if !defined(STM32_I2C_I2C4_TX_BDMA_STREAM)
#error "STM32_I2C_I2C4_TX_BDMA_STREAM not defined"
#endif
#if !STM32_BDMA_IS_VALID_STREAM(STM32_I2C_I2C4_RX_BDMA_STREAM)
#error "Invalid BDMA stream assigned to I2C4 RX"
#endif
#if !STM32_BDMA_IS_VALID_STREAM(STM32_I2C_I2C4_TX_BDMA_STREAM)
#error "Invalid BDMA stream assigned to I2C4 TX"
#endif
#if !STM32_BDMA_IS_VALID_PRIORITY(STM32_I2C_I2C4_DMA_PRIORITY)

19
os/hal/ports/STM32/LLD/OCTOSPIv1/hal_wspi_lld.c
View File

@ -169,8 +169,8 @@ void wspi_lld_init(void) {
#if STM32_WSPI_USE_OCTOSPI1
wspiObjectInit(&WSPID1);
WSPID1.ospi = OCTOSPI1;
WSPID1.dma = STM32_DMA_STREAM(STM32_WSPI_OCTOSPI1_DMA_CHANNEL);
WSPID1.dmamode = STM32_DMA_CR_CHSEL(OCTOSPI1_DMA_CHANNEL) |
WSPID1.dma = NULL;
WSPID1.dmamode = STM32_DMA_CR_CHSEL(OCTOSPI1_DMA_STREAM) |
STM32_DMA_CR_PL(STM32_WSPI_OCTOSPI1_DMA_PRIORITY) |
STM32_DMA_CR_PSIZE_BYTE |
STM32_DMA_CR_MSIZE_BYTE |
@ -183,8 +183,8 @@ void wspi_lld_init(void) {
#if STM32_WSPI_USE_OCTOSPI2
wspiObjectInit(&WSPID2);
WSPID2.ospi = OCTOSPI2;
WSPID2.dma = STM32_DMA_STREAM(STM32_WSPI_OCTOSPI2_DMA_CHANNEL);
WSPID2.dmamode = STM32_DMA_CR_CHSEL(OCTOSPI2_DMA_CHANNEL) |
WSPID2.dma = NULL;
WSPID2.dmamode = STM32_DMA_CR_CHSEL(OCTOSPI2_DMA_STREAM) |
STM32_DMA_CR_PL(STM32_WSPI_OCTOSPI2_DMA_PRIORITY) |
STM32_DMA_CR_PSIZE_BYTE |
STM32_DMA_CR_MSIZE_BYTE |
@ -208,11 +208,11 @@ void wspi_lld_start(WSPIDriver *wspip) {
if (wspip->state == WSPI_STOP) {
#if STM32_WSPI_USE_OCTOSPI1
if (&WSPID1 == wspip) {
bool b = dmaStreamAllocate(wspip->dma,
wspip->dma = dmaStreamAllocI(STM32_WSPI_OCTOSPI1_DMA_STREAM,
STM32_WSPI_OCTOSPI1_DMA_IRQ_PRIORITY,
(stm32_dmaisr_t)wspi_lld_serve_dma_interrupt,
(void *)wspip);
osalDbgAssert(!b, "stream already allocated");
osalDbgAssert(wspip->dma != NULL, "unable to allocate stream");
rccEnableOCTOSPI1(true);
dmaSetRequestSource(wspip->dma, STM32_DMAMUX1_OCTOSPI1);
}
@ -220,11 +220,11 @@ void wspi_lld_start(WSPIDriver *wspip) {
#if STM32_WSPI_USE_OCTOSPI2
if (&WSPID2 == wspip) {
bool b = dmaStreamAllocate(wspip->dma,
wspip->dma = dmaStreamAllocI(STM32_WSPI_OCTOSPI2_DMA_STREAM,
STM32_WSPI_OCTOSPI2_DMA_IRQ_PRIORITY,
(stm32_dmaisr_t)wspi_lld_serve_dma_interrupt,
(void *)wspip);
osalDbgAssert(!b, "stream already allocated");
osalDbgAssert(wspip->dma != NULL, "unable to allocate stream");
rccEnableOCTOSPI2(true);
dmaSetRequestSource(wspip->dma, STM32_DMAMUX1_OCTOSPI2);
}
@ -263,7 +263,8 @@ void wspi_lld_stop(WSPIDriver *wspip) {
wspip->ospi->CR = 0U;
/* Releasing the DMA.*/
dmaStreamRelease(wspip->dma);
dmaStreamFreeI(wspip->dma);
wspip->dma = NULL;
/* Stopping involved clocks.*/
#if STM32_WSPI_USE_OCTOSPI1

12
os/hal/ports/STM32/LLD/OCTOSPIv1/hal_wspi_lld.h
View File

@ -227,22 +227,22 @@
#endif
/* Check on the presence of the DMA channels settings in mcuconf.h.*/
#if STM32_WSPI_USE_OCTOSPI1 && !defined(STM32_WSPI_OCTOSPI1_DMA_CHANNEL)
#error "OCTOSPI1 DMA channel not defined"
#if STM32_WSPI_USE_OCTOSPI1 && !defined(STM32_WSPI_OCTOSPI1_DMA_STREAM)
#error "OCTOSPI1 DMA stream not defined"
#endif
#if STM32_WSPI_USE_OCTOSPI2 && !defined(STM32_WSPI_OCTOSPI2_DMA_CHANNEL)
#error "OCTOSPI2 DMA channel not defined"
#if STM32_WSPI_USE_OCTOSPI2 && !defined(STM32_WSPI_OCTOSPI2_DMA_STREAM)
#error "OCTOSPI2 DMA stream not defined"
#endif
/* Check on the validity of the assigned DMA channels.*/
#if STM32_WSPI_USE_OCTOSPI1 && \
!STM32_DMA_IS_VALID_CHANNEL(STM32_WSPI_OCTOSPI1_DMA_CHANNEL)
!STM32_DMA_IS_VALID_STREAM(STM32_WSPI_OCTOSPI1_DMA_STREAM)
#error "invalid DMA stream associated to OCTOSPI1"
#endif
#if STM32_WSPI_USE_OCTOSPI2 && \
!STM32_DMA_IS_VALID_CHANNEL(STM32_WSPI_OCTOSPI2_DMA_CHANNEL)
!STM32_DMA_IS_VALID_STREAM(STM32_WSPI_OCTOSPI2_DMA_STREAM)
#error "invalid DMA stream associated to OCTOSPI2"
#endif

9
os/hal/ports/STM32/LLD/QUADSPIv1/hal_wspi_lld.c
View File

@ -139,7 +139,7 @@ void wspi_lld_init(void) {
#if STM32_WSPI_USE_QUADSPI1
wspiObjectInit(&WSPID1);
WSPID1.qspi = QUADSPI;
WSPID1.dma = STM32_DMA_STREAM(STM32_WSPI_QUADSPI1_DMA_STREAM);
WSPID1.dma = NULL;
WSPID1.dmamode = STM32_DMA_CR_CHSEL(QUADSPI1_DMA_CHANNEL) |
STM32_DMA_CR_PL(STM32_WSPI_QUADSPI1_DMA_PRIORITY) |
STM32_DMA_CR_PSIZE_BYTE |
@ -164,11 +164,11 @@ void wspi_lld_start(WSPIDriver *wspip) {
if (wspip->state == WSPI_STOP) {
#if STM32_WSPI_USE_QUADSPI1
if (&WSPID1 == wspip) {
bool b = dmaStreamAllocate(wspip->dma,
wspip->dma = dmaStreamAllocI(STM32_WSPI_QUADSPI1_DMA_STREAM,
STM32_WSPI_QUADSPI1_DMA_IRQ_PRIORITY,
(stm32_dmaisr_t)wspi_lld_serve_dma_interrupt,
(void *)wspip);
osalDbgAssert(!b, "stream already allocated");
osalDbgAssert(wspip->dma != NULL, "unable to allocate stream");
rccEnableQUADSPI1(true);
}
#endif
@ -201,7 +201,8 @@ void wspi_lld_stop(WSPIDriver *wspip) {
wspip->qspi->CR = 0U;
/* Releasing the DMA.*/
dmaStreamRelease(wspip->dma);
dmaStreamFreeI(wspip->dma);
wspip->dma = NULL;
/* Stopping involved clocks.*/
#if STM32_WSPI_USE_QUADSPI1

6
os/hal/ports/STM32/LLD/QUADSPIv1/hal_wspi_lld.h
View File

@ -230,6 +230,12 @@
#error "QUADSPI1 DMA stream not defined"
#endif
/* Check on the validity of the assigned DMA channels.*/
#if STM32_WSPI_USE_QUADSPI1 && \
!STM32_DMA_IS_VALID_STREAM(STM32_WSPI_QUADSPI1_DMA_STREAM)
#error "invalid DMA stream associated to QUADSPI1"
#endif
/* Check on the validity of the assigned DMA channels.*/
#if STM32_WSPI_USE_QUADSPI1 && \
!STM32_DMA_IS_VALID_ID(STM32_WSPI_QUADSPI1_DMA_STREAM, STM32_QUADSPI1_DMA_MSK)

4
os/hal/ports/STM32/LLD/RTCv1/hal_rtc_lld.h
View File

@ -101,12 +101,12 @@ typedef void (*rtccb_t)(RTCDriver *rtcp, rtcevent_t event);
/**
* @brief Type of a structure representing an RTC alarm time stamp.
*/
typedef struct hsl_rtc_alarm {
typedef struct hal_rtc_alarm {
/**
* @brief Seconds since UNIX epoch.
*/
uint32_t tv_sec;
};
} RTCAlarm;
/**
* @brief Implementation-specific @p RTCDriver fields.

20
os/hal/ports/STM32/LLD/SDIOv1/hal_sdc_lld.c
View File

@ -346,8 +346,9 @@ void sdc_lld_init(void) {
sdcObjectInit(&SDCD1);
SDCD1.thread = NULL;
SDCD1.dma = STM32_DMA_STREAM(STM32_SDC_SDIO_DMA_STREAM);
SDCD1.dma = NULL;
SDCD1.sdio = SDIO;
nvicEnableVector(STM32_SDIO_NUMBER, STM32_SDC_SDIO_IRQ_PRIORITY);
}
/**
@ -377,15 +378,16 @@ void sdc_lld_start(SDCDriver *sdcp) {
#endif
if (sdcp->state == BLK_STOP) {
/* Note, the DMA must be enabled before the IRQs.*/
bool b;
b = dmaStreamAllocate(sdcp->dma, STM32_SDC_SDIO_IRQ_PRIORITY, NULL, NULL);
osalDbgAssert(!b, "stream already allocated");
sdcp->dma = dmaStreamAllocI(STM32_SDC_SDIO_DMA_STREAM,
STM32_SDC_SDIO_IRQ_PRIORITY,
NULL,
NULL);
osalDbgAssert(sdcp->dma != NULL, "unable to allocate stream");
dmaStreamSetPeripheral(sdcp->dma, &sdcp->sdio->FIFO);
#if (defined(STM32F4XX) || defined(STM32F2XX))
dmaStreamSetFIFO(sdcp->dma, STM32_DMA_FCR_DMDIS | STM32_DMA_FCR_FTH_FULL);
#endif
nvicEnableVector(STM32_SDIO_NUMBER, STM32_SDC_SDIO_IRQ_PRIORITY);
rccEnableSDIO(true);
}
@ -413,9 +415,11 @@ void sdc_lld_stop(SDCDriver *sdcp) {
sdcp->sdio->DCTRL = 0;
sdcp->sdio->DTIMER = 0;
/* DMA stream released.*/
dmaStreamFreeI(sdcp->dma);
sdcp->dma = NULL;
/* Clock deactivation.*/
nvicDisableVector(STM32_SDIO_NUMBER);
dmaStreamRelease(sdcp->dma);
rccDisableSDIO();
}
}

23
os/hal/ports/STM32/LLD/SDMMCv1/hal_sdc_lld.c
View File

@ -397,7 +397,7 @@ void sdc_lld_init(void) {
SDCD1.thread = NULL;
SDCD1.rtmo = SDMMC1_READ_TIMEOUT;
SDCD1.wtmo = SDMMC1_WRITE_TIMEOUT;
SDCD1.dma = STM32_DMA_STREAM(STM32_SDC_SDMMC1_DMA_STREAM);
SDCD1.dma = NULL;
SDCD1.sdmmc = SDMMC1;
nvicEnableVector(STM32_SDMMC1_NUMBER, STM32_SDC_SDMMC1_IRQ_PRIORITY);
#endif
@ -407,7 +407,7 @@ void sdc_lld_init(void) {
SDCD2.thread = NULL;
SDCD2.rtmo = SDMMC2_READ_TIMEOUT;
SDCD2.wtmo = SDMMC2_WRITE_TIMEOUT;
SDCD2.dma = STM32_DMA_STREAM(STM32_SDC_SDMMC2_DMA_STREAM);
SDCD2.dma = NULL;
SDCD2.sdmmc = SDMMC2;
nvicEnableVector(STM32_SDMMC2_NUMBER, STM32_SDC_SDMMC2_IRQ_PRIORITY);
#endif
@ -441,10 +441,11 @@ void sdc_lld_start(SDCDriver *sdcp) {
if (sdcp->state == BLK_STOP) {
#if STM32_SDC_USE_SDMMC1
if (&SDCD1 == sdcp) {
bool b = dmaStreamAllocate(sdcp->dma, STM32_SDC_SDMMC1_IRQ_PRIORITY,
NULL, NULL);
osalDbgAssert(!b, "stream already allocated");
sdcp->dma = dmaStreamAllocI(STM32_SDC_SDMMC1_DMA_STREAM,
STM32_SDC_SDMMC1_IRQ_PRIORITY,
NULL,
NULL);
osalDbgAssert(sdcp->dma != NULL, "unable to allocate stream");
sdcp->dmamode |= STM32_DMA_CR_CHSEL(SDMMC1_DMA_CHANNEL) |
STM32_DMA_CR_PL(STM32_SDC_SDMMC1_DMA_PRIORITY);
@ -459,10 +460,11 @@ void sdc_lld_start(SDCDriver *sdcp) {
#if STM32_SDC_USE_SDMMC2
if (&SDCD2 == sdcp) {
bool b = dmaStreamAllocate(sdcp->dma, STM32_SDC_SDMMC2_IRQ_PRIORITY,
NULL, NULL);
osalDbgAssert(!b, "stream already allocated");
sdcp->dma = dmaStreamAllocI(STM32_SDC_SDMMC2_DMA_STREAM,
STM32_SDC_SDMMC2_IRQ_PRIORITY,
NULL,
NULL);
osalDbgAssert(sdcp->dma != NULL, "unable to allocate stream");
sdcp->dmamode |= STM32_DMA_CR_CHSEL(SDMMC2_DMA_CHANNEL) |
STM32_DMA_CR_PL(STM32_SDC_SDMMC2_DMA_PRIORITY);
@ -502,6 +504,7 @@ void sdc_lld_stop(SDCDriver *sdcp) {
/* DMA stream released.*/
dmaStreamRelease(sdcp->dma);
sdcp->dma = NULL;
/* Clock deactivation.*/
#if STM32_SDC_USE_SDMMC1

57
os/hal/ports/STM32/LLD/SPIv1/hal_i2s_lld.c
View File

@ -226,8 +226,9 @@ void i2s_lld_init(void) {
i2sObjectInit(&I2SD1);
I2SD1.spi = SPI1;
I2SD1.cfg = STM32_I2S1_CFGR_CFG;
I2SD1.dmarx = NULL;
I2SD1.dmatx = NULL;
#if STM32_I2S_RX_ENABLED(STM32_I2S_SPI1_MODE)
I2SD1.dmarx = STM32_DMA_STREAM(STM32_I2S_SPI1_RX_DMA_STREAM);
I2SD1.rxdmamode = STM32_DMA_CR_CHSEL(I2S1_RX_DMA_CHANNEL) |
STM32_DMA_CR_PL(STM32_I2S_SPI1_DMA_PRIORITY) |
STM32_DMA_CR_PSIZE_HWORD |
@ -240,11 +241,9 @@ void i2s_lld_init(void) {
STM32_DMA_CR_DMEIE |
STM32_DMA_CR_TEIE;
#else
I2SD1.dmarx = NULL;
I2SD1.rxdmamode = 0;
#endif
#if STM32_I2S_TX_ENABLED(STM32_I2S_SPI1_MODE)
I2SD1.dmatx = STM32_DMA_STREAM(STM32_I2S_SPI1_TX_DMA_STREAM);
I2SD1.txdmamode = STM32_DMA_CR_CHSEL(I2S1_TX_DMA_CHANNEL) |
STM32_DMA_CR_PL(STM32_I2S_SPI1_DMA_PRIORITY) |
STM32_DMA_CR_PSIZE_HWORD |
@ -257,7 +256,6 @@ void i2s_lld_init(void) {
STM32_DMA_CR_DMEIE |
STM32_DMA_CR_TEIE;
#else
I2SD1.dmatx = NULL;
I2SD1.txdmamode = 0;
#endif
#endif
@ -266,8 +264,9 @@ void i2s_lld_init(void) {
i2sObjectInit(&I2SD2);
I2SD2.spi = SPI2;
I2SD2.cfg = STM32_I2S2_CFGR_CFG;
I2SD2.dmarx = NULL;
I2SD2.dmatx = NULL;
#if STM32_I2S_RX_ENABLED(STM32_I2S_SPI2_MODE)
I2SD2.dmarx = STM32_DMA_STREAM(STM32_I2S_SPI2_RX_DMA_STREAM);
I2SD2.rxdmamode = STM32_DMA_CR_CHSEL(I2S2_RX_DMA_CHANNEL) |
STM32_DMA_CR_PL(STM32_I2S_SPI2_DMA_PRIORITY) |
STM32_DMA_CR_PSIZE_HWORD |
@ -280,11 +279,9 @@ void i2s_lld_init(void) {
STM32_DMA_CR_DMEIE |
STM32_DMA_CR_TEIE;
#else
I2SD2.dmarx = NULL;
I2SD2.rxdmamode = 0;
#endif
#if STM32_I2S_TX_ENABLED(STM32_I2S_SPI2_MODE)
I2SD2.dmatx = STM32_DMA_STREAM(STM32_I2S_SPI2_TX_DMA_STREAM);
I2SD2.txdmamode = STM32_DMA_CR_CHSEL(I2S2_TX_DMA_CHANNEL) |
STM32_DMA_CR_PL(STM32_I2S_SPI2_DMA_PRIORITY) |
STM32_DMA_CR_PSIZE_HWORD |
@ -297,7 +294,6 @@ void i2s_lld_init(void) {
STM32_DMA_CR_DMEIE |
STM32_DMA_CR_TEIE;
#else
I2SD2.dmatx = NULL;
I2SD2.txdmamode = 0;
#endif
#endif
@ -306,8 +302,9 @@ void i2s_lld_init(void) {
i2sObjectInit(&I2SD3);
I2SD3.spi = SPI3;
I2SD3.cfg = STM32_I2S3_CFGR_CFG;
I2SD3.dmarx = NULL;
I2SD3.dmatx = NULL;
#if STM32_I2S_RX_ENABLED(STM32_I2S_SPI3_MODE)
I2SD3.dmarx = STM32_DMA_STREAM(STM32_I2S_SPI3_RX_DMA_STREAM);
I2SD3.rxdmamode = STM32_DMA_CR_CHSEL(I2S3_RX_DMA_CHANNEL) |
STM32_DMA_CR_PL(STM32_I2S_SPI3_DMA_PRIORITY) |
STM32_DMA_CR_PSIZE_HWORD |
@ -320,11 +317,9 @@ void i2s_lld_init(void) {
STM32_DMA_CR_DMEIE |
STM32_DMA_CR_TEIE;
#else
I2SD3.dmarx = NULL;
I2SD3.rxdmamode = 0;
#endif
#if STM32_I2S_TX_ENABLED(STM32_I2S_SPI3_MODE)
I2SD3.dmatx = STM32_DMA_STREAM(STM32_I2S_SPI3_TX_DMA_STREAM);
I2SD3.txdmamode = STM32_DMA_CR_CHSEL(I2S3_TX_DMA_CHANNEL) |
STM32_DMA_CR_PL(STM32_I2S_SPI3_DMA_PRIORITY) |
STM32_DMA_CR_PSIZE_HWORD |
@ -337,7 +332,6 @@ void i2s_lld_init(void) {
STM32_DMA_CR_DMEIE |
STM32_DMA_CR_TEIE;
#else
I2SD3.dmatx = NULL;
I2SD3.txdmamode = 0;
#endif
#endif
@ -357,17 +351,16 @@ void i2s_lld_start(I2SDriver *i2sp) {
#if STM32_I2S_USE_SPI1
if (&I2SD1 == i2sp) {
bool b;
/* Enabling I2S unit clock.*/
rccEnableSPI1(true);
#if STM32_I2S_RX_ENABLED(STM32_I2S_SPI1_MODE)
b = dmaStreamAllocate(i2sp->dmarx,
i2sp->dmarx = dmaStreamAllocI(STM32_I2S_SPI1_RX_DMA_STREAM,
STM32_I2S_SPI1_IRQ_PRIORITY,
(stm32_dmaisr_t)i2s_lld_serve_rx_interrupt,
(void *)i2sp);
osalDbgAssert(!b, "stream already allocated");
osalDbgAssert(i2sp->dmarx != NULL, "unable to allocate stream");
/* CRs settings are done here because those never changes until
the driver is stopped.*/
@ -375,11 +368,11 @@ void i2s_lld_start(I2SDriver *i2sp) {
i2sp->spi->CR2 = SPI_CR2_RXDMAEN;
#endif
#if STM32_I2S_TX_ENABLED(STM32_I2S_SPI1_MODE)
b = dmaStreamAllocate(i2sp->dmatx,
i2sp->dmatx = dmaStreamAllocI(STM32_I2S_SPI1_TX_DMA_STREAM,
STM32_I2S_SPI1_IRQ_PRIORITY,
(stm32_dmaisr_t)i2s_lld_serve_tx_interrupt,
(void *)i2sp);
osalDbgAssert(!b, "stream already allocated");
osalDbgAssert(i2sp->dmatx != NULL, "unable to allocate stream");
/* CRs settings are done here because those never changes until
the driver is stopped.*/
@ -391,17 +384,16 @@ void i2s_lld_start(I2SDriver *i2sp) {
#if STM32_I2S_USE_SPI2
if (&I2SD2 == i2sp) {
bool b;
/* Enabling I2S unit clock.*/
rccEnableSPI2(true);
#if STM32_I2S_RX_ENABLED(STM32_I2S_SPI2_MODE)
b = dmaStreamAllocate(i2sp->dmarx,
i2sp->dmarx = dmaStreamAllocI(STM32_I2S_SPI2_RX_DMA_STREAM,
STM32_I2S_SPI2_IRQ_PRIORITY,
(stm32_dmaisr_t)i2s_lld_serve_rx_interrupt,
(void *)i2sp);
osalDbgAssert(!b, "stream already allocated");
osalDbgAssert(i2sp->dmarx != NULL, "unable to allocate stream");
/* CRs settings are done here because those never changes until
the driver is stopped.*/
@ -409,11 +401,11 @@ void i2s_lld_start(I2SDriver *i2sp) {
i2sp->spi->CR2 = SPI_CR2_RXDMAEN;
#endif
#if STM32_I2S_TX_ENABLED(STM32_I2S_SPI2_MODE)
b = dmaStreamAllocate(i2sp->dmatx,
i2sp->dmatx = dmaStreamAllocI(STM32_I2S_SPI2_TX_DMA_STREAM,
STM32_I2S_SPI2_IRQ_PRIORITY,
(stm32_dmaisr_t)i2s_lld_serve_tx_interrupt,
(void *)i2sp);
osalDbgAssert(!b, "stream already allocated");
osalDbgAssert(i2sp->dmatx != NULL, "unable to allocate stream");
/* CRs settings are done here because those never changes until
the driver is stopped.*/
@ -425,17 +417,16 @@ void i2s_lld_start(I2SDriver *i2sp) {
#if STM32_I2S_USE_SPI3
if (&I2SD3 == i2sp) {
bool b;
/* Enabling I2S unit clock.*/
rccEnableSPI3(true);
#if STM32_I2S_RX_ENABLED(STM32_I2S_SPI3_MODE)
b = dmaStreamAllocate(i2sp->dmarx,
i2sp->dmarx = dmaStreamAllocI(STM32_I2S_SPI3_RX_DMA_STREAM,
STM32_I2S_SPI3_IRQ_PRIORITY,
(stm32_dmaisr_t)i2s_lld_serve_rx_interrupt,
(void *)i2sp);
osalDbgAssert(!b, "stream already allocated");
osalDbgAssert(i2sp->dmarx != NULL, "unable to allocate stream");
/* CRs settings are done here because those never changes until
the driver is stopped.*/
@ -443,11 +434,11 @@ void i2s_lld_start(I2SDriver *i2sp) {
i2sp->spi->CR2 = SPI_CR2_RXDMAEN;
#endif
#if STM32_I2S_TX_ENABLED(STM32_I2S_SPI3_MODE)
b = dmaStreamAllocate(i2sp->dmatx,
i2sp->dmatx = dmaStreamAllocI(STM32_I2S_SPI3_TX_DMA_STREAM,
STM32_I2S_SPI3_IRQ_PRIORITY,
(stm32_dmaisr_t)i2s_lld_serve_tx_interrupt,
(void *)i2sp);
osalDbgAssert(!b, "stream already allocated");
osalDbgAssert(i2sp->dmatx != NULL, "unable to allocate stream");
/* CRs settings are done here because those never changes until
the driver is stopped.*/
@ -477,10 +468,14 @@ void i2s_lld_stop(I2SDriver *i2sp) {
/* SPI disable.*/
i2sp->spi->CR2 = 0;
if (NULL != i2sp->dmarx)
dmaStreamRelease(i2sp->dmarx);
if (NULL != i2sp->dmatx)
dmaStreamRelease(i2sp->dmatx);
if (NULL != i2sp->dmarx) {
dmaStreamFreeI(i2sp->dmarx);
i2sp->dmarx = NULL;
}
if (NULL != i2sp->dmatx) {
dmaStreamFreeI(i2sp->dmatx);
i2sp->dmatx = NULL;
}
#if STM32_I2S_USE_SPI1
if (&I2SD1 == i2sp)

84
os/hal/ports/STM32/LLD/SPIv1/hal_spi_lld.c
View File

@ -199,8 +199,8 @@ void spi_lld_init(void) {
#if STM32_SPI_USE_SPI1
spiObjectInit(&SPID1);
SPID1.spi = SPI1;
SPID1.dmarx = STM32_DMA_STREAM(STM32_SPI_SPI1_RX_DMA_STREAM);
SPID1.dmatx = STM32_DMA_STREAM(STM32_SPI_SPI1_TX_DMA_STREAM);
SPID1.dmarx = NULL;
SPID1.dmatx = NULL;
SPID1.rxdmamode = STM32_DMA_CR_CHSEL(SPI1_RX_DMA_CHANNEL) |
STM32_DMA_CR_PL(STM32_SPI_SPI1_DMA_PRIORITY) |
STM32_DMA_CR_DIR_P2M |
@ -217,8 +217,8 @@ void spi_lld_init(void) {
#if STM32_SPI_USE_SPI2
spiObjectInit(&SPID2);
SPID2.spi = SPI2;
SPID2.dmarx = STM32_DMA_STREAM(STM32_SPI_SPI2_RX_DMA_STREAM);
SPID2.dmatx = STM32_DMA_STREAM(STM32_SPI_SPI2_TX_DMA_STREAM);
SPID2.dmarx = NULL;
SPID2.dmatx = NULL;
SPID2.rxdmamode = STM32_DMA_CR_CHSEL(SPI2_RX_DMA_CHANNEL) |
STM32_DMA_CR_PL(STM32_SPI_SPI2_DMA_PRIORITY) |
STM32_DMA_CR_DIR_P2M |
@ -235,8 +235,8 @@ void spi_lld_init(void) {
#if STM32_SPI_USE_SPI3
spiObjectInit(&SPID3);
SPID3.spi = SPI3;
SPID3.dmarx = STM32_DMA_STREAM(STM32_SPI_SPI3_RX_DMA_STREAM);
SPID3.dmatx = STM32_DMA_STREAM(STM32_SPI_SPI3_TX_DMA_STREAM);
SPID3.dmarx = NULL;
SPID3.dmatx = NULL;
SPID3.rxdmamode = STM32_DMA_CR_CHSEL(SPI3_RX_DMA_CHANNEL) |
STM32_DMA_CR_PL(STM32_SPI_SPI3_DMA_PRIORITY) |
STM32_DMA_CR_DIR_P2M |
@ -253,8 +253,8 @@ void spi_lld_init(void) {
#if STM32_SPI_USE_SPI4
spiObjectInit(&SPID4);
SPID4.spi = SPI4;
SPID4.dmarx = STM32_DMA_STREAM(STM32_SPI_SPI4_RX_DMA_STREAM);
SPID4.dmatx = STM32_DMA_STREAM(STM32_SPI_SPI4_TX_DMA_STREAM);
SPID4.dmarx = NULL;
SPID4.dmatx = NULL;
SPID4.rxdmamode = STM32_DMA_CR_CHSEL(SPI4_RX_DMA_CHANNEL) |
STM32_DMA_CR_PL(STM32_SPI_SPI4_DMA_PRIORITY) |
STM32_DMA_CR_DIR_P2M |
@ -271,8 +271,8 @@ void spi_lld_init(void) {
#if STM32_SPI_USE_SPI5
spiObjectInit(&SPID5);
SPID5.spi = SPI5;
SPID5.dmarx = STM32_DMA_STREAM(STM32_SPI_SPI5_RX_DMA_STREAM);
SPID5.dmatx = STM32_DMA_STREAM(STM32_SPI_SPI5_TX_DMA_STREAM);
SPID5.dmarx = NULL;
SPID5.dmatx = NULL;
SPID5.rxdmamode = STM32_DMA_CR_CHSEL(SPI5_RX_DMA_CHANNEL) |
STM32_DMA_CR_PL(STM32_SPI_SPI5_DMA_PRIORITY) |
STM32_DMA_CR_DIR_P2M |
@ -289,8 +289,8 @@ void spi_lld_init(void) {
#if STM32_SPI_USE_SPI6
spiObjectInit(&SPID6);
SPID6.spi = SPI6;
SPID6.dmarx = STM32_DMA_STREAM(STM32_SPI_SPI6_RX_DMA_STREAM);
SPID6.dmatx = STM32_DMA_STREAM(STM32_SPI_SPI6_TX_DMA_STREAM);
SPID6.dmarx = NULL;
SPID6.dmatx = NULL;
SPID6.rxdmamode = STM32_DMA_CR_CHSEL(SPI6_RX_DMA_CHANNEL) |
STM32_DMA_CR_PL(STM32_SPI_SPI6_DMA_PRIORITY) |
STM32_DMA_CR_DIR_P2M |
@ -318,97 +318,91 @@ void spi_lld_start(SPIDriver *spip) {
if (spip->state == SPI_STOP) {
#if STM32_SPI_USE_SPI1
if (&SPID1 == spip) {
bool b;
b = dmaStreamAllocate(spip->dmarx,
spip->dmarx = dmaStreamAllocI(STM32_SPI_SPI1_RX_DMA_STREAM,
STM32_SPI_SPI1_IRQ_PRIORITY,
(stm32_dmaisr_t)spi_lld_serve_rx_interrupt,
(void *)spip);
osalDbgAssert(!b, "stream already allocated");
b = dmaStreamAllocate(spip->dmatx,
osalDbgAssert(spip->dmarx != NULL, "unable to allocate stream");
spip->dmatx = dmaStreamAllocI(STM32_SPI_SPI1_TX_DMA_STREAM,
STM32_SPI_SPI1_IRQ_PRIORITY,
(stm32_dmaisr_t)spi_lld_serve_tx_interrupt,
(void *)spip);
osalDbgAssert(!b, "stream already allocated");
osalDbgAssert(spip->dmatx != NULL, "unable to allocate stream");
rccEnableSPI1(true);
}
#endif
#if STM32_SPI_USE_SPI2
if (&SPID2 == spip) {
bool b;
b = dmaStreamAllocate(spip->dmarx,
spip->dmarx = dmaStreamAllocI(STM32_SPI_SPI2_RX_DMA_STREAM,
STM32_SPI_SPI2_IRQ_PRIORITY,
(stm32_dmaisr_t)spi_lld_serve_rx_interrupt,
(void *)spip);
osalDbgAssert(!b, "stream already allocated");
b = dmaStreamAllocate(spip->dmatx,
osalDbgAssert(spip->dmarx != NULL, "unable to allocate stream");
spip->dmatx = dmaStreamAllocI(STM32_SPI_SPI2_TX_DMA_STREAM,
STM32_SPI_SPI2_IRQ_PRIORITY,
(stm32_dmaisr_t)spi_lld_serve_tx_interrupt,
(void *)spip);
osalDbgAssert(!b, "stream already allocated");
osalDbgAssert(spip->dmatx != NULL, "unable to allocate stream");
rccEnableSPI2(true);
}
#endif
#if STM32_SPI_USE_SPI3
if (&SPID3 == spip) {
bool b;
b = dmaStreamAllocate(spip->dmarx,
spip->dmarx = dmaStreamAllocI(STM32_SPI_SPI3_RX_DMA_STREAM,
STM32_SPI_SPI3_IRQ_PRIORITY,
(stm32_dmaisr_t)spi_lld_serve_rx_interrupt,
(void *)spip);
osalDbgAssert(!b, "stream already allocated");
b = dmaStreamAllocate(spip->dmatx,
osalDbgAssert(spip->dmarx != NULL, "unable to allocate stream");
spip->dmatx = dmaStreamAllocI(STM32_SPI_SPI3_TX_DMA_STREAM,
STM32_SPI_SPI3_IRQ_PRIORITY,
(stm32_dmaisr_t)spi_lld_serve_tx_interrupt,
(void *)spip);
osalDbgAssert(!b, "stream already allocated");
osalDbgAssert(spip->dmatx != NULL, "unable to allocate stream");
rccEnableSPI3(true);
}
#endif
#if STM32_SPI_USE_SPI4
if (&SPID4 == spip) {
bool b;
b = dmaStreamAllocate(spip->dmarx,
spip->dmarx = dmaStreamAllocI(STM32_SPI_SPI4_RX_DMA_STREAM,
STM32_SPI_SPI4_IRQ_PRIORITY,
(stm32_dmaisr_t)spi_lld_serve_rx_interrupt,
(void *)spip);
osalDbgAssert(!b, "stream already allocated");
b = dmaStreamAllocate(spip->dmatx,
osalDbgAssert(spip->dmarx != NULL, "unable to allocate stream");
spip->dmatx = dmaStreamAllocI(STM32_SPI_SPI4_TX_DMA_STREAM,
STM32_SPI_SPI4_IRQ_PRIORITY,
(stm32_dmaisr_t)spi_lld_serve_tx_interrupt,
(void *)spip);
osalDbgAssert(!b, "stream already allocated");
osalDbgAssert(spip->dmatx != NULL, "unable to allocate stream");
rccEnableSPI4(true);
}
#endif
#if STM32_SPI_USE_SPI5
if (&SPID5 == spip) {
bool b;
b = dmaStreamAllocate(spip->dmarx,
spip->dmarx = dmaStreamAllocI(STM32_SPI_SPI5_RX_DMA_STREAM,
STM32_SPI_SPI5_IRQ_PRIORITY,
(stm32_dmaisr_t)spi_lld_serve_rx_interrupt,
(void *)spip);
osalDbgAssert(!b, "stream already allocated");
b = dmaStreamAllocate(spip->dmatx,
osalDbgAssert(spip->dmarx != NULL, "unable to allocate stream");
spip->dmatx = dmaStreamAllocI(STM32_SPI_SPI5_TX_DMA_STREAM,
STM32_SPI_SPI5_IRQ_PRIORITY,
(stm32_dmaisr_t)spi_lld_serve_tx_interrupt,
(void *)spip);
osalDbgAssert(!b, "stream already allocated");
osalDbgAssert(spip->dmatx != NULL, "unable to allocate stream");
rccEnableSPI5(true);
}
#endif
#if STM32_SPI_USE_SPI6
if (&SPID6 == spip) {
bool b;
b = dmaStreamAllocate(spip->dmarx,
spip->dmarx = dmaStreamAllocI(STM32_SPI_SPI6_RX_DMA_STREAM,
STM32_SPI_SPI6_IRQ_PRIORITY,
(stm32_dmaisr_t)spi_lld_serve_rx_interrupt,
(void *)spip);
osalDbgAssert(!b, "stream already allocated");
b = dmaStreamAllocate(spip->dmatx,
osalDbgAssert(spip->dmarx != NULL, "unable to allocate stream");
spip->dmatx = dmaStreamAllocI(STM32_SPI_SPI6_TX_DMA_STREAM,
STM32_SPI_SPI6_IRQ_PRIORITY,
(stm32_dmaisr_t)spi_lld_serve_tx_interrupt,
(void *)spip);
osalDbgAssert(!b, "stream already allocated");
osalDbgAssert(spip->dmatx != NULL, "unable to allocate stream");
rccEnableSPI6(true);
}
#endif
@ -468,8 +462,10 @@ void spi_lld_stop(SPIDriver *spip) {
spip->spi->CR1 &= ~SPI_CR1_SPE;
spip->spi->CR1 = 0;
spip->spi->CR2 = 0;
dmaStreamRelease(spip->dmarx);
dmaStreamRelease(spip->dmatx);
dmaStreamFreeI(spip->dmarx);
dmaStreamFreeI(spip->dmatx);
spip->dmarx = NULL;
spip->dmatx = NULL;
#if STM32_SPI_USE_SPI1
if (&SPID1 == spip)

61
os/hal/ports/STM32/LLD/SPIv2/hal_i2s_lld.c
View File

@ -198,11 +198,11 @@ static void i2s_lld_serve_tx_interrupt(I2SDriver *i2sp, uint32_t flags) {
level driver.*/
if ((flags & STM32_DMA_ISR_TCIF) != 0) {
/* Transfer complete processing.*/
_i2s_isr_code_half2(i2sp);
_i2s_isr_full_code(i2sp);
}
else if ((flags & STM32_DMA_ISR_HTIF) != 0) {
/* Half transfer processing.*/
_i2s_isr_code_half1(i2sp);
_i2s_isr_half_code(i2sp);
}
}
#endif
@ -226,8 +226,9 @@ void i2s_lld_init(void) {
i2sObjectInit(&I2SD1);
I2SD1.spi = SPI1;
I2SD1.cfg = STM32_I2S1_CFGR_CFG;
I2SD1.dmarx = NULL;
I2SD1.dmatx = NULL;
#if STM32_I2S_RX_ENABLED(STM32_I2S_SPI1_MODE)
I2SD1.dmarx = STM32_DMA_STREAM(STM32_I2S_SPI1_RX_DMA_STREAM);
I2SD1.rxdmamode = STM32_DMA_CR_CHSEL(I2S1_RX_DMA_CHANNEL) |
STM32_DMA_CR_PL(STM32_I2S_SPI1_DMA_PRIORITY) |
STM32_DMA_CR_PSIZE_HWORD |
@ -240,11 +241,9 @@ void i2s_lld_init(void) {
STM32_DMA_CR_DMEIE |
STM32_DMA_CR_TEIE;
#else
I2SD1.dmarx = NULL;
I2SD1.rxdmamode = 0;
#endif
#if STM32_I2S_TX_ENABLED(STM32_I2S_SPI1_MODE)
I2SD1.dmatx = STM32_DMA_STREAM(STM32_I2S_SPI1_TX_DMA_STREAM);
I2SD1.txdmamode = STM32_DMA_CR_CHSEL(I2S1_TX_DMA_CHANNEL) |
STM32_DMA_CR_PL(STM32_I2S_SPI1_DMA_PRIORITY) |
STM32_DMA_CR_PSIZE_HWORD |
@ -257,7 +256,6 @@ void i2s_lld_init(void) {
STM32_DMA_CR_DMEIE |
STM32_DMA_CR_TEIE;
#else
I2SD1.dmatx = NULL;
I2SD1.txdmamode = 0;
#endif
#endif
@ -266,8 +264,9 @@ void i2s_lld_init(void) {
i2sObjectInit(&I2SD2);
I2SD2.spi = SPI2;
I2SD2.cfg = STM32_I2S2_CFGR_CFG;
I2SD2.dmarx = NULL;
I2SD2.dmatx = NULL;
#if STM32_I2S_RX_ENABLED(STM32_I2S_SPI2_MODE)
I2SD2.dmarx = STM32_DMA_STREAM(STM32_I2S_SPI2_RX_DMA_STREAM);
I2SD2.rxdmamode = STM32_DMA_CR_CHSEL(I2S2_RX_DMA_CHANNEL) |
STM32_DMA_CR_PL(STM32_I2S_SPI2_DMA_PRIORITY) |
STM32_DMA_CR_PSIZE_HWORD |
@ -280,11 +279,9 @@ void i2s_lld_init(void) {
STM32_DMA_CR_DMEIE |
STM32_DMA_CR_TEIE;
#else
I2SD2.dmarx = NULL;
I2SD2.rxdmamode = 0;
#endif
#if STM32_I2S_TX_ENABLED(STM32_I2S_SPI2_MODE)
I2SD2.dmatx = STM32_DMA_STREAM(STM32_I2S_SPI2_TX_DMA_STREAM);
I2SD2.txdmamode = STM32_DMA_CR_CHSEL(I2S2_TX_DMA_CHANNEL) |
STM32_DMA_CR_PL(STM32_I2S_SPI2_DMA_PRIORITY) |
STM32_DMA_CR_PSIZE_HWORD |
@ -297,7 +294,6 @@ void i2s_lld_init(void) {
STM32_DMA_CR_DMEIE |
STM32_DMA_CR_TEIE;
#else
I2SD2.dmatx = NULL;
I2SD2.txdmamode = 0;
#endif
#endif
@ -306,8 +302,9 @@ void i2s_lld_init(void) {
i2sObjectInit(&I2SD3);
I2SD3.spi = SPI3;
I2SD3.cfg = STM32_I2S3_CFGR_CFG;
I2SD3.dmarx = NULL;
I2SD3.dmatx = NULL;
#if STM32_I2S_RX_ENABLED(STM32_I2S_SPI3_MODE)
I2SD3.dmarx = STM32_DMA_STREAM(STM32_I2S_SPI3_RX_DMA_STREAM);
I2SD3.rxdmamode = STM32_DMA_CR_CHSEL(I2S3_RX_DMA_CHANNEL) |
STM32_DMA_CR_PL(STM32_I2S_SPI3_DMA_PRIORITY) |
STM32_DMA_CR_PSIZE_HWORD |
@ -320,11 +317,9 @@ void i2s_lld_init(void) {
STM32_DMA_CR_DMEIE |
STM32_DMA_CR_TEIE;
#else
I2SD3.dmarx = NULL;
I2SD3.rxdmamode = 0;
#endif
#if STM32_I2S_TX_ENABLED(STM32_I2S_SPI3_MODE)
I2SD3.dmatx = STM32_DMA_STREAM(STM32_I2S_SPI3_TX_DMA_STREAM);
I2SD3.txdmamode = STM32_DMA_CR_CHSEL(I2S3_TX_DMA_CHANNEL) |
STM32_DMA_CR_PL(STM32_I2S_SPI3_DMA_PRIORITY) |
STM32_DMA_CR_PSIZE_HWORD |
@ -337,7 +332,6 @@ void i2s_lld_init(void) {
STM32_DMA_CR_DMEIE |
STM32_DMA_CR_TEIE;
#else
I2SD3.dmatx = NULL;
I2SD3.txdmamode = 0;
#endif
#endif
@ -357,17 +351,16 @@ void i2s_lld_start(I2SDriver *i2sp) {
#if STM32_I2S_USE_SPI1
if (&I2SD1 == i2sp) {
bool b;
/* Enabling I2S unit clock.*/
rccEnableSPI1(true);
#if STM32_I2S_RX_ENABLED(STM32_I2S_SPI1_MODE)
b = dmaStreamAllocate(i2sp->dmarx,
i2sp->dmarx = dmaStreamAllocI(STM32_I2S_SPI1_RX_DMA_STREAM,
STM32_I2S_SPI1_IRQ_PRIORITY,
(stm32_dmaisr_t)i2s_lld_serve_rx_interrupt,
(void *)i2sp);
osalDbgAssert(!b, "stream already allocated");
osalDbgAssert(i2sp->dmarx != NULL, "unable to allocate stream");
/* CRs settings are done here because those never changes until
the driver is stopped.*/
@ -375,11 +368,11 @@ void i2s_lld_start(I2SDriver *i2sp) {
i2sp->spi->CR2 = SPI_CR2_RXDMAEN;
#endif
#if STM32_I2S_TX_ENABLED(STM32_I2S_SPI1_MODE)
b = dmaStreamAllocate(i2sp->dmatx,
i2sp->dmatx = dmaStreamAllocI(STM32_I2S_SPI1_TX_DMA_STREAM,
STM32_I2S_SPI1_IRQ_PRIORITY,
(stm32_dmaisr_t)i2s_lld_serve_tx_interrupt,
(void *)i2sp);
osalDbgAssert(!b, "stream already allocated");
osalDbgAssert(i2sp->dmatx != NULL, "unable to allocate stream");
/* CRs settings are done here because those never changes until
the driver is stopped.*/
@ -391,17 +384,16 @@ void i2s_lld_start(I2SDriver *i2sp) {
#if STM32_I2S_USE_SPI2
if (&I2SD2 == i2sp) {
bool b;
/* Enabling I2S unit clock.*/
rccEnableSPI2(true);
#if STM32_I2S_RX_ENABLED(STM32_I2S_SPI2_MODE)
b = dmaStreamAllocate(i2sp->dmarx,
i2sp->dmarx = dmaStreamAllocI(STM32_I2S_SPI2_RX_DMA_STREAM,
STM32_I2S_SPI2_IRQ_PRIORITY,
(stm32_dmaisr_t)i2s_lld_serve_rx_interrupt,
(void *)i2sp);
osalDbgAssert(!b, "stream already allocated");
osalDbgAssert(i2sp->dmarx != NULL, "unable to allocate stream");
/* CRs settings are done here because those never changes until
the driver is stopped.*/
@ -409,11 +401,11 @@ void i2s_lld_start(I2SDriver *i2sp) {
i2sp->spi->CR2 = SPI_CR2_RXDMAEN;
#endif
#if STM32_I2S_TX_ENABLED(STM32_I2S_SPI2_MODE)
b = dmaStreamAllocate(i2sp->dmatx,
i2sp->dmatx = dmaStreamAllocI(STM32_I2S_SPI2_TX_DMA_STREAM,
STM32_I2S_SPI2_IRQ_PRIORITY,
(stm32_dmaisr_t)i2s_lld_serve_tx_interrupt,
(void *)i2sp);
osalDbgAssert(!b, "stream already allocated");
osalDbgAssert(i2sp->dmatx != NULL, "unable to allocate stream");
/* CRs settings are done here because those never changes until
the driver is stopped.*/
@ -425,17 +417,16 @@ void i2s_lld_start(I2SDriver *i2sp) {
#if STM32_I2S_USE_SPI3
if (&I2SD3 == i2sp) {
bool b;
/* Enabling I2S unit clock.*/
rccEnableSPI3(true);
#if STM32_I2S_RX_ENABLED(STM32_I2S_SPI3_MODE)
b = dmaStreamAllocate(i2sp->dmarx,
i2sp->dmarx = dmaStreamAllocI(STM32_I2S_SPI3_RX_DMA_STREAM,
STM32_I2S_SPI3_IRQ_PRIORITY,
(stm32_dmaisr_t)i2s_lld_serve_rx_interrupt,
(void *)i2sp);
osalDbgAssert(!b, "stream already allocated");
osalDbgAssert(i2sp->dmarx != NULL, "unable to allocate stream");
/* CRs settings are done here because those never changes until
the driver is stopped.*/
@ -443,11 +434,11 @@ void i2s_lld_start(I2SDriver *i2sp) {
i2sp->spi->CR2 = SPI_CR2_RXDMAEN;
#endif
#if STM32_I2S_TX_ENABLED(STM32_I2S_SPI3_MODE)
b = dmaStreamAllocate(i2sp->dmatx,
i2sp->dmatx = dmaStreamAllocI(STM32_I2S_SPI3_TX_DMA_STREAM,
STM32_I2S_SPI3_IRQ_PRIORITY,
(stm32_dmaisr_t)i2s_lld_serve_tx_interrupt,
(void *)i2sp);
osalDbgAssert(!b, "stream already allocated");
osalDbgAssert(i2sp->dmatx != NULL, "unable to allocate stream");
/* CRs settings are done here because those never changes until
the driver is stopped.*/
@ -477,10 +468,14 @@ void i2s_lld_stop(I2SDriver *i2sp) {
/* SPI disable.*/
i2sp->spi->CR2 = 0;
if (NULL != i2sp->dmarx)
dmaStreamRelease(i2sp->dmarx);
if (NULL != i2sp->dmatx)
dmaStreamRelease(i2sp->dmatx);
if (NULL != i2sp->dmarx) {
dmaStreamFreeI(i2sp->dmarx);
i2sp->dmarx = NULL;
}
if (NULL != i2sp->dmatx) {
dmaStreamFreeI(i2sp->dmatx);
i2sp->dmatx = NULL;
}
#if STM32_I2S_USE_SPI1
if (&I2SD1 == i2sp)

162
os/hal/ports/STM32/LLD/SPIv2/hal_spi_lld.c
View File

@ -30,51 +30,51 @@
/* Driver local definitions. */
/*===========================================================================*/
#define SPI1_RX_DMA_CHANNEL \
#define SPI1_RX_DMA_STREAM \
STM32_DMA_GETCHANNEL(STM32_SPI_SPI1_RX_DMA_STREAM, \
STM32_SPI1_RX_DMA_CHN)
#define SPI1_TX_DMA_CHANNEL \
#define SPI1_TX_DMA_STREAM \
STM32_DMA_GETCHANNEL(STM32_SPI_SPI1_TX_DMA_STREAM, \
STM32_SPI1_TX_DMA_CHN)
#define SPI2_RX_DMA_CHANNEL \
#define SPI2_RX_DMA_STREAM \
STM32_DMA_GETCHANNEL(STM32_SPI_SPI2_RX_DMA_STREAM, \
STM32_SPI2_RX_DMA_CHN)
#define SPI2_TX_DMA_CHANNEL \
#define SPI2_TX_DMA_STREAM \
STM32_DMA_GETCHANNEL(STM32_SPI_SPI2_TX_DMA_STREAM, \
STM32_SPI2_TX_DMA_CHN)
#define SPI3_RX_DMA_CHANNEL \
#define SPI3_RX_DMA_STREAM \
STM32_DMA_GETCHANNEL(STM32_SPI_SPI3_RX_DMA_STREAM, \
STM32_SPI3_RX_DMA_CHN)
#define SPI3_TX_DMA_CHANNEL \
#define SPI3_TX_DMA_STREAM \
STM32_DMA_GETCHANNEL(STM32_SPI_SPI3_TX_DMA_STREAM, \
STM32_SPI3_TX_DMA_CHN)
#define SPI4_RX_DMA_CHANNEL \
#define SPI4_RX_DMA_STREAM \
STM32_DMA_GETCHANNEL(STM32_SPI_SPI4_RX_DMA_STREAM, \
STM32_SPI4_RX_DMA_CHN)
#define SPI4_TX_DMA_CHANNEL \
#define SPI4_TX_DMA_STREAM \
STM32_DMA_GETCHANNEL(STM32_SPI_SPI4_TX_DMA_STREAM, \
STM32_SPI4_TX_DMA_CHN)
#define SPI5_RX_DMA_CHANNEL \
#define SPI5_RX_DMA_STREAM \
STM32_DMA_GETCHANNEL(STM32_SPI_SPI5_RX_DMA_STREAM, \
STM32_SPI5_RX_DMA_CHN)
#define SPI5_TX_DMA_CHANNEL \
#define SPI5_TX_DMA_STREAM \
STM32_DMA_GETCHANNEL(STM32_SPI_SPI5_TX_DMA_STREAM, \
STM32_SPI5_TX_DMA_CHN)
#define SPI6_RX_DMA_CHANNEL \
#define SPI6_RX_DMA_STREAM \
STM32_DMA_GETCHANNEL(STM32_SPI_SPI6_RX_DMA_STREAM, \
STM32_SPI6_RX_DMA_CHN)
#define SPI6_TX_DMA_CHANNEL \
#define SPI6_TX_DMA_STREAM \
STM32_DMA_GETCHANNEL(STM32_SPI_SPI6_TX_DMA_STREAM, \
STM32_SPI6_TX_DMA_CHN)
@ -199,20 +199,15 @@ void spi_lld_init(void) {
#if STM32_SPI_USE_SPI1
spiObjectInit(&SPID1);
SPID1.spi = SPI1;
#if STM32_DMA_SUPPORTS_DMAMUX
SPID1.dmarx = STM32_DMA_STREAM(STM32_SPI_SPI1_RX_DMA_CHANNEL);
SPID1.dmatx = STM32_DMA_STREAM(STM32_SPI_SPI1_TX_DMA_CHANNEL);
#else
SPID1.dmarx = STM32_DMA_STREAM(STM32_SPI_SPI1_RX_DMA_STREAM);
SPID1.dmatx = STM32_DMA_STREAM(STM32_SPI_SPI1_TX_DMA_STREAM);
#endif
SPID1.rxdmamode = STM32_DMA_CR_CHSEL(SPI1_RX_DMA_CHANNEL) |
SPID1.dmarx = NULL;
SPID1.dmatx = NULL;
SPID1.rxdmamode = STM32_DMA_CR_CHSEL(SPI1_RX_DMA_STREAM) |
STM32_DMA_CR_PL(STM32_SPI_SPI1_DMA_PRIORITY) |
STM32_DMA_CR_DIR_P2M |
STM32_DMA_CR_TCIE |
STM32_DMA_CR_DMEIE |
STM32_DMA_CR_TEIE;
SPID1.txdmamode = STM32_DMA_CR_CHSEL(SPI1_TX_DMA_CHANNEL) |
SPID1.txdmamode = STM32_DMA_CR_CHSEL(SPI1_TX_DMA_STREAM) |
STM32_DMA_CR_PL(STM32_SPI_SPI1_DMA_PRIORITY) |
STM32_DMA_CR_DIR_M2P |
STM32_DMA_CR_DMEIE |
@ -222,20 +217,15 @@ void spi_lld_init(void) {
#if STM32_SPI_USE_SPI2
spiObjectInit(&SPID2);
SPID2.spi = SPI2;
#if STM32_DMA_SUPPORTS_DMAMUX
SPID2.dmarx = STM32_DMA_STREAM(STM32_SPI_SPI2_RX_DMA_CHANNEL);
SPID2.dmatx = STM32_DMA_STREAM(STM32_SPI_SPI2_TX_DMA_CHANNEL);
#else
SPID2.dmarx = STM32_DMA_STREAM(STM32_SPI_SPI2_RX_DMA_STREAM);
SPID2.dmatx = STM32_DMA_STREAM(STM32_SPI_SPI2_TX_DMA_STREAM);
#endif
SPID2.rxdmamode = STM32_DMA_CR_CHSEL(SPI2_RX_DMA_CHANNEL) |
SPID2.dmarx = NULL;
SPID2.dmatx = NULL;
SPID2.rxdmamode = STM32_DMA_CR_CHSEL(SPI2_RX_DMA_STREAM) |
STM32_DMA_CR_PL(STM32_SPI_SPI2_DMA_PRIORITY) |
STM32_DMA_CR_DIR_P2M |
STM32_DMA_CR_TCIE |
STM32_DMA_CR_DMEIE |
STM32_DMA_CR_TEIE;
SPID2.txdmamode = STM32_DMA_CR_CHSEL(SPI2_TX_DMA_CHANNEL) |
SPID2.txdmamode = STM32_DMA_CR_CHSEL(SPI2_TX_DMA_STREAM) |
STM32_DMA_CR_PL(STM32_SPI_SPI2_DMA_PRIORITY) |
STM32_DMA_CR_DIR_M2P |
STM32_DMA_CR_DMEIE |
@ -245,20 +235,15 @@ void spi_lld_init(void) {
#if STM32_SPI_USE_SPI3
spiObjectInit(&SPID3);
SPID3.spi = SPI3;
#if STM32_DMA_SUPPORTS_DMAMUX
SPID3.dmarx = STM32_DMA_STREAM(STM32_SPI_SPI3_RX_DMA_CHANNEL);
SPID3.dmatx = STM32_DMA_STREAM(STM32_SPI_SPI3_TX_DMA_CHANNEL);
#else
SPID3.dmarx = STM32_DMA_STREAM(STM32_SPI_SPI3_RX_DMA_STREAM);
SPID3.dmatx = STM32_DMA_STREAM(STM32_SPI_SPI3_TX_DMA_STREAM);
#endif
SPID3.rxdmamode = STM32_DMA_CR_CHSEL(SPI3_RX_DMA_CHANNEL) |
SPID3.dmarx = NULL;
SPID3.dmatx = NULL;
SPID3.rxdmamode = STM32_DMA_CR_CHSEL(SPI3_RX_DMA_STREAM) |
STM32_DMA_CR_PL(STM32_SPI_SPI3_DMA_PRIORITY) |
STM32_DMA_CR_DIR_P2M |
STM32_DMA_CR_TCIE |
STM32_DMA_CR_DMEIE |
STM32_DMA_CR_TEIE;
SPID3.txdmamode = STM32_DMA_CR_CHSEL(SPI3_TX_DMA_CHANNEL) |
SPID3.txdmamode = STM32_DMA_CR_CHSEL(SPI3_TX_DMA_STREAM) |
STM32_DMA_CR_PL(STM32_SPI_SPI3_DMA_PRIORITY) |
STM32_DMA_CR_DIR_M2P |
STM32_DMA_CR_DMEIE |
@ -268,20 +253,15 @@ void spi_lld_init(void) {
#if STM32_SPI_USE_SPI4
spiObjectInit(&SPID4);
SPID4.spi = SPI4;
#if STM32_DMA_SUPPORTS_DMAMUX
SPID4.dmarx = STM32_DMA_STREAM(STM32_SPI_SPI4_RX_DMA_CHANNEL);
SPID4.dmatx = STM32_DMA_STREAM(STM32_SPI_SPI4_TX_DMA_CHANNEL);
#else
SPID4.dmarx = STM32_DMA_STREAM(STM32_SPI_SPI4_RX_DMA_STREAM);
SPID4.dmatx = STM32_DMA_STREAM(STM32_SPI_SPI4_TX_DMA_STREAM);
#endif
SPID4.rxdmamode = STM32_DMA_CR_CHSEL(SPI4_RX_DMA_CHANNEL) |
SPID4.dmarx = NULL;
SPID4.dmatx = NULL;
SPID4.rxdmamode = STM32_DMA_CR_CHSEL(SPI4_RX_DMA_STREAM) |
STM32_DMA_CR_PL(STM32_SPI_SPI4_DMA_PRIORITY) |
STM32_DMA_CR_DIR_P2M |
STM32_DMA_CR_TCIE |
STM32_DMA_CR_DMEIE |
STM32_DMA_CR_TEIE;
SPID4.txdmamode = STM32_DMA_CR_CHSEL(SPI4_TX_DMA_CHANNEL) |
SPID4.txdmamode = STM32_DMA_CR_CHSEL(SPI4_TX_DMA_STREAM) |
STM32_DMA_CR_PL(STM32_SPI_SPI4_DMA_PRIORITY) |
STM32_DMA_CR_DIR_M2P |
STM32_DMA_CR_DMEIE |
@ -291,20 +271,15 @@ void spi_lld_init(void) {
#if STM32_SPI_USE_SPI5
spiObjectInit(&SPID5);
SPID5.spi = SPI5;
#if STM32_DMA_SUPPORTS_DMAMUX
SPID5.dmarx = STM32_DMA_STREAM(STM32_SPI_SPI5_RX_DMA_CHANNEL);
SPID5.dmatx = STM32_DMA_STREAM(STM32_SPI_SPI5_TX_DMA_CHANNEL);
#else
SPID5.dmarx = STM32_DMA_STREAM(STM32_SPI_SPI5_RX_DMA_STREAM);
SPID5.dmatx = STM32_DMA_STREAM(STM32_SPI_SPI5_TX_DMA_STREAM);
#endif
SPID5.rxdmamode = STM32_DMA_CR_CHSEL(SPI5_RX_DMA_CHANNEL) |
SPID5.dmarx = NULL;
SPID5.dmatx = NULL;
SPID5.rxdmamode = STM32_DMA_CR_CHSEL(SPI5_RX_DMA_STREAM) |
STM32_DMA_CR_PL(STM32_SPI_SPI5_DMA_PRIORITY) |
STM32_DMA_CR_DIR_P2M |
STM32_DMA_CR_TCIE |
STM32_DMA_CR_DMEIE |
STM32_DMA_CR_TEIE;
SPID5.txdmamode = STM32_DMA_CR_CHSEL(SPI5_TX_DMA_CHANNEL) |
SPID5.txdmamode = STM32_DMA_CR_CHSEL(SPI5_TX_DMA_STREAM) |
STM32_DMA_CR_PL(STM32_SPI_SPI5_DMA_PRIORITY) |
STM32_DMA_CR_DIR_M2P |
STM32_DMA_CR_DMEIE |
@ -314,20 +289,15 @@ void spi_lld_init(void) {
#if STM32_SPI_USE_SPI6
spiObjectInit(&SPID6);
SPID6.spi = SPI6;
#if STM32_DMA_SUPPORTS_DMAMUX
SPID6.dmarx = STM32_DMA_STREAM(STM32_SPI_SPI6_RX_DMA_CHANNEL);
SPID6.dmatx = STM32_DMA_STREAM(STM32_SPI_SPI6_TX_DMA_CHANNEL);
#else
SPID6.dmarx = STM32_DMA_STREAM(STM32_SPI_SPI6_RX_DMA_STREAM);
SPID6.dmatx = STM32_DMA_STREAM(STM32_SPI_SPI6_TX_DMA_STREAM);
#endif
SPID6.rxdmamode = STM32_DMA_CR_CHSEL(SPI6_RX_DMA_CHANNEL) |
SPID6.dmarx = NULL;
SPID6.dmatx = NULL;
SPID6.rxdmamode = STM32_DMA_CR_CHSEL(SPI6_RX_DMA_STREAM) |
STM32_DMA_CR_PL(STM32_SPI_SPI6_DMA_PRIORITY) |
STM32_DMA_CR_DIR_P2M |
STM32_DMA_CR_TCIE |
STM32_DMA_CR_DMEIE |
STM32_DMA_CR_TEIE;
SPID6.txdmamode = STM32_DMA_CR_CHSEL(SPI6_TX_DMA_CHANNEL) |
SPID6.txdmamode = STM32_DMA_CR_CHSEL(SPI6_TX_DMA_STREAM) |
STM32_DMA_CR_PL(STM32_SPI_SPI6_DMA_PRIORITY) |
STM32_DMA_CR_DIR_M2P |
STM32_DMA_CR_DMEIE |
@ -349,17 +319,16 @@ void spi_lld_start(SPIDriver *spip) {
if (spip->state == SPI_STOP) {
#if STM32_SPI_USE_SPI1
if (&SPID1 == spip) {
bool b;
b = dmaStreamAllocate(spip->dmarx,
spip->dmarx = dmaStreamAllocI(STM32_SPI_SPI1_RX_DMA_STREAM,
STM32_SPI_SPI1_IRQ_PRIORITY,
(stm32_dmaisr_t)spi_lld_serve_rx_interrupt,
(void *)spip);
osalDbgAssert(!b, "stream already allocated");
b = dmaStreamAllocate(spip->dmatx,
osalDbgAssert(spip->dmarx != NULL, "unable to allocate stream");
spip->dmatx = dmaStreamAllocI(STM32_SPI_SPI1_TX_DMA_STREAM,
STM32_SPI_SPI1_IRQ_PRIORITY,
(stm32_dmaisr_t)spi_lld_serve_tx_interrupt,
(void *)spip);
osalDbgAssert(!b, "stream already allocated");
osalDbgAssert(spip->dmatx != NULL, "unable to allocate stream");
rccEnableSPI1(true);
#if STM32_DMA_SUPPORTS_DMAMUX
dmaSetRequestSource(spip->dmarx, STM32_DMAMUX1_SPI1_RX);
@ -369,17 +338,16 @@ void spi_lld_start(SPIDriver *spip) {
#endif
#if STM32_SPI_USE_SPI2
if (&SPID2 == spip) {
bool b;
b = dmaStreamAllocate(spip->dmarx,
spip->dmarx = dmaStreamAllocI(STM32_SPI_SPI2_RX_DMA_STREAM,
STM32_SPI_SPI2_IRQ_PRIORITY,
(stm32_dmaisr_t)spi_lld_serve_rx_interrupt,
(void *)spip);
osalDbgAssert(!b, "stream already allocated");
b = dmaStreamAllocate(spip->dmatx,
osalDbgAssert(spip->dmarx != NULL, "unable to allocate stream");
spip->dmatx = dmaStreamAllocI(STM32_SPI_SPI2_TX_DMA_STREAM,
STM32_SPI_SPI2_IRQ_PRIORITY,
(stm32_dmaisr_t)spi_lld_serve_tx_interrupt,
(void *)spip);
osalDbgAssert(!b, "stream already allocated");
osalDbgAssert(spip->dmatx != NULL, "unable to allocate stream");
rccEnableSPI2(true);
#if STM32_DMA_SUPPORTS_DMAMUX
dmaSetRequestSource(spip->dmarx, STM32_DMAMUX1_SPI2_RX);
@ -389,17 +357,16 @@ void spi_lld_start(SPIDriver *spip) {
#endif
#if STM32_SPI_USE_SPI3
if (&SPID3 == spip) {
bool b;
b = dmaStreamAllocate(spip->dmarx,
spip->dmarx = dmaStreamAllocI(STM32_SPI_SPI3_RX_DMA_STREAM,
STM32_SPI_SPI3_IRQ_PRIORITY,
(stm32_dmaisr_t)spi_lld_serve_rx_interrupt,
(void *)spip);
osalDbgAssert(!b, "stream already allocated");
b = dmaStreamAllocate(spip->dmatx,
osalDbgAssert(spip->dmarx != NULL, "unable to allocate stream");
spip->dmatx = dmaStreamAllocI(STM32_SPI_SPI3_TX_DMA_STREAM,
STM32_SPI_SPI3_IRQ_PRIORITY,
(stm32_dmaisr_t)spi_lld_serve_tx_interrupt,
(void *)spip);
osalDbgAssert(!b, "stream already allocated");
osalDbgAssert(spip->dmatx != NULL, "unable to allocate stream");
rccEnableSPI3(true);
#if STM32_DMA_SUPPORTS_DMAMUX
dmaSetRequestSource(spip->dmarx, STM32_DMAMUX1_SPI3_RX);
@ -409,17 +376,16 @@ void spi_lld_start(SPIDriver *spip) {
#endif
#if STM32_SPI_USE_SPI4
if (&SPID4 == spip) {
bool b;
b = dmaStreamAllocate(spip->dmarx,
spip->dmarx = dmaStreamAllocI(STM32_SPI_SPI4_RX_DMA_STREAM,
STM32_SPI_SPI4_IRQ_PRIORITY,
(stm32_dmaisr_t)spi_lld_serve_rx_interrupt,
(void *)spip);
osalDbgAssert(!b, "stream already allocated");
b = dmaStreamAllocate(spip->dmatx,
osalDbgAssert(spip->dmarx != NULL, "unable to allocate stream");
spip->dmatx = dmaStreamAllocI(STM32_SPI_SPI4_TX_DMA_STREAM,
STM32_SPI_SPI4_IRQ_PRIORITY,
(stm32_dmaisr_t)spi_lld_serve_tx_interrupt,
(void *)spip);
osalDbgAssert(!b, "stream already allocated");
osalDbgAssert(spip->dmatx != NULL, "unable to allocate stream");
rccEnableSPI4(true);
#if STM32_DMA_SUPPORTS_DMAMUX
dmaSetRequestSource(spip->dmarx, STM32_DMAMUX1_SPI4_RX);
@ -429,17 +395,16 @@ void spi_lld_start(SPIDriver *spip) {
#endif
#if STM32_SPI_USE_SPI5
if (&SPID5 == spip) {
bool b;
b = dmaStreamAllocate(spip->dmarx,
spip->dmarx = dmaStreamAllocI(STM32_SPI_SPI5_RX_DMA_STREAM,
STM32_SPI_SPI5_IRQ_PRIORITY,
(stm32_dmaisr_t)spi_lld_serve_rx_interrupt,
(void *)spip);
osalDbgAssert(!b, "stream already allocated");
b = dmaStreamAllocate(spip->dmatx,
osalDbgAssert(spip->dmarx != NULL, "unable to allocate stream");
spip->dmatx = dmaStreamAllocI(STM32_SPI_SPI5_TX_DMA_STREAM,
STM32_SPI_SPI5_IRQ_PRIORITY,
(stm32_dmaisr_t)spi_lld_serve_tx_interrupt,
(void *)spip);
osalDbgAssert(!b, "stream already allocated");
osalDbgAssert(spip->dmatx != NULL, "unable to allocate stream");
rccEnableSPI5(true);
#if STM32_DMA_SUPPORTS_DMAMUX
dmaSetRequestSource(spip->dmarx, STM32_DMAMUX1_SPI5_RX);
@ -449,17 +414,16 @@ void spi_lld_start(SPIDriver *spip) {
#endif
#if STM32_SPI_USE_SPI6
if (&SPID6 == spip) {
bool b;
b = dmaStreamAllocate(spip->dmarx,
spip->dmarx = dmaStreamAllocI(STM32_SPI_SPI6_RX_DMA_STREAM,
STM32_SPI_SPI6_IRQ_PRIORITY,
(stm32_dmaisr_t)spi_lld_serve_rx_interrupt,
(void *)spip);
osalDbgAssert(!b, "stream already allocated");
b = dmaStreamAllocate(spip->dmatx,
osalDbgAssert(spip->dmarx != NULL, "unable to allocate stream");
spip->dmatx = dmaStreamAllocI(STM32_SPI_SPI6_TX_DMA_STREAM,
STM32_SPI_SPI6_IRQ_PRIORITY,
(stm32_dmaisr_t)spi_lld_serve_tx_interrupt,
(void *)spip);
osalDbgAssert(!b, "stream already allocated");
osalDbgAssert(spip->dmatx != NULL, "unable to allocate stream");
rccEnableSPI6(true);
#if STM32_DMA_SUPPORTS_DMAMUX
dmaSetRequestSource(spip->dmarx, STM32_DMAMUX1_SPI6_RX);
@ -523,8 +487,10 @@ void spi_lld_stop(SPIDriver *spip) {
spip->spi->CR1 &= ~SPI_CR1_SPE;
spip->spi->CR1 = 0;
spip->spi->CR2 = 0;
dmaStreamRelease(spip->dmarx);
dmaStreamRelease(spip->dmatx);
dmaStreamFreeI(spip->dmarx);
dmaStreamFreeI(spip->dmatx);
spip->dmarx = NULL;
spip->dmatx = NULL;
#if STM32_SPI_USE_SPI1
if (&SPID1 == spip)

159
os/hal/ports/STM32/LLD/SPIv2/hal_spi_lld.h
View File

@ -301,102 +301,6 @@
#error "Invalid DMA priority assigned to SPI6"
#endif
/* The following checks are only required when there is a DMA able to
reassign streams to different channels.*/
#if STM32_ADVANCED_DMA
/* Devices with DMAMUX require a different kind of check.*/
#if STM32_DMA_SUPPORTS_DMAMUX
/* Check on the presence of the DMA channel settings in mcuconf.h.*/
#if STM32_SPI_USE_SPI1 && (!defined(STM32_SPI_SPI1_RX_DMA_CHANNEL) || \
!defined(STM32_SPI_SPI1_TX_DMA_CHANNEL))
#error "SPI1 DMA channels not defined"
#endif
#if STM32_SPI_USE_SPI2 && (!defined(STM32_SPI_SPI2_RX_DMA_CHANNEL) || \
!defined(STM32_SPI_SPI2_TX_DMA_CHANNEL))
#error "SPI2 DMA streams not defined"
#endif
#if STM32_SPI_USE_SPI3 && (!defined(STM32_SPI_SPI3_RX_DMA_CHANNEL) || \
!defined(STM32_SPI_SPI3_TX_DMA_CHANNEL))
#error "SPI3 DMA streams not defined"
#endif
#if STM32_SPI_USE_SPI4 && (!defined(STM32_SPI_SPI4_RX_DMA_CHANNEL) || \
!defined(STM32_SPI_SPI4_TX_DMA_CHANNEL))
#error "SPI4 DMA streams not defined"
#endif
#if STM32_SPI_USE_SPI5 && (!defined(STM32_SPI_SPI5_RX_DMA_CHANNEL) || \
!defined(STM32_SPI_SPI5_TX_DMA_CHANNEL))
#error "SPI5 DMA streams not defined"
#endif
#if STM32_SPI_USE_SPI6 && (!defined(STM32_SPI_SPI6_RX_DMA_CHANNEL) || \
!defined(STM32_SPI_SPI6_TX_DMA_CHANNEL))
#error "SPI6 DMA streams not defined"
#endif
/* Check on the validity of the assigned DMA channels.*/
#if STM32_SPI_USE_SPI1 && \
!STM32_DMA_IS_VALID_CHANNEL(STM32_SPI_SPI1_TX_DMA_CHANNEL)
#error "Invalid DMA channel assigned to SPI1 TX"
#endif
#if STM32_SPI_USE_SPI2 && \
!STM32_DMA_IS_VALID_CHANNEL(STM32_SPI_SPI2_RX_DMA_CHANNEL)
#error "Invalid DMA channel assigned to SPI2 RX"
#endif
#if STM32_SPI_USE_SPI2 && \
!STM32_DMA_IS_VALID_CHANNEL(STM32_SPI_SPI2_TX_DMA_CHANNEL)
#error "Invalid DMA channel assigned to SPI2 TX"
#endif
#if STM32_SPI_USE_SPI3 && \
!STM32_DMA_IS_VALID_CHANNEL(STM32_SPI_SPI3_RX_DMA_CHANNEL)
#error "Invalid DMA channel assigned to SPI3 RX"
#endif
#if STM32_SPI_USE_SPI3 && \
!STM32_DMA_IS_VALID_CHANNEL(STM32_SPI_SPI3_TX_DMA_CHANNEL)
#error "Invalid DMA channel assigned to SPI3 TX"
#endif
#if STM32_SPI_USE_SPI4 && \
!STM32_DMA_IS_VALID_CHANNEL(STM32_SPI_SPI4_RX_DMA_CHANNEL)
#error "Invalid DMA channel assigned to SPI4 RX"
#endif
#if STM32_SPI_USE_SPI4 && \
!STM32_DMA_IS_VALID_CHANNEL(STM32_SPI_SPI4_TX_DMA_CHANNEL)
#error "Invalid DMA channel assigned to SPI4 TX"
#endif
#if STM32_SPI_USE_SPI5 && \
!STM32_DMA_IS_VALID_CHANNEL(STM32_SPI_SPI5_RX_DMA_CHANNEL)
#error "Invalid DMA channel assigned to SPI5 RX"
#endif
#if STM32_SPI_USE_SPI5 && \
!STM32_DMA_IS_VALID_CHANNEL(STM32_SPI_SPI5_TX_DMA_CHANNEL)
#error "Invalid DMA channel assigned to SPI5 TX"
#endif
#if STM32_SPI_USE_SPI6 && \
!STM32_DMA_IS_VALID_CHANNEL(STM32_SPI_SPI6_RX_DMA_CHANNEL)
#error "Invalid DMA channel assigned to SPI6 RX"
#endif
#if STM32_SPI_USE_SPI6 && \
!STM32_DMA_IS_VALID_CHANNEL(STM32_SPI_SPI6_TX_DMA_CHANNEL)
#error "Invalid DMA channel assigned to SPI6 TX"
#endif
#else /* !STM32_DMA_SUPPORTS_DMAMUX */
/* Check on the presence of the DMA streams settings in mcuconf.h.*/
#if STM32_SPI_USE_SPI1 && (!defined(STM32_SPI_SPI1_RX_DMA_STREAM) || \
!defined(STM32_SPI_SPI1_TX_DMA_STREAM))
@ -428,6 +332,65 @@
#error "SPI6 DMA streams not defined"
#endif
/* Check on the validity of the assigned DMA channels.*/
#if STM32_SPI_USE_SPI1 && \
!STM32_DMA_IS_VALID_STREAM(STM32_SPI_SPI1_TX_DMA_STREAM)
#error "Invalid DMA channel assigned to SPI1 TX"
#endif
#if STM32_SPI_USE_SPI2 && \
!STM32_DMA_IS_VALID_STREAM(STM32_SPI_SPI2_RX_DMA_STREAM)
#error "Invalid DMA channel assigned to SPI2 RX"
#endif
#if STM32_SPI_USE_SPI2 && \
!STM32_DMA_IS_VALID_STREAM(STM32_SPI_SPI2_TX_DMA_STREAM)
#error "Invalid DMA channel assigned to SPI2 TX"
#endif
#if STM32_SPI_USE_SPI3 && \
!STM32_DMA_IS_VALID_STREAM(STM32_SPI_SPI3_RX_DMA_STREAM)
#error "Invalid DMA channel assigned to SPI3 RX"
#endif
#if STM32_SPI_USE_SPI3 && \
!STM32_DMA_IS_VALID_STREAM(STM32_SPI_SPI3_TX_DMA_STREAM)
#error "Invalid DMA channel assigned to SPI3 TX"
#endif
#if STM32_SPI_USE_SPI4 && \
!STM32_DMA_IS_VALID_STREAM(STM32_SPI_SPI4_RX_DMA_STREAM)
#error "Invalid DMA channel assigned to SPI4 RX"
#endif
#if STM32_SPI_USE_SPI4 && \
!STM32_DMA_IS_VALID_STREAM(STM32_SPI_SPI4_TX_DMA_STREAM)
#error "Invalid DMA channel assigned to SPI4 TX"
#endif
#if STM32_SPI_USE_SPI5 && \
!STM32_DMA_IS_VALID_STREAM(STM32_SPI_SPI5_RX_DMA_STREAM)
#error "Invalid DMA channel assigned to SPI5 RX"
#endif
#if STM32_SPI_USE_SPI5 && \
!STM32_DMA_IS_VALID_STREAM(STM32_SPI_SPI5_TX_DMA_STREAM)
#error "Invalid DMA channel assigned to SPI5 TX"
#endif
#if STM32_SPI_USE_SPI6 && \
!STM32_DMA_IS_VALID_STREAM(STM32_SPI_SPI6_RX_DMA_STREAM)
#error "Invalid DMA channel assigned to SPI6 RX"
#endif
#if STM32_SPI_USE_SPI6 && \
!STM32_DMA_IS_VALID_STREAM(STM32_SPI_SPI6_TX_DMA_STREAM)
#error "Invalid DMA channel assigned to SPI6 TX"
#endif
/* Devices without DMAMUX require an additional check.*/
#if STM32_ADVANCED_DMA && !STM32_DMA_SUPPORTS_DMAMUX
/* Check on the validity of the assigned DMA channels.*/
#if STM32_SPI_USE_SPI1 && \
!STM32_DMA_IS_VALID_ID(STM32_SPI_SPI1_RX_DMA_STREAM, STM32_SPI1_RX_DMA_MSK)
@ -489,9 +452,7 @@
#error "invalid DMA stream associated to SPI6 TX"
#endif
#endif /* !STM32_DMA_SUPPORTS_DMAMUX */
#endif /* STM32_ADVANCED_DMA */
#endif /* STM32_ADVANCED_DMA && !STM32_DMA_SUPPORTS_DMAMUX */
#if !defined(STM32_DMA_REQUIRED)
#define STM32_DMA_REQUIRED

4
os/hal/ports/STM32/LLD/SPIv3/driver.mk
View File

@ -1,12 +1,8 @@
ifeq ($(USE_SMART_BUILD),yes)
ifneq ($(findstring HAL_USE_I2S TRUE,$(HALCONF)),)
PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/SPIv3/hal_i2s_lld.c
endif
ifneq ($(findstring HAL_USE_SPI TRUE,$(HALCONF)),)
PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/SPIv3/hal_spi_lld.c
endif
else
PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/SPIv3/hal_i2s_lld.c
PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/SPIv3/hal_spi_lld.c
endif

577
os/hal/ports/STM32/LLD/SPIv3/hal_i2s_lld.c
View File

@ -1,577 +0,0 @@
/*
ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
/**
* @file SPIv2/hal_i2s_lld.c
* @brief STM32 I2S subsystem low level driver source.
*
* @addtogroup I2S
* @{
*/
#include "hal.h"
#if HAL_USE_I2S || defined(__DOXYGEN__)
/*===========================================================================*/
/* Driver local definitions. */
/*===========================================================================*/
#define I2S1_RX_DMA_CHANNEL \
STM32_DMA_GETCHANNEL(STM32_I2S_SPI1_RX_DMA_STREAM, \
STM32_SPI1_RX_DMA_CHN)
#define I2S1_TX_DMA_CHANNEL \
STM32_DMA_GETCHANNEL(STM32_I2S_SPI1_TX_DMA_STREAM, \
STM32_SPI1_TX_DMA_CHN)
#define I2S2_RX_DMA_CHANNEL \
STM32_DMA_GETCHANNEL(STM32_I2S_SPI2_RX_DMA_STREAM, \
STM32_SPI2_RX_DMA_CHN)
#define I2S2_TX_DMA_CHANNEL \
STM32_DMA_GETCHANNEL(STM32_I2S_SPI2_TX_DMA_STREAM, \
STM32_SPI2_TX_DMA_CHN)
#define I2S3_RX_DMA_CHANNEL \
STM32_DMA_GETCHANNEL(STM32_I2S_SPI3_RX_DMA_STREAM, \
STM32_SPI3_RX_DMA_CHN)
#define I2S3_TX_DMA_CHANNEL \
STM32_DMA_GETCHANNEL(STM32_I2S_SPI3_TX_DMA_STREAM, \
STM32_SPI3_TX_DMA_CHN)
/*
* Static I2S settings for I2S1.
*/
#if !STM32_I2S_IS_MASTER(STM32_I2S_SPI1_MODE)
#if STM32_I2S_TX_ENABLED(STM32_I2S_SPI1_MODE)
#define STM32_I2S1_CFGR_CFG 0
#endif
#if STM32_I2S_RX_ENABLED(STM32_I2S_SPI1_MODE)
#define STM32_I2S1_CFGR_CFG SPI_I2SCFGR_I2SCFG_0
#endif
#else /* !STM32_I2S_IS_MASTER(STM32_I2S_SPI1_MODE) */
#if STM32_I2S_TX_ENABLED(STM32_I2S_SPI1_MODE)
#define STM32_I2S1_CFGR_CFG SPI_I2SCFGR_I2SCFG_1
#endif
#if STM32_I2S_RX_ENABLED(STM32_I2S_SPI1_MODE)
#define STM32_I2S1_CFGR_CFG (SPI_I2SCFGR_I2SCFG_1 | \
SPI_I2SCFGR_I2SCFG_0)
#endif
#endif /* !STM32_I2S_IS_MASTER(STM32_I2S_SPI1_MODE) */
/*
* Static I2S settings for I2S2.
*/
#if !STM32_I2S_IS_MASTER(STM32_I2S_SPI2_MODE)
#if STM32_I2S_TX_ENABLED(STM32_I2S_SPI2_MODE)
#define STM32_I2S2_CFGR_CFG 0
#endif
#if STM32_I2S_RX_ENABLED(STM32_I2S_SPI2_MODE)
#define STM32_I2S2_CFGR_CFG SPI_I2SCFGR_I2SCFG_0
#endif
#else /* !STM32_I2S_IS_MASTER(STM32_I2S_SPI2_MODE) */
#if STM32_I2S_TX_ENABLED(STM32_I2S_SPI2_MODE)
#define STM32_I2S2_CFGR_CFG SPI_I2SCFGR_I2SCFG_1
#endif
#if STM32_I2S_RX_ENABLED(STM32_I2S_SPI2_MODE)
#define STM32_I2S2_CFGR_CFG (SPI_I2SCFGR_I2SCFG_1 | \
SPI_I2SCFGR_I2SCFG_0)
#endif
#endif /* !STM32_I2S_IS_MASTER(STM32_I2S_SPI2_MODE) */
/*
* Static I2S settings for I2S3.
*/
#if !STM32_I2S_IS_MASTER(STM32_I2S_SPI3_MODE)
#if STM32_I2S_TX_ENABLED(STM32_I2S_SPI3_MODE)
#define STM32_I2S3_CFGR_CFG 0
#endif
#if STM32_I2S_RX_ENABLED(STM32_I2S_SPI3_MODE)
#define STM32_I2S3_CFGR_CFG SPI_I2SCFGR_I2SCFG_0
#endif
#else /* !STM32_I2S_IS_MASTER(STM32_I2S_SPI3_MODE) */
#if STM32_I2S_TX_ENABLED(STM32_I2S_SPI3_MODE)
#define STM32_I2S3_CFGR_CFG SPI_I2SCFGR_I2SCFG_1
#endif
#if STM32_I2S_RX_ENABLED(STM32_I2S_SPI3_MODE)
#define STM32_I2S3_CFGR_CFG (SPI_I2SCFGR_I2SCFG_1 | \
SPI_I2SCFGR_I2SCFG_0)
#endif
#endif /* !STM32_I2S_IS_MASTER(STM32_I2S_SPI3_MODE) */
/*===========================================================================*/
/* Driver exported variables. */
/*===========================================================================*/
/** @brief I2S1 driver identifier.*/
#if STM32_I2S_USE_SPI1 || defined(__DOXYGEN__)
I2SDriver I2SD1;
#endif
/** @brief I2S2 driver identifier.*/
#if STM32_I2S_USE_SPI2 || defined(__DOXYGEN__)
I2SDriver I2SD2;
#endif
/** @brief I2S3 driver identifier.*/
#if STM32_I2S_USE_SPI3 || defined(__DOXYGEN__)
I2SDriver I2SD3;
#endif
/*===========================================================================*/
/* Driver local variables and types. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver local functions. */
/*===========================================================================*/
#if STM32_I2S_RX_ENABLED(STM32_I2S_SPI1_MODE) || \
STM32_I2S_RX_ENABLED(STM32_I2S_SPI2_MODE) || \
STM32_I2S_RX_ENABLED(STM32_I2S_SPI3_MODE) || defined(__DOXYGEN__)
/**
* @brief Shared end-of-rx service routine.
*
* @param[in] i2sp pointer to the @p I2SDriver object
* @param[in] flags pre-shifted content of the ISR register
*/
static void i2s_lld_serve_rx_interrupt(I2SDriver *i2sp, uint32_t flags) {
(void)i2sp;
/* DMA errors handling.*/
#if defined(STM32_I2S_DMA_ERROR_HOOK)
if ((flags & (STM32_DMA_ISR_TEIF | STM32_DMA_ISR_DMEIF)) != 0) {
STM32_I2S_DMA_ERROR_HOOK(i2sp);
}
#endif
/* Callbacks handling, note it is portable code defined in the high
level driver.*/
if ((flags & STM32_DMA_ISR_TCIF) != 0) {
/* Transfer complete processing.*/
_i2s_isr_full_code(i2sp);
}
else if ((flags & STM32_DMA_ISR_HTIF) != 0) {
/* Half transfer processing.*/
_i2s_isr_half_code(i2sp);
}
}
#endif
#if STM32_I2S_TX_ENABLED(STM32_I2S_SPI1_MODE) || \
STM32_I2S_TX_ENABLED(STM32_I2S_SPI2_MODE) || \
STM32_I2S_TX_ENABLED(STM32_I2S_SPI3_MODE) || defined(__DOXYGEN__)
/**
* @brief Shared end-of-tx service routine.
*
* @param[in] i2sp pointer to the @p I2SDriver object
* @param[in] flags pre-shifted content of the ISR register
*/
static void i2s_lld_serve_tx_interrupt(I2SDriver *i2sp, uint32_t flags) {
(void)i2sp;
/* DMA errors handling.*/
#if defined(STM32_I2S_DMA_ERROR_HOOK)
if ((flags & (STM32_DMA_ISR_TEIF | STM32_DMA_ISR_DMEIF)) != 0) {
STM32_I2S_DMA_ERROR_HOOK(i2sp);
}
#endif
/* Callbacks handling, note it is portable code defined in the high
level driver.*/
if ((flags & STM32_DMA_ISR_TCIF) != 0) {
/* Transfer complete processing.*/
_i2s_isr_code_half2(i2sp);
}
else if ((flags & STM32_DMA_ISR_HTIF) != 0) {
/* Half transfer processing.*/
_i2s_isr_code_half1(i2sp);
}
}
#endif
/*===========================================================================*/
/* Driver interrupt handlers. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver exported functions. */
/*===========================================================================*/
/**
* @brief Low level I2S driver initialization.
*
* @notapi
*/
void i2s_lld_init(void) {
#if STM32_I2S_USE_SPI1
i2sObjectInit(&I2SD1);
I2SD1.spi = SPI1;
I2SD1.cfg = STM32_I2S1_CFGR_CFG;
#if STM32_I2S_RX_ENABLED(STM32_I2S_SPI1_MODE)
I2SD1.dmarx = STM32_DMA_STREAM(STM32_I2S_SPI1_RX_DMA_STREAM);
I2SD1.rxdmamode = STM32_DMA_CR_CHSEL(I2S1_RX_DMA_CHANNEL) |
STM32_DMA_CR_PL(STM32_I2S_SPI1_DMA_PRIORITY) |
STM32_DMA_CR_PSIZE_HWORD |
STM32_DMA_CR_MSIZE_HWORD |
STM32_DMA_CR_DIR_P2M |
STM32_DMA_CR_MINC |
STM32_DMA_CR_CIRC |
STM32_DMA_CR_HTIE |
STM32_DMA_CR_TCIE |
STM32_DMA_CR_DMEIE |
STM32_DMA_CR_TEIE;
#else
I2SD1.dmarx = NULL;
I2SD1.rxdmamode = 0;
#endif
#if STM32_I2S_TX_ENABLED(STM32_I2S_SPI1_MODE)
I2SD1.dmatx = STM32_DMA_STREAM(STM32_I2S_SPI1_TX_DMA_STREAM);
I2SD1.txdmamode = STM32_DMA_CR_CHSEL(I2S1_TX_DMA_CHANNEL) |
STM32_DMA_CR_PL(STM32_I2S_SPI1_DMA_PRIORITY) |
STM32_DMA_CR_PSIZE_HWORD |
STM32_DMA_CR_MSIZE_HWORD |
STM32_DMA_CR_DIR_M2P |
STM32_DMA_CR_MINC |
STM32_DMA_CR_CIRC |
STM32_DMA_CR_HTIE |
STM32_DMA_CR_TCIE |
STM32_DMA_CR_DMEIE |
STM32_DMA_CR_TEIE;
#else
I2SD1.dmatx = NULL;
I2SD1.txdmamode = 0;
#endif
#endif
#if STM32_I2S_USE_SPI2
i2sObjectInit(&I2SD2);
I2SD2.spi = SPI2;
I2SD2.cfg = STM32_I2S2_CFGR_CFG;
#if STM32_I2S_RX_ENABLED(STM32_I2S_SPI2_MODE)
I2SD2.dmarx = STM32_DMA_STREAM(STM32_I2S_SPI2_RX_DMA_STREAM);
I2SD2.rxdmamode = STM32_DMA_CR_CHSEL(I2S2_RX_DMA_CHANNEL) |
STM32_DMA_CR_PL(STM32_I2S_SPI2_DMA_PRIORITY) |
STM32_DMA_CR_PSIZE_HWORD |
STM32_DMA_CR_MSIZE_HWORD |
STM32_DMA_CR_DIR_P2M |
STM32_DMA_CR_MINC |
STM32_DMA_CR_CIRC |
STM32_DMA_CR_HTIE |
STM32_DMA_CR_TCIE |
STM32_DMA_CR_DMEIE |
STM32_DMA_CR_TEIE;
#else
I2SD2.dmarx = NULL;
I2SD2.rxdmamode = 0;
#endif
#if STM32_I2S_TX_ENABLED(STM32_I2S_SPI2_MODE)
I2SD2.dmatx = STM32_DMA_STREAM(STM32_I2S_SPI2_TX_DMA_STREAM);
I2SD2.txdmamode = STM32_DMA_CR_CHSEL(I2S2_TX_DMA_CHANNEL) |
STM32_DMA_CR_PL(STM32_I2S_SPI2_DMA_PRIORITY) |
STM32_DMA_CR_PSIZE_HWORD |
STM32_DMA_CR_MSIZE_HWORD |
STM32_DMA_CR_DIR_M2P |
STM32_DMA_CR_MINC |
STM32_DMA_CR_CIRC |
STM32_DMA_CR_HTIE |
STM32_DMA_CR_TCIE |
STM32_DMA_CR_DMEIE |
STM32_DMA_CR_TEIE;
#else
I2SD2.dmatx = NULL;
I2SD2.txdmamode = 0;
#endif
#endif
#if STM32_I2S_USE_SPI3
i2sObjectInit(&I2SD3);
I2SD3.spi = SPI3;
I2SD3.cfg = STM32_I2S3_CFGR_CFG;
#if STM32_I2S_RX_ENABLED(STM32_I2S_SPI3_MODE)
I2SD3.dmarx = STM32_DMA_STREAM(STM32_I2S_SPI3_RX_DMA_STREAM);
I2SD3.rxdmamode = STM32_DMA_CR_CHSEL(I2S3_RX_DMA_CHANNEL) |
STM32_DMA_CR_PL(STM32_I2S_SPI3_DMA_PRIORITY) |
STM32_DMA_CR_PSIZE_HWORD |
STM32_DMA_CR_MSIZE_HWORD |
STM32_DMA_CR_DIR_P2M |
STM32_DMA_CR_MINC |
STM32_DMA_CR_CIRC |
STM32_DMA_CR_HTIE |
STM32_DMA_CR_TCIE |
STM32_DMA_CR_DMEIE |
STM32_DMA_CR_TEIE;
#else
I2SD3.dmarx = NULL;
I2SD3.rxdmamode = 0;
#endif
#if STM32_I2S_TX_ENABLED(STM32_I2S_SPI3_MODE)
I2SD3.dmatx = STM32_DMA_STREAM(STM32_I2S_SPI3_TX_DMA_STREAM);
I2SD3.txdmamode = STM32_DMA_CR_CHSEL(I2S3_TX_DMA_CHANNEL) |
STM32_DMA_CR_PL(STM32_I2S_SPI3_DMA_PRIORITY) |
STM32_DMA_CR_PSIZE_HWORD |
STM32_DMA_CR_MSIZE_HWORD |
STM32_DMA_CR_DIR_M2P |
STM32_DMA_CR_MINC |
STM32_DMA_CR_CIRC |
STM32_DMA_CR_HTIE |
STM32_DMA_CR_TCIE |
STM32_DMA_CR_DMEIE |
STM32_DMA_CR_TEIE;
#else
I2SD3.dmatx = NULL;
I2SD3.txdmamode = 0;
#endif
#endif
}
/**
* @brief Configures and activates the I2S peripheral.
*
* @param[in] i2sp pointer to the @p I2SDriver object
*
* @notapi
*/
void i2s_lld_start(I2SDriver *i2sp) {
/* If in stopped state then enables the SPI and DMA clocks.*/
if (i2sp->state == I2S_STOP) {
#if STM32_I2S_USE_SPI1
if (&I2SD1 == i2sp) {
bool b;
/* Enabling I2S unit clock.*/
rccEnableSPI1(true);
#if STM32_I2S_RX_ENABLED(STM32_I2S_SPI1_MODE)
b = dmaStreamAllocate(i2sp->dmarx,
STM32_I2S_SPI1_IRQ_PRIORITY,
(stm32_dmaisr_t)i2s_lld_serve_rx_interrupt,
(void *)i2sp);
osalDbgAssert(!b, "stream already allocated");
/* CRs settings are done here because those never changes until
the driver is stopped.*/
i2sp->spi->CR1 = 0;
i2sp->spi->CR2 = SPI_CR2_RXDMAEN;
#endif
#if STM32_I2S_TX_ENABLED(STM32_I2S_SPI1_MODE)
b = dmaStreamAllocate(i2sp->dmatx,
STM32_I2S_SPI1_IRQ_PRIORITY,
(stm32_dmaisr_t)i2s_lld_serve_tx_interrupt,
(void *)i2sp);
osalDbgAssert(!b, "stream already allocated");
/* CRs settings are done here because those never changes until
the driver is stopped.*/
i2sp->spi->CR1 = 0;
i2sp->spi->CR2 = SPI_CR2_TXDMAEN;
#endif
}
#endif
#if STM32_I2S_USE_SPI2
if (&I2SD2 == i2sp) {
bool b;
/* Enabling I2S unit clock.*/
rccEnableSPI2(true);
#if STM32_I2S_RX_ENABLED(STM32_I2S_SPI2_MODE)
b = dmaStreamAllocate(i2sp->dmarx,
STM32_I2S_SPI2_IRQ_PRIORITY,
(stm32_dmaisr_t)i2s_lld_serve_rx_interrupt,
(void *)i2sp);
osalDbgAssert(!b, "stream already allocated");
/* CRs settings are done here because those never changes until
the driver is stopped.*/
i2sp->spi->CR1 = 0;
i2sp->spi->CR2 = SPI_CR2_RXDMAEN;
#endif
#if STM32_I2S_TX_ENABLED(STM32_I2S_SPI2_MODE)
b = dmaStreamAllocate(i2sp->dmatx,
STM32_I2S_SPI2_IRQ_PRIORITY,
(stm32_dmaisr_t)i2s_lld_serve_tx_interrupt,
(void *)i2sp);
osalDbgAssert(!b, "stream already allocated");
/* CRs settings are done here because those never changes until
the driver is stopped.*/
i2sp->spi->CR1 = 0;
i2sp->spi->CR2 = SPI_CR2_TXDMAEN;
#endif
}
#endif
#if STM32_I2S_USE_SPI3
if (&I2SD3 == i2sp) {
bool b;
/* Enabling I2S unit clock.*/
rccEnableSPI3(true);
#if STM32_I2S_RX_ENABLED(STM32_I2S_SPI3_MODE)
b = dmaStreamAllocate(i2sp->dmarx,
STM32_I2S_SPI3_IRQ_PRIORITY,
(stm32_dmaisr_t)i2s_lld_serve_rx_interrupt,
(void *)i2sp);
osalDbgAssert(!b, "stream already allocated");
/* CRs settings are done here because those never changes until
the driver is stopped.*/
i2sp->spi->CR1 = 0;
i2sp->spi->CR2 = SPI_CR2_RXDMAEN;
#endif
#if STM32_I2S_TX_ENABLED(STM32_I2S_SPI3_MODE)
b = dmaStreamAllocate(i2sp->dmatx,
STM32_I2S_SPI3_IRQ_PRIORITY,
(stm32_dmaisr_t)i2s_lld_serve_tx_interrupt,
(void *)i2sp);
osalDbgAssert(!b, "stream already allocated");
/* CRs settings are done here because those never changes until
the driver is stopped.*/
i2sp->spi->CR1 = 0;
i2sp->spi->CR2 = SPI_CR2_TXDMAEN;
#endif
}
#endif
}
/* I2S (re)configuration.*/
i2sp->spi->I2SPR = i2sp->config->i2spr;
i2sp->spi->I2SCFGR = i2sp->config->i2scfgr | i2sp->cfg | SPI_I2SCFGR_I2SMOD;
}
/**
* @brief Deactivates the I2S peripheral.
*
* @param[in] i2sp pointer to the @p I2SDriver object
*
* @notapi
*/
void i2s_lld_stop(I2SDriver *i2sp) {
/* If in ready state then disables the SPI clock.*/
if (i2sp->state == I2S_READY) {
/* SPI disable.*/
i2sp->spi->CR2 = 0;
if (NULL != i2sp->dmarx)
dmaStreamRelease(i2sp->dmarx);
if (NULL != i2sp->dmatx)
dmaStreamRelease(i2sp->dmatx);
#if STM32_I2S_USE_SPI1
if (&I2SD1 == i2sp)
rccDisableSPI1();
#endif
#if STM32_I2S_USE_SPI2
if (&I2SD2 == i2sp)
rccDisableSPI2();
#endif
#if STM32_I2S_USE_SPI3
if (&I2SD3 == i2sp)
rccDisableSPI3();
#endif
}
}
/**
* @brief Starts a I2S data exchange.
*
* @param[in] i2sp pointer to the @p I2SDriver object
*
* @notapi
*/
void i2s_lld_start_exchange(I2SDriver *i2sp) {
size_t size = i2sp->config->size;
/* In 32 bit modes the DMA has to perform double operations because fetches
are always performed using 16 bit accesses.
DATLEN CHLEN SIZE
00 (16) 0 (16) 16
00 (16) 1 (32) 16
01 (24) X 32
10 (32) X 32
11 (NA) X NA
*/
if ((i2sp->config->i2scfgr & SPI_I2SCFGR_DATLEN) != 0)
size *= 2;
/* RX DMA setup.*/
if (NULL != i2sp->dmarx) {
dmaStreamSetMode(i2sp->dmarx, i2sp->rxdmamode);
dmaStreamSetPeripheral(i2sp->dmarx, &i2sp->spi->DR);
dmaStreamSetMemory0(i2sp->dmarx, i2sp->config->rx_buffer);
dmaStreamSetTransactionSize(i2sp->dmarx, size);
dmaStreamEnable(i2sp->dmarx);
}
/* TX DMA setup.*/
if (NULL != i2sp->dmatx) {
dmaStreamSetMode(i2sp->dmatx, i2sp->txdmamode);
dmaStreamSetPeripheral(i2sp->dmatx, &i2sp->spi->DR);
dmaStreamSetMemory0(i2sp->dmatx, i2sp->config->tx_buffer);
dmaStreamSetTransactionSize(i2sp->dmatx, size);
dmaStreamEnable(i2sp->dmatx);
}
/* Starting transfer.*/
i2sp->spi->I2SCFGR |= SPI_I2SCFGR_I2SE;
}
/**
* @brief Stops the ongoing data exchange.
* @details The ongoing data exchange, if any, is stopped, if the driver
* was not active the function does nothing.
*
* @param[in] i2sp pointer to the @p I2SDriver object
*
* @notapi
*/
void i2s_lld_stop_exchange(I2SDriver *i2sp) {
/* Stop TX DMA, if enabled.*/
if (NULL != i2sp->dmatx) {
dmaStreamDisable(i2sp->dmatx);
/* From the RM: To switch off the I2S, by clearing I2SE, it is mandatory
to wait for TXE = 1 and BSY = 0.*/
while ((i2sp->spi->SR & (SPI_SR_TXE | SPI_SR_BSY)) != SPI_SR_TXE)
;
}
/* Stop SPI/I2S peripheral.*/
i2sp->spi->I2SCFGR &= ~SPI_I2SCFGR_I2SE;
/* Stop RX DMA, if enabled.*/
if (NULL != i2sp->dmarx)
dmaStreamDisable(i2sp->dmarx);
}
#endif /* HAL_USE_I2S */
/** @} */

432
os/hal/ports/STM32/LLD/SPIv3/hal_i2s_lld.h
View File

@ -1,432 +0,0 @@
/*
ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
/**
* @file SPIv2/hal_i2s_lld.h
* @brief STM32 I2S subsystem low level driver header.
*
* @addtogroup I2S
* @{
*/
#ifndef HAL_I2S_LLD_H
#define HAL_I2S_LLD_H
#if HAL_USE_I2S || defined(__DOXYGEN__)
/*===========================================================================*/
/* Driver constants. */
/*===========================================================================*/
/**
* @name Static I2S modes
* @{
*/
#define STM32_I2S_MODE_SLAVE 0
#define STM32_I2S_MODE_MASTER 1
#define STM32_I2S_MODE_RX 2
#define STM32_I2S_MODE_TX 4
#define STM32_I2S_MODE_RXTX (STM32_I2S_MODE_RX | \
STM32_I2S_MODE_TX)
/** @} */
/**
* @name Mode checks
* @{
*/
#define STM32_I2S_IS_MASTER(mode) ((mode) & STM32_I2S_MODE_MASTER)
#define STM32_I2S_RX_ENABLED(mode) ((mode) & STM32_I2S_MODE_RX)
#define STM32_I2S_TX_ENABLED(mode) ((mode) & STM32_I2S_MODE_TX)
/** @} */
/*===========================================================================*/
/* Driver pre-compile time settings. */
/*===========================================================================*/
/**
* @name Configuration options
* @{
*/
/**
* @brief I2S1 driver enable switch.
* @details If set to @p TRUE the support for I2S1 is included.
* @note The default is @p TRUE.
*/
#if !defined(STM32_I2S_USE_SPI1) || defined(__DOXYGEN__)
#define STM32_I2S_USE_SPI1 FALSE
#endif
/**
* @brief I2S2 driver enable switch.
* @details If set to @p TRUE the support for I2S2 is included.
* @note The default is @p TRUE.
*/
#if !defined(STM32_I2S_USE_SPI2) || defined(__DOXYGEN__)
#define STM32_I2S_USE_SPI2 FALSE
#endif
/**
* @brief I2S3 driver enable switch.
* @details If set to @p TRUE the support for I2S3 is included.
* @note The default is @p TRUE.
*/
#if !defined(STM32_I2S_USE_SPI3) || defined(__DOXYGEN__)
#define STM32_I2S_USE_SPI3 FALSE
#endif
/**
* @brief I2S1 mode.
*/
#if !defined(STM32_I2S_SPI1_MODE) || defined(__DOXYGEN__)
#define STM32_I2S_SPI1_MODE (STM32_I2S_MODE_MASTER | \
STM32_I2S_MODE_RX)
#endif
/**
* @brief I2S2 mode.
*/
#if !defined(STM32_I2S_SPI2_MODE) || defined(__DOXYGEN__)
#define STM32_I2S_SPI2_MODE (STM32_I2S_MODE_MASTER | \
STM32_I2S_MODE_RX)
#endif
/**
* @brief I2S3 mode.
*/
#if !defined(STM32_I2S_SPI3_MODE) || defined(__DOXYGEN__)
#define STM32_I2S_SPI3_MODE (STM32_I2S_MODE_MASTER | \
STM32_I2S_MODE_RX)
#endif
/**
* @brief I2S1 interrupt priority level setting.
*/
#if !defined(STM32_I2S_SPI1_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define STM32_I2S_SPI1_IRQ_PRIORITY 10
#endif
/**
* @brief I2S2 interrupt priority level setting.
*/
#if !defined(STM32_I2S_SPI2_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define STM32_I2S_SPI2_IRQ_PRIORITY 10
#endif
/**
* @brief I2S3 interrupt priority level setting.
*/
#if !defined(STM32_I2S_SPI3_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define STM32_I2S_SPI3_IRQ_PRIORITY 10
#endif
/**
* @brief I2S1 DMA priority (0..3|lowest..highest).
*/
#if !defined(STM32_I2S_SPI1_DMA_PRIORITY) || defined(__DOXYGEN__)
#define STM32_I2S_SPI1_DMA_PRIORITY 1
#endif
/**
* @brief I2S2 DMA priority (0..3|lowest..highest).
*/
#if !defined(STM32_I2S_SPI2_DMA_PRIORITY) || defined(__DOXYGEN__)
#define STM32_I2S_SPI2_DMA_PRIORITY 1
#endif
/**
* @brief I2S3 DMA priority (0..3|lowest..highest).
*/
#if !defined(STM32_I2S_SPI3_DMA_PRIORITY) || defined(__DOXYGEN__)
#define STM32_I2S_SPI3_DMA_PRIORITY 1
#endif
/**
* @brief I2S DMA error hook.
*/
#if !defined(STM32_I2S_DMA_ERROR_HOOK) || defined(__DOXYGEN__)
#define STM32_I2S_DMA_ERROR_HOOK(i2sp) osalSysHalt("DMA failure")
#endif
/** @} */
/*===========================================================================*/
/* Derived constants and error checks. */
/*===========================================================================*/
#if STM32_I2S_USE_SPI1 && !STM32_SPI1_SUPPORTS_I2S
#error "SPI1 does not support I2S mode"
#endif
#if STM32_I2S_USE_SPI2 && !STM32_SPI2_SUPPORTS_I2S
#error "SPI2 does not support I2S mode"
#endif
#if STM32_I2S_USE_SPI3 && !STM32_SPI3_SUPPORTS_I2S
#error "SPI3 does not support I2S mode"
#endif
#if STM32_I2S_RX_ENABLED(STM32_I2S_SPI1_MODE) && \
STM32_I2S_TX_ENABLED(STM32_I2S_SPI1_MODE)
#error "I2S1 RX and TX mode not supported in this driver implementation"
#endif
#if STM32_I2S_RX_ENABLED(STM32_I2S_SPI2_MODE) && \
STM32_I2S_TX_ENABLED(STM32_I2S_SPI2_MODE)
#error "I2S2 RX and TX mode not supported in this driver implementation"
#endif
#if STM32_I2S_RX_ENABLED(STM32_I2S_SPI3_MODE) && \
STM32_I2S_TX_ENABLED(STM32_I2S_SPI3_MODE)
#error "I2S3 RX and TX mode not supported in this driver implementation"
#endif
#if STM32_I2S_USE_SPI1 && !STM32_HAS_SPI1
#error "SPI1 not present in the selected device"
#endif
#if STM32_I2S_USE_SPI2 && !STM32_HAS_SPI2
#error "SPI2 not present in the selected device"
#endif
#if STM32_I2S_USE_SPI3 && !STM32_HAS_SPI3
#error "SPI3 not present in the selected device"
#endif
#if !STM32_I2S_USE_SPI1 && !STM32_I2S_USE_SPI2 && !STM32_I2S_USE_SPI3
#error "I2S driver activated but no SPI peripheral assigned"
#endif
#if STM32_I2S_USE_SPI1 && \
!OSAL_IRQ_IS_VALID_PRIORITY(STM32_I2S_SPI1_IRQ_PRIORITY)
#error "Invalid IRQ priority assigned to SPI1"
#endif
#if STM32_I2S_USE_SPI2 && \
!OSAL_IRQ_IS_VALID_PRIORITY(STM32_I2S_SPI2_IRQ_PRIORITY)
#error "Invalid IRQ priority assigned to SPI2"
#endif
#if STM32_I2S_USE_SPI3 && \
!OSAL_IRQ_IS_VALID_PRIORITY(STM32_I2S_SPI3_IRQ_PRIORITY)
#error "Invalid IRQ priority assigned to SPI3"
#endif
#if STM32_I2S_USE_SPI1 && \
!STM32_DMA_IS_VALID_PRIORITY(STM32_I2S_SPI1_DMA_PRIORITY)
#error "Invalid DMA priority assigned to SPI1"
#endif
#if STM32_I2S_USE_SPI2 && \
!STM32_DMA_IS_VALID_PRIORITY(STM32_I2S_SPI2_DMA_PRIORITY)
#error "Invalid DMA priority assigned to SPI2"
#endif
#if STM32_I2S_USE_SPI3 && \
!STM32_DMA_IS_VALID_PRIORITY(STM32_I2S_SPI3_DMA_PRIORITY)
#error "Invalid DMA priority assigned to SPI3"
#endif
/* The following checks are only required when there is a DMA able to
reassign streams to different channels.*/
#if STM32_ADVANCED_DMA
/* Check on the presence of the DMA streams settings in mcuconf.h.*/
#if STM32_I2S_USE_SPI1 && (!defined(STM32_I2S_SPI1_RX_DMA_STREAM) || \
!defined(STM32_I2S_SPI1_TX_DMA_STREAM))
#error "SPI1 DMA streams not defined"
#endif
#if STM32_I2S_USE_SPI2 && (!defined(STM32_I2S_SPI2_RX_DMA_STREAM) || \
!defined(STM32_I2S_SPI2_TX_DMA_STREAM))
#error "SPI2 DMA streams not defined"
#endif
#if STM32_I2S_USE_SPI3 && (!defined(STM32_I2S_SPI3_RX_DMA_STREAM) || \
!defined(STM32_I2S_SPI3_TX_DMA_STREAM))
#error "SPI3 DMA streams not defined"
#endif
/* Check on the validity of the assigned DMA channels.*/
#if STM32_I2S_USE_SPI1 && \
!STM32_DMA_IS_VALID_ID(STM32_I2S_SPI1_RX_DMA_STREAM, STM32_SPI1_RX_DMA_MSK)
#error "invalid DMA stream associated to SPI1 RX"
#endif
#if STM32_I2S_USE_SPI1 && \
!STM32_DMA_IS_VALID_ID(STM32_I2S_SPI1_TX_DMA_STREAM, STM32_SPI1_TX_DMA_MSK)
#error "invalid DMA stream associated to SPI1 TX"
#endif
#if STM32_I2S_USE_SPI2 && \
!STM32_DMA_IS_VALID_ID(STM32_I2S_SPI2_RX_DMA_STREAM, STM32_SPI2_RX_DMA_MSK)
#error "invalid DMA stream associated to SPI2 RX"
#endif
#if STM32_I2S_USE_SPI2 && \
!STM32_DMA_IS_VALID_ID(STM32_I2S_SPI2_TX_DMA_STREAM, STM32_SPI2_TX_DMA_MSK)
#error "invalid DMA stream associated to SPI2 TX"
#endif
#if STM32_I2S_USE_SPI3 && \
!STM32_DMA_IS_VALID_ID(STM32_I2S_SPI3_RX_DMA_STREAM, STM32_SPI3_RX_DMA_MSK)
#error "invalid DMA stream associated to SPI3 RX"
#endif
#if STM32_I2S_USE_SPI3 && \
!STM32_DMA_IS_VALID_ID(STM32_I2S_SPI3_TX_DMA_STREAM, STM32_SPI3_TX_DMA_MSK)
#error "invalid DMA stream associated to SPI3 TX"
#endif
#endif /* STM32_ADVANCED_DMA */
#if !defined(STM32_DMA_REQUIRED)
#define STM32_DMA_REQUIRED
#endif
/*===========================================================================*/
/* Driver data structures and types. */
/*===========================================================================*/
/**
* @brief Type of a structure representing an I2S driver.
*/
typedef struct I2SDriver I2SDriver;
/**
* @brief I2S notification callback type.
*
* @param[in] i2sp pointer to the @p I2SDriver object
* @param[in] offset offset in buffers of the data to read/write
* @param[in] n number of samples to read/write
*/
typedef void (*i2scallback_t)(I2SDriver *i2sp, size_t offset, size_t n);
/**
* @brief Driver configuration structure.
* @note It could be empty on some architectures.
*/
typedef struct {
/**
* @brief Transmission buffer pointer.
* @note Can be @p NULL if TX is not required.
*/
const void *tx_buffer;
/**
* @brief Receive buffer pointer.
* @note Can be @p NULL if RX is not required.
*/
void *rx_buffer;
/**
* @brief TX and RX buffers size as number of samples.
*/
size_t size;
/**
* @brief Callback function called during streaming.
*/
i2scallback_t end_cb;
/* End of the mandatory fields.*/
/**
* @brief Configuration of the I2SCFGR register.
* @details See the STM32 reference manual, this register is used for
* the I2S configuration, the following bits must not be
* specified because handled directly by the driver:
* - I2SMOD
* - I2SE
* - I2SCFG
* .
*/
int16_t i2scfgr;
/**
* @brief Configuration of the I2SPR register.
* @details See the STM32 reference manual, this register is used for
* the I2S clock setup.
*/
int16_t i2spr;
} I2SConfig;
/**
* @brief Structure representing an I2S driver.
*/
struct I2SDriver {
/**
* @brief Driver state.
*/
i2sstate_t state;
/**
* @brief Current configuration data.
*/
const I2SConfig *config;
/* End of the mandatory fields.*/
/**
* @brief Pointer to the SPIx registers block.
*/
SPI_TypeDef *spi;
/**
* @brief Calculated part of the I2SCFGR register.
*/
uint16_t cfg;
/**
* @brief Receive DMA stream or @p NULL.
*/
const stm32_dma_stream_t *dmarx;
/**
* @brief Transmit DMA stream or @p NULL.
*/
const stm32_dma_stream_t *dmatx;
/**
* @brief RX DMA mode bit mask.
*/
uint32_t rxdmamode;
/**
* @brief TX DMA mode bit mask.
*/
uint32_t txdmamode;
};
/*===========================================================================*/
/* Driver macros. */
/*===========================================================================*/
/*===========================================================================*/
/* External declarations. */
/*===========================================================================*/
#if STM32_I2S_USE_SPI1 && !defined(__DOXYGEN__)
extern I2SDriver I2SD1;
#endif
#if STM32_I2S_USE_SPI2 && !defined(__DOXYGEN__)
extern I2SDriver I2SD2;
#endif
#if STM32_I2S_USE_SPI3 && !defined(__DOXYGEN__)
extern I2SDriver I2SD3;
#endif
#ifdef __cplusplus
extern "C" {
#endif
void i2s_lld_init(void);
void i2s_lld_start(I2SDriver *i2sp);
void i2s_lld_stop(I2SDriver *i2sp);
void i2s_lld_start_exchange(I2SDriver *i2sp);
void i2s_lld_stop_exchange(I2SDriver *i2sp);
#ifdef __cplusplus
}
#endif
#endif /* HAL_USE_I2S */
#endif /* HAL_I2S_LLD_H */
/** @} */

32
os/hal/ports/STM32/LLD/SPIv3/hal_spi_lld.c
View File

@ -503,12 +503,12 @@ void spi_lld_start(SPIDriver *spip) {
if (spip->state == SPI_STOP) {
#if STM32_SPI_USE_SPI1
if (&SPID1 == spip) {
spip->rx.dma = dmaStreamAllocI(STM32_SPI_SPI1_RX_DMA_CHANNEL,
spip->rx.dma = dmaStreamAllocI(STM32_SPI_SPI1_RX_DMA_STREAM,
STM32_SPI_SPI1_IRQ_PRIORITY,
(stm32_dmaisr_t)spi_lld_serve_dma_rx_interrupt,
(void *)spip);
osalDbgAssert(spip->rx.dma != NULL, "unable to allocate stream");
spip->tx.dma = dmaStreamAllocI(STM32_SPI_SPI1_TX_DMA_CHANNEL,
spip->tx.dma = dmaStreamAllocI(STM32_SPI_SPI1_TX_DMA_STREAM,
STM32_SPI_SPI1_IRQ_PRIORITY,
(stm32_dmaisr_t)spi_lld_serve_dma_tx_interrupt,
(void *)spip);
@ -520,12 +520,12 @@ void spi_lld_start(SPIDriver *spip) {
#endif
#if STM32_SPI_USE_SPI2
if (&SPID2 == spip) {
spip->rx.dma = dmaStreamAllocI(STM32_SPI_SPI2_RX_DMA_CHANNEL,
spip->rx.dma = dmaStreamAllocI(STM32_SPI_SPI2_RX_DMA_STREAM,
STM32_SPI_SPI2_IRQ_PRIORITY,
(stm32_dmaisr_t)spi_lld_serve_dma_rx_interrupt,
(void *)spip);
osalDbgAssert(spip->rx.dma != NULL, "unable to allocate stream");
spip->tx.dma = dmaStreamAllocI(STM32_SPI_SPI2_TX_DMA_CHANNEL,
spip->tx.dma = dmaStreamAllocI(STM32_SPI_SPI2_TX_DMA_STREAM,
STM32_SPI_SPI2_IRQ_PRIORITY,
(stm32_dmaisr_t)spi_lld_serve_dma_tx_interrupt,
(void *)spip);
@ -537,12 +537,12 @@ void spi_lld_start(SPIDriver *spip) {
#endif
#if STM32_SPI_USE_SPI3
if (&SPID3 == spip) {
spip->rx.dma = dmaStreamAllocI(STM32_SPI_SPI3_RX_DMA_CHANNEL,
spip->rx.dma = dmaStreamAllocI(STM32_SPI_SPI3_RX_DMA_STREAM,
STM32_SPI_SPI3_IRQ_PRIORITY,
(stm32_dmaisr_t)spi_lld_serve_dma_rx_interrupt,
(void *)spip);
osalDbgAssert(spip->rx.dma != NULL, "unable to allocate stream");
spip->tx.dma = dmaStreamAllocI(STM32_SPI_SPI3_TX_DMA_CHANNEL,
spip->tx.dma = dmaStreamAllocI(STM32_SPI_SPI3_TX_DMA_STREAM,
STM32_SPI_SPI3_IRQ_PRIORITY,
(stm32_dmaisr_t)spi_lld_serve_dma_tx_interrupt,
(void *)spip);
@ -554,12 +554,12 @@ void spi_lld_start(SPIDriver *spip) {
#endif
#if STM32_SPI_USE_SPI4
if (&SPID4 == spip) {
spip->rx.dma = dmaStreamAllocI(STM32_SPI_SPI4_RX_DMA_CHANNEL,
spip->rx.dma = dmaStreamAllocI(STM32_SPI_SPI4_RX_DMA_STREAM,
STM32_SPI_SPI4_IRQ_PRIORITY,
(stm32_dmaisr_t)spi_lld_serve_dma_rx_interrupt,
(void *)spip);
osalDbgAssert(spip->rx.dma != NULL, "unable to allocate stream");
spip->tx.dma = dmaStreamAllocI(STM32_SPI_SPI4_TX_DMA_CHANNEL,
spip->tx.dma = dmaStreamAllocI(STM32_SPI_SPI4_TX_DMA_STREAM,
STM32_SPI_SPI4_IRQ_PRIORITY,
(stm32_dmaisr_t)spi_lld_serve_dma_tx_interrupt,
(void *)spip);
@ -571,12 +571,12 @@ void spi_lld_start(SPIDriver *spip) {
#endif
#if STM32_SPI_USE_SPI5
if (&SPID5 == spip) {
spip->rx.dma = dmaStreamAllocI(STM32_SPI_SPI5_RX_DMA_CHANNEL,
spip->rx.dma = dmaStreamAllocI(STM32_SPI_SPI5_RX_DMA_STREAM,
STM32_SPI_SPI5_IRQ_PRIORITY,
(stm32_dmaisr_t)spi_lld_serve_dma_rx_interrupt,
(void *)spip);
osalDbgAssert(spip->rx.dma != NULL, "unable to allocate stream");
spip->tx.dma = dmaStreamAllocI(STM32_SPI_SPI5_TX_DMA_CHANNEL,
spip->tx.dma = dmaStreamAllocI(STM32_SPI_SPI5_TX_DMA_STREAM,
STM32_SPI_SPI5_IRQ_PRIORITY,
(stm32_dmaisr_t)spi_lld_serve_dma_tx_interrupt,
(void *)spip);
@ -588,12 +588,12 @@ void spi_lld_start(SPIDriver *spip) {
#endif
#if STM32_SPI_USE_SPI6
if (&SPID6 == spip) {
spip->rx.bdma = bdmaStreamAllocI(STM32_SPI_SPI6_RX_BDMA_CHANNEL,
spip->rx.bdma = bdmaStreamAllocI(STM32_SPI_SPI6_RX_BDMA_STREAM,
STM32_SPI_SPI6_IRQ_PRIORITY,
(stm32_dmaisr_t)spi_lld_serve_bdma_rx_interrupt,
(void *)spip);
osalDbgAssert(spip->rx.dma != NULL, "unable to allocate stream");
spip->tx.bdma = bdmaStreamAllocI(STM32_SPI_SPI6_TX_BDMA_CHANNEL,
spip->tx.bdma = bdmaStreamAllocI(STM32_SPI_SPI6_TX_BDMA_STREAM,
STM32_SPI_SPI6_IRQ_PRIORITY,
(stm32_dmaisr_t)spi_lld_serve_bdma_tx_interrupt,
(void *)spip);
@ -737,8 +737,8 @@ void spi_lld_stop(SPIDriver *spip) {
#endif
#if defined(STM32_SPI_BDMA_REQUIRED)
{
bdmaStreamRelease(spip->rx.bdma);
bdmaStreamRelease(spip->tx.bdma);
bdmaStreamFreeI(spip->rx.bdma);
bdmaStreamFreeI(spip->tx.bdma);
}
#endif
#if defined(STM32_SPI_DMA_REQUIRED) && defined(STM32_SPI_BDMA_REQUIRED)
@ -746,8 +746,8 @@ void spi_lld_stop(SPIDriver *spip) {
#endif
#if defined(STM32_SPI_DMA_REQUIRED)
{
dmaStreamRelease(spip->rx.dma);
dmaStreamRelease(spip->tx.dma);
dmaStreamFreeI(spip->rx.dma);
dmaStreamFreeI(spip->tx.dma);
}
#endif

164
os/hal/ports/STM32/LLD/SPIv3/hal_spi_lld.h
View File

@ -176,90 +176,6 @@
#define STM32_SPI_SPI6_IRQ_PRIORITY 10
#endif
/**
* @brief SPI1 RX DMA channel setting.
*/
#if !defined(STM32_SPI_SPI1_RX_DMA_CHANNEL) || defined(__DOXYGEN__)
#define STM32_SPI_SPI1_RX_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY
#endif
/**
* @brief SPI1 TX DMA channel setting.
*/
#if !defined(STM32_SPI_SPI1_TX_DMA_CHANNEL) || defined(__DOXYGEN__)
#define STM32_SPI_SPI1_TX_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY
#endif
/**
* @brief SPI2 RX DMA channel setting.
*/
#if !defined(STM32_SPI_SPI2_RX_DMA_CHANNEL) || defined(__DOXYGEN__)
#define STM32_SPI_SPI2_RX_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY
#endif
/**
* @brief SPI2 TX DMA channel setting.
*/
#if !defined(STM32_SPI_SPI2_TX_DMA_CHANNEL) || defined(__DOXYGEN__)
#define STM32_SPI_SPI2_TX_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY
#endif
/**
* @brief SPI3 RX DMA channel setting.
*/
#if !defined(STM32_SPI_SPI3_RX_DMA_CHANNEL) || defined(__DOXYGEN__)
#define STM32_SPI_SPI3_RX_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY
#endif
/**
* @brief SPI3 TX DMA channel setting.
*/
#if !defined(STM32_SPI_SPI3_TX_DMA_CHANNEL) || defined(__DOXYGEN__)
#define STM32_SPI_SPI3_TX_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY
#endif
/**
* @brief SPI4 RX DMA channel setting.
*/
#if !defined(STM32_SPI_SPI4_RX_DMA_CHANNEL) || defined(__DOXYGEN__)
#define STM32_SPI_SPI4_RX_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY
#endif
/**
* @brief SPI4 TX DMA channel setting.
*/
#if !defined(STM32_SPI_SPI4_TX_DMA_CHANNEL) || defined(__DOXYGEN__)
#define STM32_SPI_SPI4_TX_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY
#endif
/**
* @brief SPI5 RX DMA channel setting.
*/
#if !defined(STM32_SPI_SPI5_RX_DMA_CHANNEL) || defined(__DOXYGEN__)
#define STM32_SPI_SPI5_RX_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY
#endif
/**
* @brief SPI5 TX DMA channel setting.
*/
#if !defined(STM32_SPI_SPI5_TX_DMA_CHANNEL) || defined(__DOXYGEN__)
#define STM32_SPI_SPI5_TX_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY
#endif
/**
* @brief SPI6 RX BDMA channel setting.
*/
#if !defined(STM32_SPI_SPI6_RX_BDMA_CHANNEL) || defined(__DOXYGEN__)
#define STM32_SPI_SPI6_RX_BDMA_CHANNEL STM32_BDMA_STREAM_ID_ANY
#endif
/**
* @brief SPI6 TX BDMA channel setting.
*/
#if !defined(STM32_SPI_SPI6_TX_BDMA_CHANNEL) || defined(__DOXYGEN__)
#define STM32_SPI_SPI6_TX_BDMA_CHANNEL 3
#endif
/**
* @brief SPI1 DMA priority (0..3|lowest..highest).
* @note The priority level is used for both the TX and RX DMA streams but
@ -391,64 +307,96 @@
#error "Invalid IRQ priority assigned to SPI6"
#endif
/* Check on the presence of the DMA streams settings in mcuconf.h.*/
#if STM32_SPI_USE_SPI1 && (!defined(STM32_SPI_SPI1_RX_DMA_STREAM) || \
!defined(STM32_SPI_SPI1_TX_DMA_STREAM))
#error "SPI1 DMA streams not defined"
#endif
#if STM32_SPI_USE_SPI2 && (!defined(STM32_SPI_SPI2_RX_DMA_STREAM) || \
!defined(STM32_SPI_SPI2_TX_DMA_STREAM))
#error "SPI2 DMA streams not defined"
#endif
#if STM32_SPI_USE_SPI3 && (!defined(STM32_SPI_SPI3_RX_DMA_STREAM) || \
!defined(STM32_SPI_SPI3_TX_DMA_STREAM))
#error "SPI3 DMA streams not defined"
#endif
#if STM32_SPI_USE_SPI4 && (!defined(STM32_SPI_SPI4_RX_DMA_STREAM) || \
!defined(STM32_SPI_SPI4_TX_DMA_STREAM))
#error "SPI4 DMA streams not defined"
#endif
#if STM32_SPI_USE_SPI5 && (!defined(STM32_SPI_SPI5_RX_DMA_STREAM) || \
!defined(STM32_SPI_SPI5_TX_DMA_STREAM))
#error "SPI5 DMA streams not defined"
#endif
#if STM32_SPI_USE_SPI6 && (!defined(STM32_SPI_SPI6_RX_BDMA_STREAM) || \
!defined(STM32_SPI_SPI6_TX_BDMA_STREAM))
#error "SPI6 BDMA streams not defined"
#endif
/* Check on the validity of the assigned DMA streams.*/
#if STM32_SPI_USE_SPI1 && \
!STM32_DMA_IS_VALID_CHANNEL(STM32_SPI_SPI1_RX_DMA_CHANNEL)
#error "Invalid DMA channel assigned to SPI1 RX"
!STM32_DMA_IS_VALID_STREAM(STM32_SPI_SPI1_RX_DMA_STREAM)
#error "Invalid DMA stream assigned to SPI1 RX"
#endif
#if STM32_SPI_USE_SPI1 && \
!STM32_DMA_IS_VALID_CHANNEL(STM32_SPI_SPI1_TX_DMA_CHANNEL)
#error "Invalid DMA channel assigned to SPI1 TX"
!STM32_DMA_IS_VALID_STREAM(STM32_SPI_SPI1_TX_DMA_STREAM)
#error "Invalid DMA stream assigned to SPI1 TX"
#endif
#if STM32_SPI_USE_SPI2 && \
!STM32_DMA_IS_VALID_CHANNEL(STM32_SPI_SPI2_RX_DMA_CHANNEL)
#error "Invalid DMA channel assigned to SPI2 RX"
!STM32_DMA_IS_VALID_STREAM(STM32_SPI_SPI2_RX_DMA_STREAM)
#error "Invalid DMA stream assigned to SPI2 RX"
#endif
#if STM32_SPI_USE_SPI2 && \
!STM32_DMA_IS_VALID_CHANNEL(STM32_SPI_SPI2_TX_DMA_CHANNEL)
#error "Invalid DMA channel assigned to SPI2 TX"
!STM32_DMA_IS_VALID_STREAM(STM32_SPI_SPI2_TX_DMA_STREAM)
#error "Invalid DMA stream assigned to SPI2 TX"
#endif
#if STM32_SPI_USE_SPI3 && \
!STM32_DMA_IS_VALID_CHANNEL(STM32_SPI_SPI3_RX_DMA_CHANNEL)
#error "Invalid DMA channel assigned to SPI3 RX"
!STM32_DMA_IS_VALID_STREAM(STM32_SPI_SPI3_RX_DMA_STREAM)
#error "Invalid DMA stream assigned to SPI3 RX"
#endif
#if STM32_SPI_USE_SPI3 && \
!STM32_DMA_IS_VALID_CHANNEL(STM32_SPI_SPI3_TX_DMA_CHANNEL)
#error "Invalid DMA channel assigned to SPI3 TX"
!STM32_DMA_IS_VALID_STREAM(STM32_SPI_SPI3_TX_DMA_STREAM)
#error "Invalid DMA stream assigned to SPI3 TX"
#endif
#if STM32_SPI_USE_SPI4 && \
!STM32_DMA_IS_VALID_CHANNEL(STM32_SPI_SPI4_RX_DMA_CHANNEL)
#error "Invalid DMA channel assigned to SPI4 RX"
!STM32_DMA_IS_VALID_STREAM(STM32_SPI_SPI4_RX_DMA_STREAM)
#error "Invalid DMA stream assigned to SPI4 RX"
#endif
#if STM32_SPI_USE_SPI4 && \
!STM32_DMA_IS_VALID_CHANNEL(STM32_SPI_SPI4_TX_DMA_CHANNEL)
#error "Invalid DMA channel assigned to SPI4 TX"
!STM32_DMA_IS_VALID_STREAM(STM32_SPI_SPI4_TX_DMA_STREAM)
#error "Invalid DMA stream assigned to SPI4 TX"
#endif
#if STM32_SPI_USE_SPI5 && \
!STM32_DMA_IS_VALID_CHANNEL(STM32_SPI_SPI5_RX_DMA_CHANNEL)
#error "Invalid DMA channel assigned to SPI5 RX"
!STM32_DMA_IS_VALID_STREAM(STM32_SPI_SPI5_RX_DMA_STREAM)
#error "Invalid DMA stream assigned to SPI5 RX"
#endif
#if STM32_SPI_USE_SPI5 && \
!STM32_DMA_IS_VALID_CHANNEL(STM32_SPI_SPI5_TX_DMA_CHANNEL)
#error "Invalid DMA channel assigned to SPI5 TX"
!STM32_DMA_IS_VALID_STREAM(STM32_SPI_SPI5_TX_DMA_STREAM)
#error "Invalid DMA stream assigned to SPI5 TX"
#endif
#if STM32_SPI_USE_SPI6 && \
!STM32_BDMA_IS_VALID_CHANNEL(STM32_SPI_SPI6_RX_BDMA_CHANNEL)
#error "Invalid BDMA channel assigned to SPI6 RX"
!STM32_BDMA_IS_VALID_STREAM(STM32_SPI_SPI6_RX_BDMA_STREAM)
#error "Invalid BDMA stream assigned to SPI6 RX"
#endif
#if STM32_SPI_USE_SPI6 && \
!STM32_BDMA_IS_VALID_CHANNEL(STM32_SPI_SPI6_TX_BDMA_CHANNEL)
#error "Invalid BDMA channel assigned to SPI6 TX"
!STM32_BDMA_IS_VALID_STREAM(STM32_SPI_SPI6_TX_BDMA_STREAM)
#error "Invalid BDMA stream assigned to SPI6 TX"
#endif
#if STM32_SPI_USE_SPI1 && \

118
os/hal/ports/STM32/LLD/USARTv1/hal_uart_lld.c
View File

@ -521,63 +521,63 @@ void uart_lld_init(void) {
uartObjectInit(&UARTD1);
UARTD1.usart = USART1;
UARTD1.dmamode = STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE;
UARTD1.dmarx = STM32_DMA_STREAM(STM32_UART_USART1_RX_DMA_STREAM);
UARTD1.dmatx = STM32_DMA_STREAM(STM32_UART_USART1_TX_DMA_STREAM);
UARTD1.dmarx = NULL;
UARTD1.dmatx = NULL;
#endif
#if STM32_UART_USE_USART2
uartObjectInit(&UARTD2);
UARTD2.usart = USART2;
UARTD2.dmamode = STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE;
UARTD2.dmarx = STM32_DMA_STREAM(STM32_UART_USART2_RX_DMA_STREAM);
UARTD2.dmatx = STM32_DMA_STREAM(STM32_UART_USART2_TX_DMA_STREAM);
UARTD2.dmarx = NULL;
UARTD2.dmatx = NULL;
#endif
#if STM32_UART_USE_USART3
uartObjectInit(&UARTD3);
UARTD3.usart = USART3;
UARTD3.dmamode = STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE;
UARTD3.dmarx = STM32_DMA_STREAM(STM32_UART_USART3_RX_DMA_STREAM);
UARTD3.dmatx = STM32_DMA_STREAM(STM32_UART_USART3_TX_DMA_STREAM);
UARTD3.dmarx = NULL;
UARTD3.dmatx = NULL;
#endif
#if STM32_UART_USE_UART4
uartObjectInit(&UARTD4);
UARTD4.usart = UART4;
UARTD4.dmamode = STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE;
UARTD4.dmarx = STM32_DMA_STREAM(STM32_UART_UART4_RX_DMA_STREAM);
UARTD4.dmatx = STM32_DMA_STREAM(STM32_UART_UART4_TX_DMA_STREAM);
UARTD4.dmarx = NULL;
UARTD4.dmatx = NULL;
#endif
#if STM32_UART_USE_UART5
uartObjectInit(&UARTD5);
UARTD5.usart = UART5;
UARTD5.dmamode = STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE;
UARTD5.dmarx = STM32_DMA_STREAM(STM32_UART_UART5_RX_DMA_STREAM);
UARTD5.dmatx = STM32_DMA_STREAM(STM32_UART_UART5_TX_DMA_STREAM);
UARTD5.dmarx = NULL;
UARTD5.dmatx = NULL;
#endif
#if STM32_UART_USE_USART6
uartObjectInit(&UARTD6);
UARTD6.usart = USART6;
UARTD6.dmarx = STM32_DMA_STREAM(STM32_UART_USART6_RX_DMA_STREAM);
UARTD6.dmatx = STM32_DMA_STREAM(STM32_UART_USART6_TX_DMA_STREAM);
UARTD6.dmarx = NULL;
UARTD6.dmatx = NULL;
#endif
#if STM32_UART_USE_UART7
uartObjectInit(&UARTD7);
UARTD7.usart = UART7;
UARTD7.dmamode = STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE;
UARTD7.dmarx = STM32_DMA_STREAM(STM32_UART_UART7_RX_DMA_STREAM);
UARTD7.dmatx = STM32_DMA_STREAM(STM32_UART_UART7_TX_DMA_STREAM);
UARTD7.dmarx = NULL;
UARTD7.dmatx = NULL;
#endif
#if STM32_UART_USE_UART8
uartObjectInit(&UARTD8);
UARTD8.usart = UART8;
UARTD8.dmamode = STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE;
UARTD8.dmarx = STM32_DMA_STREAM(STM32_UART_UART8_RX_DMA_STREAM);
UARTD8.dmatx = STM32_DMA_STREAM(STM32_UART_UART8_TX_DMA_STREAM);
UARTD8.dmarx = NULL;
UARTD8.dmatx = NULL;
#endif
}
@ -593,17 +593,17 @@ void uart_lld_start(UARTDriver *uartp) {
if (uartp->state == UART_STOP) {
#if STM32_UART_USE_USART1
if (&UARTD1 == uartp) {
bool b;
b = dmaStreamAllocate(uartp->dmarx,
uartp->dmarx = dmaStreamAllocI(STM32_UART_USART1_RX_DMA_STREAM,
STM32_UART_USART1_IRQ_PRIORITY,
(stm32_dmaisr_t)uart_lld_serve_rx_end_irq,
(void *)uartp);
osalDbgAssert(!b, "stream already allocated");
b = dmaStreamAllocate(uartp->dmatx,
osalDbgAssert(uartp->dmarx != NULL, "unable to allocate stream");
uartp->dmatx = dmaStreamAllocI(STM32_UART_USART1_TX_DMA_STREAM,
STM32_UART_USART1_IRQ_PRIORITY,
(stm32_dmaisr_t)uart_lld_serve_tx_end_irq,
(void *)uartp);
osalDbgAssert(!b, "stream already allocated");
osalDbgAssert(uartp->dmatx != NULL, "unable to allocate stream");
rccEnableUSART1(true);
nvicEnableVector(STM32_USART1_NUMBER, STM32_UART_USART1_IRQ_PRIORITY);
uartp->dmamode |= STM32_DMA_CR_CHSEL(USART1_RX_DMA_CHANNEL) |
@ -613,17 +613,17 @@ void uart_lld_start(UARTDriver *uartp) {
#if STM32_UART_USE_USART2
if (&UARTD2 == uartp) {
bool b;
b = dmaStreamAllocate(uartp->dmarx,
uartp->dmarx = dmaStreamAllocI(STM32_UART_USART2_RX_DMA_STREAM,
STM32_UART_USART2_IRQ_PRIORITY,
(stm32_dmaisr_t)uart_lld_serve_rx_end_irq,
(void *)uartp);
osalDbgAssert(!b, "stream already allocated");
b = dmaStreamAllocate(uartp->dmatx,
osalDbgAssert(uartp->dmarx != NULL, "unable to allocate stream");
uartp->dmatx = dmaStreamAllocI(STM32_UART_USART2_TX_DMA_STREAM,
STM32_UART_USART2_IRQ_PRIORITY,
(stm32_dmaisr_t)uart_lld_serve_tx_end_irq,
(void *)uartp);
osalDbgAssert(!b, "stream already allocated");
osalDbgAssert(uartp->dmatx != NULL, "unable to allocate stream");
rccEnableUSART2(true);
nvicEnableVector(STM32_USART2_NUMBER, STM32_UART_USART2_IRQ_PRIORITY);
uartp->dmamode |= STM32_DMA_CR_CHSEL(USART2_RX_DMA_CHANNEL) |
@ -633,17 +633,17 @@ void uart_lld_start(UARTDriver *uartp) {
#if STM32_UART_USE_USART3
if (&UARTD3 == uartp) {
bool b;
b = dmaStreamAllocate(uartp->dmarx,
uartp->dmarx = dmaStreamAllocI(STM32_UART_USART3_RX_DMA_STREAM,
STM32_UART_USART3_IRQ_PRIORITY,
(stm32_dmaisr_t)uart_lld_serve_rx_end_irq,
(void *)uartp);
osalDbgAssert(!b, "stream already allocated");
b = dmaStreamAllocate(uartp->dmatx,
osalDbgAssert(uartp->dmarx != NULL, "unable to allocate stream");
uartp->dmatx = dmaStreamAllocI(STM32_UART_USART3_TX_DMA_STREAM,
STM32_UART_USART3_IRQ_PRIORITY,
(stm32_dmaisr_t)uart_lld_serve_tx_end_irq,
(void *)uartp);
osalDbgAssert(!b, "stream already allocated");
osalDbgAssert(uartp->dmatx != NULL, "unable to allocate stream");
rccEnableUSART3(true);
nvicEnableVector(STM32_USART3_NUMBER, STM32_UART_USART3_IRQ_PRIORITY);
uartp->dmamode |= STM32_DMA_CR_CHSEL(USART3_RX_DMA_CHANNEL) |
@ -653,23 +653,23 @@ void uart_lld_start(UARTDriver *uartp) {
#if STM32_UART_USE_UART4
if (&UARTD4 == uartp) {
bool b;
osalDbgAssert((uartp->config->cr2 & STM32_UART45_CR2_CHECK_MASK) == 0,
"specified invalid bits in UART4 CR2 register settings");
osalDbgAssert((uartp->config->cr3 & STM32_UART45_CR3_CHECK_MASK) == 0,
"specified invalid bits in UART4 CR3 register settings");
b = dmaStreamAllocate(uartp->dmarx,
uartp->dmarx = dmaStreamAllocI(STM32_UART_UART4_RX_DMA_STREAM,
STM32_UART_UART4_IRQ_PRIORITY,
(stm32_dmaisr_t)uart_lld_serve_rx_end_irq,
(void *)uartp);
osalDbgAssert(!b, "stream already allocated");
b = dmaStreamAllocate(uartp->dmatx,
osalDbgAssert(uartp->dmarx != NULL, "unable to allocate stream");
uartp->dmatx = dmaStreamAllocI(STM32_UART_UART4_TX_DMA_STREAM,
STM32_UART_UART4_IRQ_PRIORITY,
(stm32_dmaisr_t)uart_lld_serve_tx_end_irq,
(void *)uartp);
osalDbgAssert(!b, "stream already allocated");
osalDbgAssert(uartp->dmatx != NULL, "unable to allocate stream");
rccEnableUART4(true);
nvicEnableVector(STM32_UART4_NUMBER, STM32_UART_UART4_IRQ_PRIORITY);
uartp->dmamode |= STM32_DMA_CR_CHSEL(UART4_RX_DMA_CHANNEL) |
@ -679,23 +679,23 @@ void uart_lld_start(UARTDriver *uartp) {
#if STM32_UART_USE_UART5
if (&UARTD5 == uartp) {
bool b;
osalDbgAssert((uartp->config->cr2 & STM32_UART45_CR2_CHECK_MASK) == 0,
"specified invalid bits in UART5 CR2 register settings");
osalDbgAssert((uartp->config->cr3 & STM32_UART45_CR3_CHECK_MASK) == 0,
"specified invalid bits in UART5 CR3 register settings");
b = dmaStreamAllocate(uartp->dmarx,
uartp->dmarx = dmaStreamAllocI(STM32_UART_UART5_RX_DMA_STREAM,
STM32_UART_UART5_IRQ_PRIORITY,
(stm32_dmaisr_t)uart_lld_serve_rx_end_irq,
(void *)uartp);
osalDbgAssert(!b, "stream already allocated");
b = dmaStreamAllocate(uartp->dmatx,
osalDbgAssert(uartp->dmarx != NULL, "unable to allocate stream");
uartp->dmatx = dmaStreamAllocI(STM32_UART_UART5_TX_DMA_STREAM,
STM32_UART_UART5_IRQ_PRIORITY,
(stm32_dmaisr_t)uart_lld_serve_tx_end_irq,
(void *)uartp);
osalDbgAssert(!b, "stream already allocated");
osalDbgAssert(uartp->dmatx != NULL, "unable to allocate stream");
rccEnableUART5(true);
nvicEnableVector(STM32_UART5_NUMBER, STM32_UART_UART5_IRQ_PRIORITY);
uartp->dmamode |= STM32_DMA_CR_CHSEL(UART5_RX_DMA_CHANNEL) |
@ -705,17 +705,17 @@ void uart_lld_start(UARTDriver *uartp) {
#if STM32_UART_USE_USART6
if (&UARTD6 == uartp) {
bool b;
b = dmaStreamAllocate(uartp->dmarx,
uartp->dmarx = dmaStreamAllocI(STM32_UART_USART6_RX_DMA_STREAM,
STM32_UART_USART6_IRQ_PRIORITY,
(stm32_dmaisr_t)uart_lld_serve_rx_end_irq,
(void *)uartp);
osalDbgAssert(!b, "stream already allocated");
b = dmaStreamAllocate(uartp->dmatx,
osalDbgAssert(uartp->dmarx != NULL, "unable to allocate stream");
uartp->dmatx = dmaStreamAllocI(STM32_UART_USART6_TX_DMA_STREAM,
STM32_UART_USART6_IRQ_PRIORITY,
(stm32_dmaisr_t)uart_lld_serve_tx_end_irq,
(void *)uartp);
osalDbgAssert(!b, "stream already allocated");
osalDbgAssert(uartp->dmatx != NULL, "unable to allocate stream");
rccEnableUSART6(true);
nvicEnableVector(STM32_USART6_NUMBER, STM32_UART_USART6_IRQ_PRIORITY);
uartp->dmamode |= STM32_DMA_CR_CHSEL(USART6_RX_DMA_CHANNEL) |
@ -725,23 +725,23 @@ void uart_lld_start(UARTDriver *uartp) {
#if STM32_UART_USE_UART7
if (&UARTD7 == uartp) {
bool b;
osalDbgAssert((uartp->config->cr2 & STM32_UART45_CR2_CHECK_MASK) == 0,
"specified invalid bits in UART7 CR2 register settings");
osalDbgAssert((uartp->config->cr3 & STM32_UART45_CR3_CHECK_MASK) == 0,
"specified invalid bits in UART7 CR3 register settings");
b = dmaStreamAllocate(uartp->dmarx,
uartp->dmarx = dmaStreamAllocI(STM32_UART_UART7_RX_DMA_STREAM,
STM32_UART_UART7_IRQ_PRIORITY,
(stm32_dmaisr_t)uart_lld_serve_rx_end_irq,
(void *)uartp);
osalDbgAssert(!b, "stream already allocated");
b = dmaStreamAllocate(uartp->dmatx,
osalDbgAssert(uartp->dmarx != NULL, "unable to allocate stream");
uartp->dmatx = dmaStreamAllocI(STM32_UART_UART7_TX_DMA_STREAM,
STM32_UART_UART7_IRQ_PRIORITY,
(stm32_dmaisr_t)uart_lld_serve_tx_end_irq,
(void *)uartp);
osalDbgAssert(!b, "stream already allocated");
osalDbgAssert(uartp->dmatx != NULL, "unable to allocate stream");
rccEnableUART7(true);
nvicEnableVector(STM32_UART7_NUMBER, STM32_UART_UART7_IRQ_PRIORITY);
uartp->dmamode |= STM32_DMA_CR_CHSEL(UART7_RX_DMA_CHANNEL) |
@ -751,23 +751,23 @@ void uart_lld_start(UARTDriver *uartp) {
#if STM32_UART_USE_UART8
if (&UARTD8 == uartp) {
bool b;
osalDbgAssert((uartp->config->cr2 & STM32_UART45_CR2_CHECK_MASK) == 0,
"specified invalid bits in UART8 CR2 register settings");
osalDbgAssert((uartp->config->cr3 & STM32_UART45_CR3_CHECK_MASK) == 0,
"specified invalid bits in UART8 CR3 register settings");
b = dmaStreamAllocate(uartp->dmarx,
uartp->dmarx = dmaStreamAllocI(STM32_UART_UART8_RX_DMA_STREAM,
STM32_UART_UART8_IRQ_PRIORITY,
(stm32_dmaisr_t)uart_lld_serve_rx_end_irq,
(void *)uartp);
osalDbgAssert(!b, "stream already allocated");
b = dmaStreamAllocate(uartp->dmatx,
osalDbgAssert(uartp->dmarx != NULL, "unable to allocate stream");
uartp->dmatx = dmaStreamAllocI(STM32_UART_UART8_TX_DMA_STREAM,
STM32_UART_UART8_IRQ_PRIORITY,
(stm32_dmaisr_t)uart_lld_serve_tx_end_irq,
(void *)uartp);
osalDbgAssert(!b, "stream already allocated");
osalDbgAssert(uartp->dmatx != NULL, "unable to allocate stream");
rccEnableUART8(true);
nvicEnableVector(STM32_UART8_NUMBER, STM32_UART_UART8_IRQ_PRIORITY);
uartp->dmamode |= STM32_DMA_CR_CHSEL(UART8_RX_DMA_CHANNEL) |
@ -800,8 +800,10 @@ void uart_lld_stop(UARTDriver *uartp) {
if (uartp->state == UART_READY) {
usart_stop(uartp);
dmaStreamRelease(uartp->dmarx);
dmaStreamRelease(uartp->dmatx);
dmaStreamFreeI(uartp->dmarx);
dmaStreamFreeI(uartp->dmatx);
uartp->dmarx = NULL;
uartp->dmatx = NULL;
#if STM32_UART_USE_USART1
if (&UARTD1 == uartp) {

158
os/hal/ports/STM32/LLD/USARTv2/hal_uart_lld.c
View File

@ -594,13 +594,8 @@ void uart_lld_init(void) {
UARTD1.usart = USART1;
UARTD1.clock = STM32_USART1CLK;
UARTD1.dmamode = STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE;
#if STM32_DMA_SUPPORTS_DMAMUX
UARTD1.dmarx = STM32_DMA_STREAM(STM32_UART_USART1_RX_DMA_CHANNEL);
UARTD1.dmatx = STM32_DMA_STREAM(STM32_UART_USART1_TX_DMA_CHANNEL);
#else
UARTD1.dmarx = STM32_DMA_STREAM(STM32_UART_USART1_RX_DMA_STREAM);
UARTD1.dmatx = STM32_DMA_STREAM(STM32_UART_USART1_TX_DMA_STREAM);
#endif
UARTD1.dmarx = NULL;
UARTD1.dmatx = NULL;
#if defined(STM32_USART1_NUMBER)
nvicEnableVector(STM32_USART1_NUMBER, STM32_UART_USART1_IRQ_PRIORITY);
#endif
@ -611,13 +606,8 @@ void uart_lld_init(void) {
UARTD2.usart = USART2;
UARTD2.clock = STM32_USART2CLK;
UARTD2.dmamode = STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE;
#if STM32_DMA_SUPPORTS_DMAMUX
UARTD2.dmarx = STM32_DMA_STREAM(STM32_UART_USART2_RX_DMA_CHANNEL);
UARTD2.dmatx = STM32_DMA_STREAM(STM32_UART_USART2_TX_DMA_CHANNEL);
#else
UARTD2.dmarx = STM32_DMA_STREAM(STM32_UART_USART2_RX_DMA_STREAM);
UARTD2.dmatx = STM32_DMA_STREAM(STM32_UART_USART2_TX_DMA_STREAM);
#endif
UARTD2.dmarx = NULL;
UARTD2.dmatx = NULL;
#if defined(STM32_USART2_NUMBER)
nvicEnableVector(STM32_USART2_NUMBER, STM32_UART_USART2_IRQ_PRIORITY);
#endif
@ -628,13 +618,8 @@ void uart_lld_init(void) {
UARTD3.usart = USART3;
UARTD3.clock = STM32_USART3CLK;
UARTD3.dmamode = STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE;
#if STM32_DMA_SUPPORTS_DMAMUX
UARTD3.dmarx = STM32_DMA_STREAM(STM32_UART_USART3_RX_DMA_CHANNEL);
UARTD3.dmatx = STM32_DMA_STREAM(STM32_UART_USART3_TX_DMA_CHANNEL);
#else
UARTD3.dmarx = STM32_DMA_STREAM(STM32_UART_USART3_RX_DMA_STREAM);
UARTD3.dmatx = STM32_DMA_STREAM(STM32_UART_USART3_TX_DMA_STREAM);
#endif
UARTD3.dmarx = NULL;
UARTD3.dmatx = NULL;
#if defined(STM32_USART3_NUMBER)
nvicEnableVector(STM32_USART3_NUMBER, STM32_UART_USART3_IRQ_PRIORITY);
#endif
@ -645,13 +630,8 @@ void uart_lld_init(void) {
UARTD4.usart = UART4;
UARTD4.clock = STM32_UART4CLK;
UARTD4.dmamode = STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE;
#if STM32_DMA_SUPPORTS_DMAMUX
UARTD4.dmarx = STM32_DMA_STREAM(STM32_UART_UART4_RX_DMA_CHANNEL);
UARTD4.dmatx = STM32_DMA_STREAM(STM32_UART_UART4_TX_DMA_CHANNEL);
#else
UARTD4.dmarx = STM32_DMA_STREAM(STM32_UART_UART4_RX_DMA_STREAM);
UARTD4.dmatx = STM32_DMA_STREAM(STM32_UART_UART4_TX_DMA_STREAM);
#endif
UARTD4.dmarx = NULL;
UARTD4.dmatx = NULL;
#if defined(STM32_UART4_NUMBER)
nvicEnableVector(STM32_UART4_NUMBER, STM32_UART_UART4_IRQ_PRIORITY);
#endif
@ -662,13 +642,8 @@ void uart_lld_init(void) {
UARTD5.usart = UART5;
UARTD5.clock = STM32_UART5CLK;
UARTD5.dmamode = STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE;
#if STM32_DMA_SUPPORTS_DMAMUX
UARTD5.dmarx = STM32_DMA_STREAM(STM32_UART_UART5_RX_DMA_CHANNEL);
UARTD5.dmatx = STM32_DMA_STREAM(STM32_UART_UART5_TX_DMA_CHANNEL);
#else
UARTD5.dmarx = STM32_DMA_STREAM(STM32_UART_UART5_RX_DMA_STREAM);
UARTD5.dmatx = STM32_DMA_STREAM(STM32_UART_UART5_TX_DMA_STREAM);
#endif
UARTD5.dmarx = NULL;
UARTD5.dmatx = NULL;
#if defined(STM32_UART5_NUMBER)
nvicEnableVector(STM32_UART5_NUMBER, STM32_UART_UART5_IRQ_PRIORITY);
#endif
@ -679,13 +654,8 @@ void uart_lld_init(void) {
UARTD6.usart = USART6;
UARTD6.clock = STM32_USART6CLK;
UARTD6.dmamode = STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE;
#if STM32_DMA_SUPPORTS_DMAMUX
UARTD6.dmarx = STM32_DMA_STREAM(STM32_UART_USART6_RX_DMA_CHANNEL);
UARTD6.dmatx = STM32_DMA_STREAM(STM32_UART_USART6_TX_DMA_CHANNEL);
#else
UARTD6.dmarx = STM32_DMA_STREAM(STM32_UART_USART6_RX_DMA_STREAM);
UARTD6.dmatx = STM32_DMA_STREAM(STM32_UART_USART6_TX_DMA_STREAM);
#endif
UARTD6.dmarx = NULL;
UARTD6.dmatx = NULL;
#if defined(STM32_USART6_NUMBER)
nvicEnableVector(STM32_USART6_NUMBER, STM32_UART_USART6_IRQ_PRIORITY);
#endif
@ -696,13 +666,8 @@ void uart_lld_init(void) {
UARTD7.usart = UART7;
UARTD7.clock = STM32_UART7CLK;
UARTD7.dmamode = STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE;
#if STM32_DMA_SUPPORTS_DMAMUX
UARTD7.dmarx = STM32_DMA_STREAM(STM32_UART_UART7_RX_DMA_CHANNEL);
UARTD7.dmatx = STM32_DMA_STREAM(STM32_UART_UART7_TX_DMA_CHANNEL);
#else
UARTD7.dmarx = STM32_DMA_STREAM(STM32_UART_UART7_RX_DMA_STREAM);
UARTD7.dmatx = STM32_DMA_STREAM(STM32_UART_UART7_TX_DMA_STREAM);
#endif
UARTD7.dmarx = NULL;
UARTD7.dmatx = NULL;
#if defined(STM32_UART7_NUMBER)
nvicEnableVector(STM32_UART7_NUMBER, STM32_UART_UART7_IRQ_PRIORITY);
#endif
@ -713,13 +678,8 @@ void uart_lld_init(void) {
UARTD8.usart = UART8;
UARTD8.clock = STM32_UART8CLK;
UARTD8.dmamode = STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE;
#if STM32_DMA_SUPPORTS_DMAMUX
UARTD8.dmarx = STM32_DMA_STREAM(STM32_UART_UART8_RX_DMA_CHANNEL);
UARTD8.dmatx = STM32_DMA_STREAM(STM32_UART_UART8_TX_DMA_CHANNEL);
#else
UARTD8.dmarx = STM32_DMA_STREAM(STM32_UART_UART8_RX_DMA_STREAM);
UARTD8.dmatx = STM32_DMA_STREAM(STM32_UART_UART8_TX_DMA_STREAM);
#endif
UARTD8.dmarx = NULL;
UARTD8.dmatx = NULL;
#if defined(STM32_UART8_NUMBER)
nvicEnableVector(STM32_UART8_NUMBER, STM32_UART_UART8_IRQ_PRIORITY);
#endif
@ -746,17 +706,17 @@ void uart_lld_start(UARTDriver *uartp) {
if (uartp->state == UART_STOP) {
#if STM32_UART_USE_USART1
if (&UARTD1 == uartp) {
bool b;
b = dmaStreamAllocate(uartp->dmarx,
uartp->dmarx = dmaStreamAllocI(STM32_UART_USART1_RX_DMA_STREAM,
STM32_UART_USART1_IRQ_PRIORITY,
(stm32_dmaisr_t)uart_lld_serve_rx_end_irq,
(void *)uartp);
osalDbgAssert(!b, "stream already allocated");
b = dmaStreamAllocate(uartp->dmatx,
osalDbgAssert(uartp->dmarx != NULL, "unable to allocate stream");
uartp->dmatx = dmaStreamAllocI(STM32_UART_USART1_TX_DMA_STREAM,
STM32_UART_USART1_IRQ_PRIORITY,
(stm32_dmaisr_t)uart_lld_serve_tx_end_irq,
(void *)uartp);
osalDbgAssert(!b, "stream already allocated");
osalDbgAssert(uartp->dmatx != NULL, "unable to allocate stream");
rccEnableUSART1(true);
uartp->dmamode |= STM32_DMA_CR_CHSEL(USART1_RX_DMA_CHANNEL) |
STM32_DMA_CR_PL(STM32_UART_USART1_DMA_PRIORITY);
@ -769,17 +729,17 @@ void uart_lld_start(UARTDriver *uartp) {
#if STM32_UART_USE_USART2
if (&UARTD2 == uartp) {
bool b;
b = dmaStreamAllocate(uartp->dmarx,
uartp->dmarx = dmaStreamAllocI(STM32_UART_USART2_RX_DMA_STREAM,
STM32_UART_USART2_IRQ_PRIORITY,
(stm32_dmaisr_t)uart_lld_serve_rx_end_irq,
(void *)uartp);
osalDbgAssert(!b, "stream already allocated");
b = dmaStreamAllocate(uartp->dmatx,
osalDbgAssert(uartp->dmarx != NULL, "unable to allocate stream");
uartp->dmatx = dmaStreamAllocI(STM32_UART_USART2_TX_DMA_STREAM,
STM32_UART_USART2_IRQ_PRIORITY,
(stm32_dmaisr_t)uart_lld_serve_tx_end_irq,
(void *)uartp);
osalDbgAssert(!b, "stream already allocated");
osalDbgAssert(uartp->dmatx != NULL, "unable to allocate stream");
rccEnableUSART2(true);
uartp->dmamode |= STM32_DMA_CR_CHSEL(USART2_RX_DMA_CHANNEL) |
STM32_DMA_CR_PL(STM32_UART_USART2_DMA_PRIORITY);
@ -792,17 +752,17 @@ void uart_lld_start(UARTDriver *uartp) {
#if STM32_UART_USE_USART3
if (&UARTD3 == uartp) {
bool b;
b = dmaStreamAllocate(uartp->dmarx,
uartp->dmarx = dmaStreamAllocI(STM32_UART_USART3_RX_DMA_STREAM,
STM32_UART_USART3_IRQ_PRIORITY,
(stm32_dmaisr_t)uart_lld_serve_rx_end_irq,
(void *)uartp);
osalDbgAssert(!b, "stream already allocated");
b = dmaStreamAllocate(uartp->dmatx,
osalDbgAssert(uartp->dmarx != NULL, "unable to allocate stream");
uartp->dmatx = dmaStreamAllocI(STM32_UART_USART3_TX_DMA_STREAM,
STM32_UART_USART3_IRQ_PRIORITY,
(stm32_dmaisr_t)uart_lld_serve_tx_end_irq,
(void *)uartp);
osalDbgAssert(!b, "stream already allocated");
osalDbgAssert(uartp->dmatx != NULL, "unable to allocate stream");
rccEnableUSART3(true);
uartp->dmamode |= STM32_DMA_CR_CHSEL(USART3_RX_DMA_CHANNEL) |
STM32_DMA_CR_PL(STM32_UART_USART3_DMA_PRIORITY);
@ -815,17 +775,17 @@ void uart_lld_start(UARTDriver *uartp) {
#if STM32_UART_USE_UART4
if (&UARTD4 == uartp) {
bool b;
b = dmaStreamAllocate(uartp->dmarx,
uartp->dmarx = dmaStreamAllocI(STM32_UART_UART4_RX_DMA_STREAM,
STM32_UART_UART4_IRQ_PRIORITY,
(stm32_dmaisr_t)uart_lld_serve_rx_end_irq,
(void *)uartp);
osalDbgAssert(!b, "stream already allocated");
b = dmaStreamAllocate(uartp->dmatx,
osalDbgAssert(uartp->dmarx != NULL, "unable to allocate stream");
uartp->dmatx = dmaStreamAllocI(STM32_UART_UART4_TX_DMA_STREAM,
STM32_UART_UART4_IRQ_PRIORITY,
(stm32_dmaisr_t)uart_lld_serve_tx_end_irq,
(void *)uartp);
osalDbgAssert(!b, "stream already allocated");
osalDbgAssert(uartp->dmatx != NULL, "unable to allocate stream");
rccEnableUART4(true);
uartp->dmamode |= STM32_DMA_CR_CHSEL(UART4_RX_DMA_CHANNEL) |
STM32_DMA_CR_PL(STM32_UART_UART4_DMA_PRIORITY);
@ -838,17 +798,17 @@ void uart_lld_start(UARTDriver *uartp) {
#if STM32_UART_USE_UART5
if (&UARTD5 == uartp) {
bool b;
b = dmaStreamAllocate(uartp->dmarx,
uartp->dmarx = dmaStreamAllocI(STM32_UART_UART5_RX_DMA_STREAM,
STM32_UART_UART5_IRQ_PRIORITY,
(stm32_dmaisr_t)uart_lld_serve_rx_end_irq,
(void *)uartp);
osalDbgAssert(!b, "stream already allocated");
b = dmaStreamAllocate(uartp->dmatx,
osalDbgAssert(uartp->dmarx != NULL, "unable to allocate stream");
uartp->dmatx = dmaStreamAllocI(STM32_UART_UART5_TX_DMA_STREAM,
STM32_UART_UART5_IRQ_PRIORITY,
(stm32_dmaisr_t)uart_lld_serve_tx_end_irq,
(void *)uartp);
osalDbgAssert(!b, "stream already allocated");
osalDbgAssert(uartp->dmatx != NULL, "unable to allocate stream");
rccEnableUART5(true);
uartp->dmamode |= STM32_DMA_CR_CHSEL(UART5_RX_DMA_CHANNEL) |
STM32_DMA_CR_PL(STM32_UART_UART5_DMA_PRIORITY);
@ -861,17 +821,17 @@ void uart_lld_start(UARTDriver *uartp) {
#if STM32_UART_USE_USART6
if (&UARTD6 == uartp) {
bool b;
b = dmaStreamAllocate(uartp->dmarx,
uartp->dmarx = dmaStreamAllocI(STM32_UART_USART6_RX_DMA_STREAM,
STM32_UART_USART6_IRQ_PRIORITY,
(stm32_dmaisr_t)uart_lld_serve_rx_end_irq,
(void *)uartp);
osalDbgAssert(!b, "stream already allocated");
b = dmaStreamAllocate(uartp->dmatx,
osalDbgAssert(uartp->dmarx != NULL, "unable to allocate stream");
uartp->dmatx = dmaStreamAllocI(STM32_UART_USART6_TX_DMA_STREAM,
STM32_UART_USART6_IRQ_PRIORITY,
(stm32_dmaisr_t)uart_lld_serve_tx_end_irq,
(void *)uartp);
osalDbgAssert(!b, "stream already allocated");
osalDbgAssert(uartp->dmatx != NULL, "unable to allocate stream");
rccEnableUSART6(true);
uartp->dmamode |= STM32_DMA_CR_CHSEL(USART6_RX_DMA_CHANNEL) |
STM32_DMA_CR_PL(STM32_UART_USART6_DMA_PRIORITY);
@ -884,17 +844,17 @@ void uart_lld_start(UARTDriver *uartp) {
#if STM32_UART_USE_UART7
if (&UARTD7 == uartp) {
bool b;
b = dmaStreamAllocate(uartp->dmarx,
uartp->dmarx = dmaStreamAllocI(STM32_UART_UART7_RX_DMA_STREAM,
STM32_UART_UART7_IRQ_PRIORITY,
(stm32_dmaisr_t)uart_lld_serve_rx_end_irq,
(void *)uartp);
osalDbgAssert(!b, "stream already allocated");
b = dmaStreamAllocate(uartp->dmatx,
osalDbgAssert(uartp->dmarx != NULL, "unable to allocate stream");
uartp->dmatx = dmaStreamAllocI(STM32_UART_UART7_TX_DMA_STREAM,
STM32_UART_UART7_IRQ_PRIORITY,
(stm32_dmaisr_t)uart_lld_serve_tx_end_irq,
(void *)uartp);
osalDbgAssert(!b, "stream already allocated");
osalDbgAssert(uartp->dmatx != NULL, "unable to allocate stream");
rccEnableUART7(true);
uartp->dmamode |= STM32_DMA_CR_CHSEL(UART7_RX_DMA_CHANNEL) |
STM32_DMA_CR_PL(STM32_UART_UART7_DMA_PRIORITY);
@ -907,17 +867,17 @@ void uart_lld_start(UARTDriver *uartp) {
#if STM32_UART_USE_UART8
if (&UARTD8 == uartp) {
bool b;
b = dmaStreamAllocate(uartp->dmarx,
uartp->dmarx = dmaStreamAllocI(STM32_UART_UART8_RX_DMA_STREAM,
STM32_UART_UART8_IRQ_PRIORITY,
(stm32_dmaisr_t)uart_lld_serve_rx_end_irq,
(void *)uartp);
osalDbgAssert(!b, "stream already allocated");
b = dmaStreamAllocate(uartp->dmatx,
osalDbgAssert(uartp->dmarx != NULL, "unable to allocate stream");
uartp->dmatx = dmaStreamAllocI(STM32_UART_UART8_TX_DMA_STREAM,
STM32_UART_UART8_IRQ_PRIORITY,
(stm32_dmaisr_t)uart_lld_serve_tx_end_irq,
(void *)uartp);
osalDbgAssert(!b, "stream already allocated");
osalDbgAssert(uartp->dmatx != NULL, "unable to allocate stream");
rccEnableUART8(true);
uartp->dmamode |= STM32_DMA_CR_CHSEL(UART8_RX_DMA_CHANNEL) |
STM32_DMA_CR_PL(STM32_UART_UART8_DMA_PRIORITY);
@ -953,8 +913,10 @@ void uart_lld_stop(UARTDriver *uartp) {
if (uartp->state == UART_READY) {
usart_stop(uartp);
dmaStreamRelease(uartp->dmarx);
dmaStreamRelease(uartp->dmatx);
dmaStreamFreeI(uartp->dmarx);
dmaStreamFreeI(uartp->dmatx);
uartp->dmarx = NULL;
uartp->dmatx = NULL;
#if STM32_UART_USE_USART1
if (&UARTD1 == uartp) {

218
os/hal/ports/STM32/LLD/USARTv2/hal_uart_lld.h
View File

@ -355,6 +355,9 @@
#error "Invalid IRQ priority assigned to UART8"
#endif
#endif /* !defined(STM32_USART3_8_HANDLER) */
/* Check on DMA priorities.*/
#if STM32_UART_USE_USART1 && \
!STM32_DMA_IS_VALID_PRIORITY(STM32_UART_USART1_DMA_PRIORITY)
#error "Invalid DMA priority assigned to USART1"
@ -390,140 +393,11 @@
#error "Invalid DMA priority assigned to UART7"
#endif
#endif /* !defined(STM32_USART3_8_HANDLER) */
#if STM32_UART_USE_UART8 && \
!STM32_DMA_IS_VALID_PRIORITY(STM32_UART_UART8_DMA_PRIORITY)
#error "Invalid DMA priority assigned to UART8"
#endif
/* Devices with DMAMUX require a different kind of check.*/
#if STM32_DMA_SUPPORTS_DMAMUX
/* Check on the presence of the DMA channel settings in mcuconf.h.*/
#if STM32_UART_USE_USART1 && (!defined(STM32_UART_USART1_RX_DMA_CHANNEL) || \
!defined(STM32_UART_USART1_TX_DMA_CHANNEL))
#error "USART1 DMA channels not defined"
#endif
#if STM32_UART_USE_USART2 && (!defined(STM32_UART_USART2_RX_DMA_CHANNEL) || \
!defined(STM32_UART_USART2_TX_DMA_CHANNEL))
#error "USART2 DMA channels not defined"
#endif
#if STM32_UART_USE_USART3 && (!defined(STM32_UART_USART3_RX_DMA_CHANNEL) || \
!defined(STM32_UART_USART3_TX_DMA_CHANNEL))
#error "USART3 DMA channels not defined"
#endif
#if STM32_UART_USE_UART4 && (!defined(STM32_UART_UART4_RX_DMA_CHANNEL) || \
!defined(STM32_UART_UART4_TX_DMA_CHANNEL))
#error "UART4 DMA channels not defined"
#endif
#if STM32_UART_USE_UART5 && (!defined(STM32_UART_UART5_RX_DMA_CHANNEL) || \
!defined(STM32_UART_UART5_TX_DMA_CHANNEL))
#error "UART5 DMA channels not defined"
#endif
#if STM32_UART_USE_USART6 && (!defined(STM32_UART_USART6_RX_DMA_CHANNEL) || \
!defined(STM32_UART_USART6_TX_DMA_CHANNEL))
#error "USART6 DMA channels not defined"
#endif
#if STM32_UART_USE_UART7 && (!defined(STM32_UART_UART7_RX_DMA_CHANNEL) || \
!defined(STM32_UART_UART7_TX_DMA_CHANNEL))
#error "UART7 DMA channels not defined"
#endif
#if STM32_UART_USE_UART8 && (!defined(STM32_UART_UART8_RX_DMA_CHANNEL) || \
!defined(STM32_UART_UART8_TX_DMA_CHANNEL))
#error "UART8 DMA channels not defined"
#endif
/* Check on the validity of the assigned DMA channels.*/
#if STM32_UART_USE_USART1 && \
!STM32_DMA_IS_VALID_CHANNEL(STM32_UART_USART1_RX_DMA_CHANNEL)
#error "Invalid DMA channel assigned to USART1 RX"
#endif
#if STM32_UART_USE_USART1 && \
!STM32_DMA_IS_VALID_CHANNEL(STM32_UART_USART1_TX_DMA_CHANNEL)
#error "Invalid DMA channel assigned to USART1 TX"
#endif
#if STM32_UART_USE_USART2 && \
!STM32_DMA_IS_VALID_CHANNEL(STM32_UART_USART2_RX_DMA_CHANNEL)
#error "Invalid DMA channel assigned to USART2 RX"
#endif
#if STM32_UART_USE_USART2 && \
!STM32_DMA_IS_VALID_CHANNEL(STM32_UART_USART2_TX_DMA_CHANNEL)
#error "Invalid DMA channel assigned to USART2 TX"
#endif
#if STM32_UART_USE_USART3 && \
!STM32_DMA_IS_VALID_CHANNEL(STM32_UART_USART3_RX_DMA_CHANNEL)
#error "Invalid DMA channel assigned to USART3 RX"
#endif
#if STM32_UART_USE_USART3 && \
!STM32_DMA_IS_VALID_CHANNEL(STM32_UART_USART3_TX_DMA_CHANNEL)
#error "Invalid DMA channel assigned to USART3 TX"
#endif
#if STM32_UART_USE_UART4 && \
!STM32_DMA_IS_VALID_CHANNEL(STM32_UART_UART4_RX_DMA_CHANNEL)
#error "Invalid DMA channel assigned to UART4 RX"
#endif
#if STM32_UART_USE_UART4 && \
!STM32_DMA_IS_VALID_CHANNEL(STM32_UART_UART4_TX_DMA_CHANNEL)
#error "Invalid DMA channel assigned to UART4 TX"
#endif
#if STM32_UART_USE_UART5 && \
!STM32_DMA_IS_VALID_CHANNEL(STM32_UART_UART5_RX_DMA_CHANNEL)
#error "Invalid DMA channel assigned to UART5 RX"
#endif
#if STM32_UART_USE_UART5 && \
!STM32_DMA_IS_VALID_CHANNEL(STM32_UART_UART5_TX_DMA_CHANNEL)
#error "Invalid DMA channel assigned to UART5 TX"
#endif
#if STM32_UART_USE_USART6 && \
!STM32_DMA_IS_VALID_CHANNEL(STM32_UART_USART6_RX_DMA_CHANNEL)
#error "Invalid DMA channel assigned to USART6 RX"
#endif
#if STM32_UART_USE_USART6 && \
!STM32_DMA_IS_VALID_CHANNEL(STM32_UART_USART6_TX_DMA_CHANNEL)
#error "Invalid DMA channel assigned to USART6 TX"
#endif
#if STM32_UART_USE_UART7 && \
!STM32_DMA_IS_VALID_CHANNEL(STM32_UART_UART7_RX_DMA_CHANNEL)
#error "Invalid DMA channel assigned to UART7 RX"
#endif
#if STM32_UART_USE_UART7 && \
!STM32_DMA_IS_VALID_CHANNEL(STM32_UART_UART7_TX_DMA_CHANNEL)
#error "Invalid DMA channel assigned to UART7 TX"
#endif
#if STM32_UART_USE_UART8 && \
!STM32_DMA_IS_VALID_CHANNEL(STM32_UART_UART8_RX_DMA_CHANNEL)
#error "Invalid DMA channel assigned to UART8 RX"
#endif
#if STM32_UART_USE_UART8 && \
!STM32_DMA_IS_VALID_CHANNEL(STM32_UART_UART8_TX_DMA_CHANNEL)
#error "Invalid DMA channel assigned to UART8 TX"
#endif
#else /* !STM32_DMA_SUPPORTS_DMAMUX */
/* Check on the presence of the DMA streams settings in mcuconf.h.*/
#if STM32_UART_USE_USART1 && (!defined(STM32_UART_USART1_RX_DMA_STREAM) || \
!defined(STM32_UART_USART1_TX_DMA_STREAM))
@ -565,6 +439,90 @@
#error "UART8 DMA streams not defined"
#endif
/* Check on the validity of the assigned DMA channels.*/
#if STM32_UART_USE_USART1 && \
!STM32_DMA_IS_VALID_STREAM(STM32_UART_USART1_RX_DMA_STREAM)
#error "Invalid DMA channel assigned to USART1 RX"
#endif
#if STM32_UART_USE_USART1 && \
!STM32_DMA_IS_VALID_STREAM(STM32_UART_USART1_TX_DMA_STREAM)
#error "Invalid DMA channel assigned to USART1 TX"
#endif
#if STM32_UART_USE_USART2 && \
!STM32_DMA_IS_VALID_STREAM(STM32_UART_USART2_RX_DMA_STREAM)
#error "Invalid DMA channel assigned to USART2 RX"
#endif
#if STM32_UART_USE_USART2 && \
!STM32_DMA_IS_VALID_STREAM(STM32_UART_USART2_TX_DMA_STREAM)
#error "Invalid DMA channel assigned to USART2 TX"
#endif
#if STM32_UART_USE_USART3 && \
!STM32_DMA_IS_VALID_STREAM(STM32_UART_USART3_RX_DMA_STREAM)
#error "Invalid DMA channel assigned to USART3 RX"
#endif
#if STM32_UART_USE_USART3 && \
!STM32_DMA_IS_VALID_STREAM(STM32_UART_USART3_TX_DMA_STREAM)
#error "Invalid DMA channel assigned to USART3 TX"
#endif
#if STM32_UART_USE_UART4 && \
!STM32_DMA_IS_VALID_STREAM(STM32_UART_UART4_RX_DMA_STREAM)
#error "Invalid DMA channel assigned to UART4 RX"
#endif
#if STM32_UART_USE_UART4 && \
!STM32_DMA_IS_VALID_STREAM(STM32_UART_UART4_TX_DMA_STREAM)
#error "Invalid DMA channel assigned to UART4 TX"
#endif
#if STM32_UART_USE_UART5 && \
!STM32_DMA_IS_VALID_STREAM(STM32_UART_UART5_RX_DMA_STREAM)
#error "Invalid DMA channel assigned to UART5 RX"
#endif
#if STM32_UART_USE_UART5 && \
!STM32_DMA_IS_VALID_STREAM(STM32_UART_UART5_TX_DMA_STREAM)
#error "Invalid DMA channel assigned to UART5 TX"
#endif
#if STM32_UART_USE_USART6 && \
!STM32_DMA_IS_VALID_STREAM(STM32_UART_USART6_RX_DMA_STREAM)
#error "Invalid DMA channel assigned to USART6 RX"
#endif
#if STM32_UART_USE_USART6 && \
!STM32_DMA_IS_VALID_STREAM(STM32_UART_USART6_TX_DMA_STREAM)
#error "Invalid DMA channel assigned to USART6 TX"
#endif
#if STM32_UART_USE_UART7 && \
!STM32_DMA_IS_VALID_STREAM(STM32_UART_UART7_RX_DMA_STREAM)
#error "Invalid DMA channel assigned to UART7 RX"
#endif
#if STM32_UART_USE_UART7 && \
!STM32_DMA_IS_VALID_STREAM(STM32_UART_UART7_TX_DMA_STREAM)
#error "Invalid DMA channel assigned to UART7 TX"
#endif
#if STM32_UART_USE_UART8 && \
!STM32_DMA_IS_VALID_STREAM(STM32_UART_UART8_RX_DMA_STREAM)
#error "Invalid DMA channel assigned to UART8 RX"
#endif
#if STM32_UART_USE_UART8 && \
!STM32_DMA_IS_VALID_STREAM(STM32_UART_UART8_TX_DMA_STREAM)
#error "Invalid DMA channel assigned to UART8 TX"
#endif
/* Devices without DMAMUX require an additional check.*/
#if STM32_ADVANCED_DMA && !STM32_DMA_SUPPORTS_DMAMUX
/* Check on the validity of the assigned DMA channels.*/
#if STM32_UART_USE_USART1 && \
!STM32_DMA_IS_VALID_ID(STM32_UART_USART1_RX_DMA_STREAM, \
@ -662,7 +620,7 @@
#error "invalid DMA stream associated to UART8 TX"
#endif
#endif /* !STM32_DMA_SUPPORTS_DMAMUX */
#endif /* STM32_ADVANCED_DMA && !STM32_DMA_SUPPORTS_DMAMUX */
#if !defined(STM32_DMA_REQUIRED)
#define STM32_DMA_REQUIRED

12
os/hal/ports/STM32/STM32F1xx/hal_adc_lld.c
View File

@ -92,7 +92,7 @@ void adc_lld_init(void) {
/* Driver initialization.*/
adcObjectInit(&ADCD1);
ADCD1.adc = ADC1;
ADCD1.dmastp = STM32_DMA1_STREAM1;
ADCD1.dmastp = NULL;
ADCD1.dmamode = STM32_DMA_CR_PL(STM32_ADC_ADC1_DMA_PRIORITY) |
STM32_DMA_CR_MSIZE_HWORD | STM32_DMA_CR_PSIZE_HWORD |
STM32_DMA_CR_MINC | STM32_DMA_CR_TCIE |
@ -132,12 +132,11 @@ void adc_lld_start(ADCDriver *adcp) {
if (adcp->state == ADC_STOP) {
#if STM32_ADC_USE_ADC1
if (&ADCD1 == adcp) {
bool b;
b = dmaStreamAllocate(adcp->dmastp,
adcp->dmastp = dmaStreamAllocI(STM32_DMA_STREAM_ID(1, 1),
STM32_ADC_ADC1_IRQ_PRIORITY,
(stm32_dmaisr_t)adc_lld_serve_rx_interrupt,
(void *)adcp);
osalDbgAssert(!b, "stream already allocated");
osalDbgAssert(adcp->dmastp != NULL, "unable to allocate stream");
dmaStreamSetPeripheral(adcp->dmastp, &ADC1->DR);
rccEnableADC1(true);
}
@ -165,7 +164,10 @@ void adc_lld_stop(ADCDriver *adcp) {
if (&ADCD1 == adcp) {
ADC1->CR1 = 0;
ADC1->CR2 = 0;
dmaStreamRelease(adcp->dmastp);
dmaStreamFreeI(adcp->dmastp);
adcp->dmastp = NULL;
rccDisableADC1();
}
#endif

31
os/hal/ports/STM32/STM32F37x/hal_adc_lld.c
View File

@ -314,7 +314,7 @@ void adc_lld_init(void) {
#if STM32_ADC_USE_SDADC
ADCD1.sdadc = NULL;
#endif
ADCD1.dmastp = STM32_DMA1_STREAM1;
ADCD1.dmastp = NULL;
ADCD1.dmamode = STM32_DMA_CR_CHSEL(ADC1_DMA_CHANNEL) |
STM32_DMA_CR_PL(STM32_ADC_ADC1_DMA_PRIORITY) |
STM32_DMA_CR_DIR_P2M |
@ -331,7 +331,7 @@ void adc_lld_init(void) {
SDADCD1.adc = NULL;
#endif
SDADCD1.sdadc = SDADC1;
SDADCD1.dmastp = STM32_DMA2_STREAM3;
SDADCD1.dmastp = NULL;
SDADCD1.dmamode = STM32_DMA_CR_CHSEL(SDADC1_DMA_CHANNEL) |
STM32_DMA_CR_PL(STM32_ADC_SDADC1_DMA_PRIORITY) |
STM32_DMA_CR_DIR_P2M |
@ -348,7 +348,7 @@ void adc_lld_init(void) {
SDADCD2.adc = NULL;
#endif
SDADCD2.sdadc = SDADC2;
SDADCD2.dmastp = STM32_DMA2_STREAM4;
SDADCD2.dmastp = NULL;
SDADCD2.dmamode = STM32_DMA_CR_CHSEL(SDADC2_DMA_CHANNEL) |
STM32_DMA_CR_PL(STM32_ADC_SDADC2_DMA_PRIORITY) |
STM32_DMA_CR_DIR_P2M |
@ -365,7 +365,7 @@ void adc_lld_init(void) {
SDADCD3.adc = NULL;
#endif
SDADCD3.sdadc = SDADC3;
SDADCD3.dmastp = STM32_DMA2_STREAM5;
SDADCD3.dmastp = NULL;
SDADCD3.dmamode = STM32_DMA_CR_CHSEL(SDADC3_DMA_CHANNEL) |
STM32_DMA_CR_PL(STM32_ADC_SDADC3_DMA_PRIORITY) |
STM32_DMA_CR_DIR_P2M |
@ -392,11 +392,12 @@ void adc_lld_start(ADCDriver *adcp) {
if (adcp->state == ADC_STOP) {
#if STM32_ADC_USE_ADC1
if (&ADCD1 == adcp) {
bool b = dmaStreamAllocate(adcp->dmastp,
adcp->dmastp = dmaStreamAllocI(STM32_DMA_STREAM_ID(1, 1),
STM32_ADC_ADC1_DMA_IRQ_PRIORITY,
(stm32_dmaisr_t)adc_lld_serve_dma_interrupt,
(void *)adcp);
osalDbgAssert(!b, "stream already allocated");
osalDbgAssert(adcp->dmastp != NULL, "unable to allocate stream");
dmaStreamSetPeripheral(adcp->dmastp, &ADC1->DR);
rccEnableADC1(true);
}
@ -404,11 +405,12 @@ void adc_lld_start(ADCDriver *adcp) {
#if STM32_ADC_USE_SDADC1
if (&SDADCD1 == adcp) {
bool b = dmaStreamAllocate(adcp->dmastp,
adcp->dmastp = dmaStreamAllocI(STM32_DMA_STREAM_ID(2, 3),
STM32_ADC_SDADC1_DMA_IRQ_PRIORITY,
(stm32_dmaisr_t)adc_lld_serve_dma_interrupt,
(void *)adcp);
osalDbgAssert(!b, "stream already allocated");
osalDbgAssert(adcp->dmastp != NULL, "unable to allocate stream");
dmaStreamSetPeripheral(adcp->dmastp, &SDADC1->JDATAR);
rccEnableSDADC1(true);
PWR->CR |= PWR_CR_SDADC1EN;
@ -421,11 +423,12 @@ void adc_lld_start(ADCDriver *adcp) {
#if STM32_ADC_USE_SDADC2
if (&SDADCD2 == adcp) {
bool b = dmaStreamAllocate(adcp->dmastp,
adcp->dmastp = dmaStreamAllocI(STM32_DMA_STREAM_ID(2, 4),
STM32_ADC_SDADC2_DMA_IRQ_PRIORITY,
(stm32_dmaisr_t)adc_lld_serve_dma_interrupt,
(void *)adcp);
osalDbgAssert(!b, "stream already allocated");
osalDbgAssert(adcp->dmastp != NULL, "unable to allocate stream");
dmaStreamSetPeripheral(adcp->dmastp, &SDADC2->JDATAR);
rccEnableSDADC2(true);
PWR->CR |= PWR_CR_SDADC2EN;
@ -438,11 +441,12 @@ void adc_lld_start(ADCDriver *adcp) {
#if STM32_ADC_USE_SDADC3
if (&SDADCD3 == adcp) {
bool b = dmaStreamAllocate(adcp->dmastp,
adcp->dmastp = dmaStreamAllocI(STM32_DMA_STREAM_ID(2, 5),
STM32_ADC_SDADC3_DMA_IRQ_PRIORITY,
(stm32_dmaisr_t)adc_lld_serve_dma_interrupt,
(void *)adcp);
osalDbgAssert(!b, "stream already allocated");
osalDbgAssert(adcp->dmastp != NULL, "unable to allocate stream");
dmaStreamSetPeripheral(adcp->dmastp, &SDADC3->JDATAR);
rccEnableSDADC3(true);
PWR->CR |= PWR_CR_SDADC3EN;
@ -468,7 +472,8 @@ void adc_lld_stop(ADCDriver *adcp) {
/* If in ready state then disables the ADC clock.*/
if (adcp->state == ADC_READY) {
dmaStreamRelease(adcp->dmastp);
dmaStreamFreeI(adcp->dmastp);
adcp->dmastp = NULL;
#if STM32_ADC_USE_ADC1
if (&ADCD1 == adcp) {

11
os/hal/ports/STM32/STM32L1xx/hal_adc_lld.c
View File

@ -123,7 +123,7 @@ void adc_lld_init(void) {
/* Driver initialization.*/
adcObjectInit(&ADCD1);
ADCD1.adc = ADC1;
ADCD1.dmastp = STM32_DMA1_STREAM1;
ADCD1.dmastp = NULL;
ADCD1.dmamode = STM32_DMA_CR_PL(STM32_ADC_ADC1_DMA_PRIORITY) |
STM32_DMA_CR_DIR_P2M |
STM32_DMA_CR_MSIZE_HWORD | STM32_DMA_CR_PSIZE_HWORD |
@ -149,11 +149,12 @@ void adc_lld_start(ADCDriver *adcp) {
if (adcp->state == ADC_STOP) {
#if STM32_ADC_USE_ADC1
if (&ADCD1 == adcp) {
bool b = dmaStreamAllocate(adcp->dmastp,
adcp->dmastp = dmaStreamAllocI(STM32_DMA_STREAM_ID(1, 1),
STM32_ADC_ADC1_DMA_IRQ_PRIORITY,
(stm32_dmaisr_t)adc_lld_serve_rx_interrupt,
(void *)adcp);
osalDbgAssert(!b, "stream already allocated");
osalDbgAssert(adcp->dmastp != NULL, "unable to allocate stream");
dmaStreamSetPeripheral(adcp->dmastp, &ADC1->DR);
rccEnableADC1(true);
}
@ -180,7 +181,9 @@ void adc_lld_stop(ADCDriver *adcp) {
/* If in ready state then disables the ADC clock and analog part.*/
if (adcp->state == ADC_READY) {
dmaStreamRelease(adcp->dmastp);
dmaStreamFreeI(adcp->dmastp);
adcp->dmastp = NULL;
adcp->adc->CR1 = 0;
adcp->adc->CR2 = 0;

4
os/hal/src/hal_serial_usb.c
View File

@ -310,6 +310,10 @@ void sduStop(SerialUSBDriver *sdup) {
*/
void sduSuspendHookI(SerialUSBDriver *sdup) {
/* Avoiding events spam.*/
if(bqIsSuspendedX(&sdup->ibqueue) && bqIsSuspendedX(&sdup->obqueue)) {
return;
}
chnAddFlagsI(sdup, CHN_DISCONNECTED);
bqSuspendI(&sdup->ibqueue);
bqSuspendI(&sdup->obqueue);

3
readme.txt
View File

@ -75,8 +75,7 @@
*****************************************************************************
*** Next ***
- NEW: STM32H7xx port reworked to support dynamic DMA allocation, modified
DACv1, SPIv3 and I2Cv3.
- NEW: STM32H7xx and STM32L4+ ports reworked to support dynamic DMA allocation.
- NEW: Both DMAv1 and DMAv2 have been reworked to support DMAMUX, DMAv3 has
been removed. In addition, both drivers are now able to support dynamic
channel allocation.

4
testhal/STM32/STM32F4xx/DMA_STORM/main.c
View File

@ -187,9 +187,9 @@ int main(void) {
chThdCreateStatic(waSPI3, sizeof(waSPI3), NORMALPRIO + 1, spi_thread, &SPID3);
/* Allocating two DMA2 streams for memory copy operations.*/
if (dmaStreamAllocate(STM32_DMA2_STREAM6, 0, NULL, NULL))
if (dmaStreamAlloc(STM32_DMA_STREAM_ID(2, 6), 0, NULL, NULL) == NULL)
chSysHalt("DMA already in use");
if (dmaStreamAllocate(STM32_DMA2_STREAM7, 0, NULL, NULL))
if (dmaStreamAlloc(STM32_DMA_STREAM_ID(2, 7), 0, NULL, NULL) == NULL)
chSysHalt("DMA already in use");
for (i = 0; i < sizeof (patterns1); i++)
patterns1[i] = (uint8_t)i;

82
testhal/STM32/multi/ADC/cfg/stm32h743_nucleo144/mcuconf.h
View File

@ -185,8 +185,8 @@
#define STM32_ADC_COMPACT_SAMPLES FALSE
#define STM32_ADC_USE_ADC12 TRUE
#define STM32_ADC_USE_ADC3 TRUE
#define STM32_ADC_ADC12_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY
#define STM32_ADC_ADC3_BDMA_CHANNEL STM32_BDMA_STREAM_ID_ANY
#define STM32_ADC_ADC12_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_ADC_ADC3_BDMA_STREAM STM32_BDMA_STREAM_ID_ANY
#define STM32_ADC_ADC12_DMA_PRIORITY 2
#define STM32_ADC_ADC3_DMA_PRIORITY 2
#define STM32_ADC_ADC12_IRQ_PRIORITY 5
@ -214,8 +214,8 @@
#define STM32_DAC_DAC1_CH2_IRQ_PRIORITY 10
#define STM32_DAC_DAC1_CH1_DMA_PRIORITY 2
#define STM32_DAC_DAC1_CH2_DMA_PRIORITY 2
#define STM32_DAC_DAC1_CH1_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY
#define STM32_DAC_DAC1_CH2_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY
#define STM32_DAC_DAC1_CH1_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_DAC_DAC1_CH2_DMA_STREAM STM32_DMA_STREAM_ID_ANY
/*
* GPT driver system settings.
@ -253,14 +253,14 @@
#define STM32_I2C_USE_I2C3 FALSE
#define STM32_I2C_USE_I2C4 FALSE
#define STM32_I2C_BUSY_TIMEOUT 50
#define STM32_I2C_I2C1_RX_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY
#define STM32_I2C_I2C1_TX_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY
#define STM32_I2C_I2C2_RX_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY
#define STM32_I2C_I2C2_TX_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY
#define STM32_I2C_I2C3_RX_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY
#define STM32_I2C_I2C3_TX_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY
#define STM32_I2C_I2C4_RX_BDMA_CHANNEL STM32_BDMA_STREAM_ID_ANY
#define STM32_I2C_I2C4_TX_BDMA_CHANNEL STM32_BDMA_STREAM_ID_ANY
#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_I2C_I2C4_RX_BDMA_STREAM STM32_BDMA_STREAM_ID_ANY
#define STM32_I2C_I2C4_TX_BDMA_STREAM STM32_BDMA_STREAM_ID_ANY
#define STM32_I2C_I2C1_IRQ_PRIORITY 5
#define STM32_I2C_I2C2_IRQ_PRIORITY 5
#define STM32_I2C_I2C3_IRQ_PRIORITY 5
@ -335,7 +335,7 @@
#define STM32_SDC_SDMMC_WRITE_TIMEOUT 1000
#define STM32_SDC_SDMMC_READ_TIMEOUT 1000
#define STM32_SDC_SDMMC_CLOCK_DELAY 10
#define STM32_SDC_SDMMC1_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY
#define STM32_SDC_SDMMC1_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_SDC_SDMMC1_DMA_PRIORITY 3
#define STM32_SDC_SDMMC1_IRQ_PRIORITY 9
@ -368,18 +368,18 @@
#define STM32_SPI_USE_SPI4 FALSE
#define STM32_SPI_USE_SPI5 FALSE
#define STM32_SPI_USE_SPI6 FALSE
#define STM32_SPI_SPI1_RX_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY
#define STM32_SPI_SPI1_TX_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY
#define STM32_SPI_SPI2_RX_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY
#define STM32_SPI_SPI2_TX_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY
#define STM32_SPI_SPI3_RX_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY
#define STM32_SPI_SPI3_TX_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY
#define STM32_SPI_SPI4_RX_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY
#define STM32_SPI_SPI4_TX_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY
#define STM32_SPI_SPI5_RX_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY
#define STM32_SPI_SPI5_TX_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY
#define STM32_SPI_SPI6_RX_BDMA_CHANNEL STM32_BDMA_STREAM_ID_ANY
#define STM32_SPI_SPI6_TX_BDMA_CHANNEL STM32_BDMA_STREAM_ID_ANY
#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_SPI_SPI4_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_SPI_SPI4_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_SPI_SPI5_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_SPI_SPI5_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_SPI_SPI6_RX_BDMA_STREAM STM32_BDMA_STREAM_ID_ANY
#define STM32_SPI_SPI6_TX_BDMA_STREAM STM32_BDMA_STREAM_ID_ANY
#define STM32_SPI_SPI1_DMA_PRIORITY 1
#define STM32_SPI_SPI2_DMA_PRIORITY 1
#define STM32_SPI_SPI3_DMA_PRIORITY 1
@ -411,22 +411,22 @@
#define STM32_UART_USE_USART6 FALSE
#define STM32_UART_USE_UART7 FALSE
#define STM32_UART_USE_UART8 FALSE
#define STM32_UART_USART1_RX_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY
#define STM32_UART_USART1_TX_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY
#define STM32_UART_USART2_RX_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY
#define STM32_UART_USART2_TX_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY
#define STM32_UART_USART3_RX_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY
#define STM32_UART_USART3_TX_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY
#define STM32_UART_UART4_RX_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY
#define STM32_UART_UART4_TX_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY
#define STM32_UART_UART5_RX_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY
#define STM32_UART_UART5_TX_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY
#define STM32_UART_USART6_RX_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY
#define STM32_UART_USART6_TX_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY
#define STM32_UART_UART7_RX_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY
#define STM32_UART_UART7_TX_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY
#define STM32_UART_UART8_RX_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY
#define STM32_UART_UART8_TX_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY
#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_UART4_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_UART4_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_UART5_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_UART5_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_UART7_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_UART7_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_UART8_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_UART8_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_USART1_IRQ_PRIORITY 12
#define STM32_UART_USART2_IRQ_PRIORITY 12
#define STM32_UART_USART3_IRQ_PRIORITY 12

54
testhal/STM32/multi/ADC/cfg/stm32l4r5zi_nucleo144/mcuconf.h
View File

@ -128,7 +128,7 @@
*/
#define STM32_ADC_COMPACT_SAMPLES FALSE
#define STM32_ADC_USE_ADC1 TRUE
#define STM32_ADC_ADC1_DMA_CHANNEL 10
#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_ADC_ADC1_DMA_PRIORITY 2
#define STM32_ADC_ADC12_IRQ_PRIORITY 5
#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 5
@ -150,8 +150,8 @@
#define STM32_DAC_DAC1_CH2_IRQ_PRIORITY 10
#define STM32_DAC_DAC1_CH1_DMA_PRIORITY 2
#define STM32_DAC_DAC1_CH2_DMA_PRIORITY 2
#define STM32_DAC_DAC1_CH1_DMA_CHANNEL 11
#define STM32_DAC_DAC1_CH2_DMA_CHANNEL 12
#define STM32_DAC_DAC1_CH1_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_DAC_DAC1_CH2_DMA_STREAM STM32_DMA_STREAM_ID_ANY
/*
* GPT driver system settings.
@ -180,12 +180,12 @@
#define STM32_I2C_USE_I2C2 FALSE
#define STM32_I2C_USE_I2C3 FALSE
#define STM32_I2C_BUSY_TIMEOUT 50
#define STM32_I2C_I2C1_RX_DMA_CHANNEL 6
#define STM32_I2C_I2C1_TX_DMA_CHANNEL 7
#define STM32_I2C_I2C2_RX_DMA_CHANNEL 8
#define STM32_I2C_I2C2_TX_DMA_CHANNEL 9
#define STM32_I2C_I2C3_RX_DMA_CHANNEL 8
#define STM32_I2C_I2C3_TX_DMA_CHANNEL 9
#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_I2C_I2C1_IRQ_PRIORITY 5
#define STM32_I2C_I2C2_IRQ_PRIORITY 5
#define STM32_I2C_I2C3_IRQ_PRIORITY 5
@ -261,12 +261,12 @@
#define STM32_SPI_USE_SPI1 FALSE
#define STM32_SPI_USE_SPI2 FALSE
#define STM32_SPI_USE_SPI3 FALSE
#define STM32_SPI_SPI1_RX_DMA_CHANNEL 0
#define STM32_SPI_SPI1_TX_DMA_CHANNEL 1
#define STM32_SPI_SPI2_RX_DMA_CHANNEL 2
#define STM32_SPI_SPI2_TX_DMA_CHANNEL 3
#define STM32_SPI_SPI3_RX_DMA_CHANNEL 4
#define STM32_SPI_SPI3_TX_DMA_CHANNEL 5
#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_SPI_SPI1_DMA_PRIORITY 1
#define STM32_SPI_SPI2_DMA_PRIORITY 1
#define STM32_SPI_SPI3_DMA_PRIORITY 1
@ -294,16 +294,16 @@
#define STM32_UART_USE_USART3 FALSE
#define STM32_UART_USE_UART4 FALSE
#define STM32_UART_USE_UART5 FALSE
#define STM32_UART_USART1_RX_DMA_CHANNEL 13
#define STM32_UART_USART1_TX_DMA_CHANNEL 0
#define STM32_UART_USART2_RX_DMA_CHANNEL 1
#define STM32_UART_USART2_TX_DMA_CHANNEL 2
#define STM32_UART_USART3_RX_DMA_CHANNEL 3
#define STM32_UART_USART3_TX_DMA_CHANNEL 4
#define STM32_UART_UART4_RX_DMA_CHANNEL 5
#define STM32_UART_UART4_TX_DMA_CHANNEL 6
#define STM32_UART_UART5_RX_DMA_CHANNEL 7
#define STM32_UART_UART5_TX_DMA_CHANNEL 8
#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_UART4_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_UART4_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_UART5_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_UART5_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_USART1_IRQ_PRIORITY 12
#define STM32_UART_USART2_IRQ_PRIORITY 12
#define STM32_UART_USART3_IRQ_PRIORITY 12
@ -337,8 +337,8 @@
#define STM32_WSPI_OCTOSPI2_PRESCALER_VALUE 1
#define STM32_WSPI_OCTOSPI1_IRQ_PRIORITY 10
#define STM32_WSPI_OCTOSPI2_IRQ_PRIORITY 10
#define STM32_WSPI_OCTOSPI1_DMA_CHANNEL 9
#define STM32_WSPI_OCTOSPI2_DMA_CHANNEL 10
#define STM32_WSPI_OCTOSPI1_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_WSPI_OCTOSPI2_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_WSPI_OCTOSPI1_DMA_PRIORITY 1
#define STM32_WSPI_OCTOSPI2_DMA_PRIORITY 1
#define STM32_WSPI_OCTOSPI1_DMA_IRQ_PRIORITY 10

82
testhal/STM32/multi/DAC/cfg/stm32h743_nucleo144/mcuconf.h
View File

@ -185,8 +185,8 @@
#define STM32_ADC_COMPACT_SAMPLES FALSE
#define STM32_ADC_USE_ADC12 FALSE
#define STM32_ADC_USE_ADC3 FALSE
#define STM32_ADC_ADC12_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY
#define STM32_ADC_ADC3_BDMA_CHANNEL STM32_BDMA_STREAM_ID_ANY
#define STM32_ADC_ADC12_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_ADC_ADC3_BDMA_STREAM STM32_BDMA_STREAM_ID_ANY
#define STM32_ADC_ADC12_DMA_PRIORITY 2
#define STM32_ADC_ADC3_DMA_PRIORITY 2
#define STM32_ADC_ADC12_IRQ_PRIORITY 5
@ -214,8 +214,8 @@
#define STM32_DAC_DAC1_CH2_IRQ_PRIORITY 10
#define STM32_DAC_DAC1_CH1_DMA_PRIORITY 2
#define STM32_DAC_DAC1_CH2_DMA_PRIORITY 2
#define STM32_DAC_DAC1_CH1_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY
#define STM32_DAC_DAC1_CH2_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY
#define STM32_DAC_DAC1_CH1_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_DAC_DAC1_CH2_DMA_STREAM STM32_DMA_STREAM_ID_ANY
/*
* GPT driver system settings.
@ -253,14 +253,14 @@
#define STM32_I2C_USE_I2C3 FALSE
#define STM32_I2C_USE_I2C4 FALSE
#define STM32_I2C_BUSY_TIMEOUT 50
#define STM32_I2C_I2C1_RX_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY
#define STM32_I2C_I2C1_TX_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY
#define STM32_I2C_I2C2_RX_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY
#define STM32_I2C_I2C2_TX_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY
#define STM32_I2C_I2C3_RX_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY
#define STM32_I2C_I2C3_TX_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY
#define STM32_I2C_I2C4_RX_BDMA_CHANNEL STM32_BDMA_STREAM_ID_ANY
#define STM32_I2C_I2C4_TX_BDMA_CHANNEL STM32_BDMA_STREAM_ID_ANY
#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_I2C_I2C4_RX_BDMA_STREAM STM32_BDMA_STREAM_ID_ANY
#define STM32_I2C_I2C4_TX_BDMA_STREAM STM32_BDMA_STREAM_ID_ANY
#define STM32_I2C_I2C1_IRQ_PRIORITY 5
#define STM32_I2C_I2C2_IRQ_PRIORITY 5
#define STM32_I2C_I2C3_IRQ_PRIORITY 5
@ -335,7 +335,7 @@
#define STM32_SDC_SDMMC_WRITE_TIMEOUT 1000
#define STM32_SDC_SDMMC_READ_TIMEOUT 1000
#define STM32_SDC_SDMMC_CLOCK_DELAY 10
#define STM32_SDC_SDMMC1_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY
#define STM32_SDC_SDMMC1_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_SDC_SDMMC1_DMA_PRIORITY 3
#define STM32_SDC_SDMMC1_IRQ_PRIORITY 9
@ -368,18 +368,18 @@
#define STM32_SPI_USE_SPI4 FALSE
#define STM32_SPI_USE_SPI5 FALSE
#define STM32_SPI_USE_SPI6 FALSE
#define STM32_SPI_SPI1_RX_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY
#define STM32_SPI_SPI1_TX_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY
#define STM32_SPI_SPI2_RX_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY
#define STM32_SPI_SPI2_TX_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY
#define STM32_SPI_SPI3_RX_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY
#define STM32_SPI_SPI3_TX_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY
#define STM32_SPI_SPI4_RX_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY
#define STM32_SPI_SPI4_TX_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY
#define STM32_SPI_SPI5_RX_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY
#define STM32_SPI_SPI5_TX_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY
#define STM32_SPI_SPI6_RX_BDMA_CHANNEL STM32_BDMA_STREAM_ID_ANY
#define STM32_SPI_SPI6_TX_BDMA_CHANNEL STM32_BDMA_STREAM_ID_ANY
#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_SPI_SPI4_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_SPI_SPI4_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_SPI_SPI5_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_SPI_SPI5_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_SPI_SPI6_RX_BDMA_STREAM STM32_BDMA_STREAM_ID_ANY
#define STM32_SPI_SPI6_TX_BDMA_STREAM STM32_BDMA_STREAM_ID_ANY
#define STM32_SPI_SPI1_DMA_PRIORITY 1
#define STM32_SPI_SPI2_DMA_PRIORITY 1
#define STM32_SPI_SPI3_DMA_PRIORITY 1
@ -411,22 +411,22 @@
#define STM32_UART_USE_USART6 FALSE
#define STM32_UART_USE_UART7 FALSE
#define STM32_UART_USE_UART8 FALSE
#define STM32_UART_USART1_RX_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY
#define STM32_UART_USART1_TX_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY
#define STM32_UART_USART2_RX_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY
#define STM32_UART_USART2_TX_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY
#define STM32_UART_USART3_RX_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY
#define STM32_UART_USART3_TX_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY
#define STM32_UART_UART4_RX_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY
#define STM32_UART_UART4_TX_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY
#define STM32_UART_UART5_RX_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY
#define STM32_UART_UART5_TX_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY
#define STM32_UART_USART6_RX_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY
#define STM32_UART_USART6_TX_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY
#define STM32_UART_UART7_RX_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY
#define STM32_UART_UART7_TX_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY
#define STM32_UART_UART8_RX_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY
#define STM32_UART_UART8_TX_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY
#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_UART4_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_UART4_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_UART5_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_UART5_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_UART7_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_UART7_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_UART8_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_UART8_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_USART1_IRQ_PRIORITY 12
#define STM32_UART_USART2_IRQ_PRIORITY 12
#define STM32_UART_USART3_IRQ_PRIORITY 12

54
testhal/STM32/multi/DAC/cfg/stm32l4r5zi_nucleo144/mcuconf.h
View File

@ -128,7 +128,7 @@
*/
#define STM32_ADC_COMPACT_SAMPLES FALSE
#define STM32_ADC_USE_ADC1 FALSE
#define STM32_ADC_ADC1_DMA_CHANNEL 10
#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_ADC_ADC1_DMA_PRIORITY 2
#define STM32_ADC_ADC12_IRQ_PRIORITY 5
#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 5
@ -150,8 +150,8 @@
#define STM32_DAC_DAC1_CH2_IRQ_PRIORITY 10
#define STM32_DAC_DAC1_CH1_DMA_PRIORITY 2
#define STM32_DAC_DAC1_CH2_DMA_PRIORITY 2
#define STM32_DAC_DAC1_CH1_DMA_CHANNEL 11
#define STM32_DAC_DAC1_CH2_DMA_CHANNEL 12
#define STM32_DAC_DAC1_CH1_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_DAC_DAC1_CH2_DMA_STREAM STM32_DMA_STREAM_ID_ANY
/*
* GPT driver system settings.
@ -180,12 +180,12 @@
#define STM32_I2C_USE_I2C2 FALSE
#define STM32_I2C_USE_I2C3 FALSE
#define STM32_I2C_BUSY_TIMEOUT 50
#define STM32_I2C_I2C1_RX_DMA_CHANNEL 6
#define STM32_I2C_I2C1_TX_DMA_CHANNEL 7
#define STM32_I2C_I2C2_RX_DMA_CHANNEL 8
#define STM32_I2C_I2C2_TX_DMA_CHANNEL 9
#define STM32_I2C_I2C3_RX_DMA_CHANNEL 8
#define STM32_I2C_I2C3_TX_DMA_CHANNEL 9
#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_I2C_I2C1_IRQ_PRIORITY 5
#define STM32_I2C_I2C2_IRQ_PRIORITY 5
#define STM32_I2C_I2C3_IRQ_PRIORITY 5
@ -261,12 +261,12 @@
#define STM32_SPI_USE_SPI1 FALSE
#define STM32_SPI_USE_SPI2 FALSE
#define STM32_SPI_USE_SPI3 FALSE
#define STM32_SPI_SPI1_RX_DMA_CHANNEL 0
#define STM32_SPI_SPI1_TX_DMA_CHANNEL 1
#define STM32_SPI_SPI2_RX_DMA_CHANNEL 2
#define STM32_SPI_SPI2_TX_DMA_CHANNEL 3
#define STM32_SPI_SPI3_RX_DMA_CHANNEL 4
#define STM32_SPI_SPI3_TX_DMA_CHANNEL 5
#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_SPI_SPI1_DMA_PRIORITY 1
#define STM32_SPI_SPI2_DMA_PRIORITY 1
#define STM32_SPI_SPI3_DMA_PRIORITY 1
@ -294,16 +294,16 @@
#define STM32_UART_USE_USART3 FALSE
#define STM32_UART_USE_UART4 FALSE
#define STM32_UART_USE_UART5 FALSE
#define STM32_UART_USART1_RX_DMA_CHANNEL 13
#define STM32_UART_USART1_TX_DMA_CHANNEL 0
#define STM32_UART_USART2_RX_DMA_CHANNEL 1
#define STM32_UART_USART2_TX_DMA_CHANNEL 2
#define STM32_UART_USART3_RX_DMA_CHANNEL 3
#define STM32_UART_USART3_TX_DMA_CHANNEL 4
#define STM32_UART_UART4_RX_DMA_CHANNEL 5
#define STM32_UART_UART4_TX_DMA_CHANNEL 6
#define STM32_UART_UART5_RX_DMA_CHANNEL 7
#define STM32_UART_UART5_TX_DMA_CHANNEL 8
#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_UART4_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_UART4_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_UART5_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_UART5_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_USART1_IRQ_PRIORITY 12
#define STM32_UART_USART2_IRQ_PRIORITY 12
#define STM32_UART_USART3_IRQ_PRIORITY 12
@ -337,8 +337,8 @@
#define STM32_WSPI_OCTOSPI2_PRESCALER_VALUE 1
#define STM32_WSPI_OCTOSPI1_IRQ_PRIORITY 10
#define STM32_WSPI_OCTOSPI2_IRQ_PRIORITY 10
#define STM32_WSPI_OCTOSPI1_DMA_CHANNEL 9
#define STM32_WSPI_OCTOSPI2_DMA_CHANNEL 10
#define STM32_WSPI_OCTOSPI1_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_WSPI_OCTOSPI2_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_WSPI_OCTOSPI1_DMA_PRIORITY 1
#define STM32_WSPI_OCTOSPI2_DMA_PRIORITY 1
#define STM32_WSPI_OCTOSPI1_DMA_IRQ_PRIORITY 10

82
testhal/STM32/multi/SPI/cfg/stm32h743_nucleo144/mcuconf.h
View File

@ -185,8 +185,8 @@
#define STM32_ADC_COMPACT_SAMPLES FALSE
#define STM32_ADC_USE_ADC12 TRUE
#define STM32_ADC_USE_ADC3 FALSE
#define STM32_ADC_ADC12_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY
#define STM32_ADC_ADC3_BDMA_CHANNEL STM32_BDMA_STREAM_ID_ANY
#define STM32_ADC_ADC12_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_ADC_ADC3_BDMA_STREAM STM32_BDMA_STREAM_ID_ANY
#define STM32_ADC_ADC12_DMA_PRIORITY 2
#define STM32_ADC_ADC3_DMA_PRIORITY 2
#define STM32_ADC_ADC12_IRQ_PRIORITY 5
@ -214,8 +214,8 @@
#define STM32_DAC_DAC1_CH2_IRQ_PRIORITY 10
#define STM32_DAC_DAC1_CH1_DMA_PRIORITY 2
#define STM32_DAC_DAC1_CH2_DMA_PRIORITY 2
#define STM32_DAC_DAC1_CH1_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY
#define STM32_DAC_DAC1_CH2_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY
#define STM32_DAC_DAC1_CH1_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_DAC_DAC1_CH2_DMA_STREAM STM32_DMA_STREAM_ID_ANY
/*
* GPT driver system settings.
@ -253,14 +253,14 @@
#define STM32_I2C_USE_I2C3 FALSE
#define STM32_I2C_USE_I2C4 FALSE
#define STM32_I2C_BUSY_TIMEOUT 50
#define STM32_I2C_I2C1_RX_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY
#define STM32_I2C_I2C1_TX_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY
#define STM32_I2C_I2C2_RX_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY
#define STM32_I2C_I2C2_TX_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY
#define STM32_I2C_I2C3_RX_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY
#define STM32_I2C_I2C3_TX_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY
#define STM32_I2C_I2C4_RX_BDMA_CHANNEL STM32_BDMA_STREAM_ID_ANY
#define STM32_I2C_I2C4_TX_BDMA_CHANNEL STM32_BDMA_STREAM_ID_ANY
#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_I2C_I2C4_RX_BDMA_STREAM STM32_BDMA_STREAM_ID_ANY
#define STM32_I2C_I2C4_TX_BDMA_STREAM STM32_BDMA_STREAM_ID_ANY
#define STM32_I2C_I2C1_IRQ_PRIORITY 5
#define STM32_I2C_I2C2_IRQ_PRIORITY 5
#define STM32_I2C_I2C3_IRQ_PRIORITY 5
@ -335,7 +335,7 @@
#define STM32_SDC_SDMMC_WRITE_TIMEOUT 1000
#define STM32_SDC_SDMMC_READ_TIMEOUT 1000
#define STM32_SDC_SDMMC_CLOCK_DELAY 10
#define STM32_SDC_SDMMC1_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY
#define STM32_SDC_SDMMC1_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_SDC_SDMMC1_DMA_PRIORITY 3
#define STM32_SDC_SDMMC1_IRQ_PRIORITY 9
@ -368,18 +368,18 @@
#define STM32_SPI_USE_SPI4 TRUE
#define STM32_SPI_USE_SPI5 TRUE
#define STM32_SPI_USE_SPI6 TRUE
#define STM32_SPI_SPI1_RX_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY
#define STM32_SPI_SPI1_TX_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY
#define STM32_SPI_SPI2_RX_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY
#define STM32_SPI_SPI2_TX_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY
#define STM32_SPI_SPI3_RX_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY
#define STM32_SPI_SPI3_TX_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY
#define STM32_SPI_SPI4_RX_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY
#define STM32_SPI_SPI4_TX_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY
#define STM32_SPI_SPI5_RX_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY
#define STM32_SPI_SPI5_TX_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY
#define STM32_SPI_SPI6_RX_BDMA_CHANNEL STM32_BDMA_STREAM_ID_ANY
#define STM32_SPI_SPI6_TX_BDMA_CHANNEL STM32_BDMA_STREAM_ID_ANY
#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_SPI_SPI4_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_SPI_SPI4_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_SPI_SPI5_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_SPI_SPI5_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_SPI_SPI6_RX_BDMA_STREAM STM32_BDMA_STREAM_ID_ANY
#define STM32_SPI_SPI6_TX_BDMA_STREAM STM32_BDMA_STREAM_ID_ANY
#define STM32_SPI_SPI1_DMA_PRIORITY 1
#define STM32_SPI_SPI2_DMA_PRIORITY 1
#define STM32_SPI_SPI3_DMA_PRIORITY 1
@ -411,22 +411,22 @@
#define STM32_UART_USE_USART6 FALSE
#define STM32_UART_USE_UART7 FALSE
#define STM32_UART_USE_UART8 FALSE
#define STM32_UART_USART1_RX_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY
#define STM32_UART_USART1_TX_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY
#define STM32_UART_USART2_RX_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY
#define STM32_UART_USART2_TX_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY
#define STM32_UART_USART3_RX_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY
#define STM32_UART_USART3_TX_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY
#define STM32_UART_UART4_RX_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY
#define STM32_UART_UART4_TX_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY
#define STM32_UART_UART5_RX_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY
#define STM32_UART_UART5_TX_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY
#define STM32_UART_USART6_RX_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY
#define STM32_UART_USART6_TX_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY
#define STM32_UART_UART7_RX_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY
#define STM32_UART_UART7_TX_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY
#define STM32_UART_UART8_RX_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY
#define STM32_UART_UART8_TX_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY
#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_UART4_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_UART4_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_UART5_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_UART5_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_UART7_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_UART7_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_UART8_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_UART8_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_USART1_IRQ_PRIORITY 12
#define STM32_UART_USART2_IRQ_PRIORITY 12
#define STM32_UART_USART3_IRQ_PRIORITY 12

54
testhal/STM32/multi/SPI/cfg/stm32l4r5_nucleo144/mcuconf.h
View File

@ -128,7 +128,7 @@
*/
#define STM32_ADC_COMPACT_SAMPLES FALSE
#define STM32_ADC_USE_ADC1 FALSE
#define STM32_ADC_ADC1_DMA_CHANNEL 10
#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_ADC_ADC1_DMA_PRIORITY 2
#define STM32_ADC_ADC12_IRQ_PRIORITY 5
#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 5
@ -150,8 +150,8 @@
#define STM32_DAC_DAC1_CH2_IRQ_PRIORITY 10
#define STM32_DAC_DAC1_CH1_DMA_PRIORITY 2
#define STM32_DAC_DAC1_CH2_DMA_PRIORITY 2
#define STM32_DAC_DAC1_CH1_DMA_CHANNEL 11
#define STM32_DAC_DAC1_CH2_DMA_CHANNEL 12
#define STM32_DAC_DAC1_CH1_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_DAC_DAC1_CH2_DMA_STREAM STM32_DMA_STREAM_ID_ANY
/*
* GPT driver system settings.
@ -180,12 +180,12 @@
#define STM32_I2C_USE_I2C2 FALSE
#define STM32_I2C_USE_I2C3 FALSE
#define STM32_I2C_BUSY_TIMEOUT 50
#define STM32_I2C_I2C1_RX_DMA_CHANNEL 6
#define STM32_I2C_I2C1_TX_DMA_CHANNEL 7
#define STM32_I2C_I2C2_RX_DMA_CHANNEL 8
#define STM32_I2C_I2C2_TX_DMA_CHANNEL 9
#define STM32_I2C_I2C3_RX_DMA_CHANNEL 8
#define STM32_I2C_I2C3_TX_DMA_CHANNEL 9
#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_I2C_I2C1_IRQ_PRIORITY 5
#define STM32_I2C_I2C2_IRQ_PRIORITY 5
#define STM32_I2C_I2C3_IRQ_PRIORITY 5
@ -261,12 +261,12 @@
#define STM32_SPI_USE_SPI1 FALSE
#define STM32_SPI_USE_SPI2 TRUE
#define STM32_SPI_USE_SPI3 FALSE
#define STM32_SPI_SPI1_RX_DMA_CHANNEL 0
#define STM32_SPI_SPI1_TX_DMA_CHANNEL 1
#define STM32_SPI_SPI2_RX_DMA_CHANNEL 2
#define STM32_SPI_SPI2_TX_DMA_CHANNEL 3
#define STM32_SPI_SPI3_RX_DMA_CHANNEL 4
#define STM32_SPI_SPI3_TX_DMA_CHANNEL 5
#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_SPI_SPI1_DMA_PRIORITY 1
#define STM32_SPI_SPI2_DMA_PRIORITY 1
#define STM32_SPI_SPI3_DMA_PRIORITY 1
@ -294,16 +294,16 @@
#define STM32_UART_USE_USART3 FALSE
#define STM32_UART_USE_UART4 FALSE
#define STM32_UART_USE_UART5 FALSE
#define STM32_UART_USART1_RX_DMA_CHANNEL 13
#define STM32_UART_USART1_TX_DMA_CHANNEL 0
#define STM32_UART_USART2_RX_DMA_CHANNEL 1
#define STM32_UART_USART2_TX_DMA_CHANNEL 2
#define STM32_UART_USART3_RX_DMA_CHANNEL 3
#define STM32_UART_USART3_TX_DMA_CHANNEL 4
#define STM32_UART_UART4_RX_DMA_CHANNEL 5
#define STM32_UART_UART4_TX_DMA_CHANNEL 6
#define STM32_UART_UART5_RX_DMA_CHANNEL 7
#define STM32_UART_UART5_TX_DMA_CHANNEL 8
#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_UART4_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_UART4_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_UART5_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_UART5_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_USART1_IRQ_PRIORITY 12
#define STM32_UART_USART2_IRQ_PRIORITY 12
#define STM32_UART_USART3_IRQ_PRIORITY 12
@ -337,8 +337,8 @@
#define STM32_WSPI_OCTOSPI2_PRESCALER_VALUE 1
#define STM32_WSPI_OCTOSPI1_IRQ_PRIORITY 10
#define STM32_WSPI_OCTOSPI2_IRQ_PRIORITY 10
#define STM32_WSPI_OCTOSPI1_DMA_CHANNEL 9
#define STM32_WSPI_OCTOSPI2_DMA_CHANNEL 10
#define STM32_WSPI_OCTOSPI1_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_WSPI_OCTOSPI2_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_WSPI_OCTOSPI1_DMA_PRIORITY 1
#define STM32_WSPI_OCTOSPI2_DMA_PRIORITY 1
#define STM32_WSPI_OCTOSPI1_DMA_IRQ_PRIORITY 10

54
testhal/STM32/multi/SPI/cfg/stm32l4r9_discovery/mcuconf.h
View File

@ -128,7 +128,7 @@
*/
#define STM32_ADC_COMPACT_SAMPLES FALSE
#define STM32_ADC_USE_ADC1 FALSE
#define STM32_ADC_ADC1_DMA_CHANNEL 10
#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_ADC_ADC1_DMA_PRIORITY 2
#define STM32_ADC_ADC12_IRQ_PRIORITY 5
#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 5
@ -150,8 +150,8 @@
#define STM32_DAC_DAC1_CH2_IRQ_PRIORITY 10
#define STM32_DAC_DAC1_CH1_DMA_PRIORITY 2
#define STM32_DAC_DAC1_CH2_DMA_PRIORITY 2
#define STM32_DAC_DAC1_CH1_DMA_CHANNEL 11
#define STM32_DAC_DAC1_CH2_DMA_CHANNEL 12
#define STM32_DAC_DAC1_CH1_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_DAC_DAC1_CH2_DMA_STREAM STM32_DMA_STREAM_ID_ANY
/*
* GPT driver system settings.
@ -180,12 +180,12 @@
#define STM32_I2C_USE_I2C2 FALSE
#define STM32_I2C_USE_I2C3 FALSE
#define STM32_I2C_BUSY_TIMEOUT 50
#define STM32_I2C_I2C1_RX_DMA_CHANNEL 6
#define STM32_I2C_I2C1_TX_DMA_CHANNEL 7
#define STM32_I2C_I2C2_RX_DMA_CHANNEL 8
#define STM32_I2C_I2C2_TX_DMA_CHANNEL 9
#define STM32_I2C_I2C3_RX_DMA_CHANNEL 8
#define STM32_I2C_I2C3_TX_DMA_CHANNEL 9
#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_I2C_I2C1_IRQ_PRIORITY 5
#define STM32_I2C_I2C2_IRQ_PRIORITY 5
#define STM32_I2C_I2C3_IRQ_PRIORITY 5
@ -261,12 +261,12 @@
#define STM32_SPI_USE_SPI1 FALSE
#define STM32_SPI_USE_SPI2 TRUE
#define STM32_SPI_USE_SPI3 FALSE
#define STM32_SPI_SPI1_RX_DMA_CHANNEL 0
#define STM32_SPI_SPI1_TX_DMA_CHANNEL 1
#define STM32_SPI_SPI2_RX_DMA_CHANNEL 2
#define STM32_SPI_SPI2_TX_DMA_CHANNEL 3
#define STM32_SPI_SPI3_RX_DMA_CHANNEL 4
#define STM32_SPI_SPI3_TX_DMA_CHANNEL 5
#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_SPI_SPI1_DMA_PRIORITY 1
#define STM32_SPI_SPI2_DMA_PRIORITY 1
#define STM32_SPI_SPI3_DMA_PRIORITY 1
@ -294,16 +294,16 @@
#define STM32_UART_USE_USART3 FALSE
#define STM32_UART_USE_UART4 FALSE
#define STM32_UART_USE_UART5 FALSE
#define STM32_UART_USART1_RX_DMA_CHANNEL 13
#define STM32_UART_USART1_TX_DMA_CHANNEL 0
#define STM32_UART_USART2_RX_DMA_CHANNEL 1
#define STM32_UART_USART2_TX_DMA_CHANNEL 2
#define STM32_UART_USART3_RX_DMA_CHANNEL 3
#define STM32_UART_USART3_TX_DMA_CHANNEL 4
#define STM32_UART_UART4_RX_DMA_CHANNEL 5
#define STM32_UART_UART4_TX_DMA_CHANNEL 6
#define STM32_UART_UART5_RX_DMA_CHANNEL 7
#define STM32_UART_UART5_TX_DMA_CHANNEL 8
#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_UART4_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_UART4_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_UART5_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_UART5_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_USART1_IRQ_PRIORITY 12
#define STM32_UART_USART2_IRQ_PRIORITY 12
#define STM32_UART_USART3_IRQ_PRIORITY 12
@ -337,8 +337,8 @@
#define STM32_WSPI_OCTOSPI2_PRESCALER_VALUE 1
#define STM32_WSPI_OCTOSPI1_IRQ_PRIORITY 10
#define STM32_WSPI_OCTOSPI2_IRQ_PRIORITY 10
#define STM32_WSPI_OCTOSPI1_DMA_CHANNEL 9
#define STM32_WSPI_OCTOSPI2_DMA_CHANNEL 10
#define STM32_WSPI_OCTOSPI1_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_WSPI_OCTOSPI2_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_WSPI_OCTOSPI1_DMA_PRIORITY 1
#define STM32_WSPI_OCTOSPI2_DMA_PRIORITY 1
#define STM32_WSPI_OCTOSPI1_DMA_IRQ_PRIORITY 10

54
testhal/STM32/multi/TRNG/cfg/stm32l4r5zi_nucleo144/mcuconf.h
View File

@ -128,7 +128,7 @@
*/
#define STM32_ADC_COMPACT_SAMPLES FALSE
#define STM32_ADC_USE_ADC1 FALSE
#define STM32_ADC_ADC1_DMA_CHANNEL 10
#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_ADC_ADC1_DMA_PRIORITY 2
#define STM32_ADC_ADC12_IRQ_PRIORITY 5
#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 5
@ -150,8 +150,8 @@
#define STM32_DAC_DAC1_CH2_IRQ_PRIORITY 10
#define STM32_DAC_DAC1_CH1_DMA_PRIORITY 2
#define STM32_DAC_DAC1_CH2_DMA_PRIORITY 2
#define STM32_DAC_DAC1_CH1_DMA_CHANNEL 11
#define STM32_DAC_DAC1_CH2_DMA_CHANNEL 12
#define STM32_DAC_DAC1_CH1_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_DAC_DAC1_CH2_DMA_STREAM STM32_DMA_STREAM_ID_ANY
/*
* GPT driver system settings.
@ -180,12 +180,12 @@
#define STM32_I2C_USE_I2C2 FALSE
#define STM32_I2C_USE_I2C3 FALSE
#define STM32_I2C_BUSY_TIMEOUT 50
#define STM32_I2C_I2C1_RX_DMA_CHANNEL 6
#define STM32_I2C_I2C1_TX_DMA_CHANNEL 7
#define STM32_I2C_I2C2_RX_DMA_CHANNEL 8
#define STM32_I2C_I2C2_TX_DMA_CHANNEL 9
#define STM32_I2C_I2C3_RX_DMA_CHANNEL 8
#define STM32_I2C_I2C3_TX_DMA_CHANNEL 9
#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_I2C_I2C1_IRQ_PRIORITY 5
#define STM32_I2C_I2C2_IRQ_PRIORITY 5
#define STM32_I2C_I2C3_IRQ_PRIORITY 5
@ -261,12 +261,12 @@
#define STM32_SPI_USE_SPI1 FALSE
#define STM32_SPI_USE_SPI2 FALSE
#define STM32_SPI_USE_SPI3 FALSE
#define STM32_SPI_SPI1_RX_DMA_CHANNEL 0
#define STM32_SPI_SPI1_TX_DMA_CHANNEL 1
#define STM32_SPI_SPI2_RX_DMA_CHANNEL 2
#define STM32_SPI_SPI2_TX_DMA_CHANNEL 3
#define STM32_SPI_SPI3_RX_DMA_CHANNEL 4
#define STM32_SPI_SPI3_TX_DMA_CHANNEL 5
#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_SPI_SPI1_DMA_PRIORITY 1
#define STM32_SPI_SPI2_DMA_PRIORITY 1
#define STM32_SPI_SPI3_DMA_PRIORITY 1
@ -294,16 +294,16 @@
#define STM32_UART_USE_USART3 FALSE
#define STM32_UART_USE_UART4 FALSE
#define STM32_UART_USE_UART5 FALSE
#define STM32_UART_USART1_RX_DMA_CHANNEL 13
#define STM32_UART_USART1_TX_DMA_CHANNEL 0
#define STM32_UART_USART2_RX_DMA_CHANNEL 1
#define STM32_UART_USART2_TX_DMA_CHANNEL 2
#define STM32_UART_USART3_RX_DMA_CHANNEL 3
#define STM32_UART_USART3_TX_DMA_CHANNEL 4
#define STM32_UART_UART4_RX_DMA_CHANNEL 5
#define STM32_UART_UART4_TX_DMA_CHANNEL 6
#define STM32_UART_UART5_RX_DMA_CHANNEL 7
#define STM32_UART_UART5_TX_DMA_CHANNEL 8
#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_UART4_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_UART4_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_UART5_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_UART5_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_USART1_IRQ_PRIORITY 12
#define STM32_UART_USART2_IRQ_PRIORITY 12
#define STM32_UART_USART3_IRQ_PRIORITY 12
@ -337,8 +337,8 @@
#define STM32_WSPI_OCTOSPI2_PRESCALER_VALUE 1
#define STM32_WSPI_OCTOSPI1_IRQ_PRIORITY 10
#define STM32_WSPI_OCTOSPI2_IRQ_PRIORITY 10
#define STM32_WSPI_OCTOSPI1_DMA_CHANNEL 9
#define STM32_WSPI_OCTOSPI2_DMA_CHANNEL 10
#define STM32_WSPI_OCTOSPI1_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_WSPI_OCTOSPI2_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_WSPI_OCTOSPI1_DMA_PRIORITY 1
#define STM32_WSPI_OCTOSPI2_DMA_PRIORITY 1
#define STM32_WSPI_OCTOSPI1_DMA_IRQ_PRIORITY 10

82
tools/ftl/processors/conf/mcuconf_stm32h743xx/mcuconf.h.ftl
View File

@ -196,8 +196,8 @@
#define STM32_ADC_COMPACT_SAMPLES ${doc.STM32_ADC_COMPACT_SAMPLES!"FALSE"}
#define STM32_ADC_USE_ADC12 ${doc.STM32_ADC_USE_ADC12!"TRUE"}
#define STM32_ADC_USE_ADC3 ${doc.STM32_ADC_USE_ADC3!"FALSE"}
#define STM32_ADC_ADC12_DMA_CHANNEL ${doc.STM32_ADC_ADC12_DMA_CHANNEL!"STM32_DMA_STREAM_ID_ANY"}
#define STM32_ADC_ADC3_BDMA_CHANNEL ${doc.STM32_ADC_ADC3_BDMA_CHANNEL!"STM32_BDMA_STREAM_ID_ANY"}
#define STM32_ADC_ADC12_DMA_STREAM ${doc.STM32_ADC_ADC12_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"}
#define STM32_ADC_ADC3_BDMA_STREAM ${doc.STM32_ADC_ADC3_BDMA_STREAM!"STM32_BDMA_STREAM_ID_ANY"}
#define STM32_ADC_ADC12_DMA_PRIORITY ${doc.STM32_ADC_ADC12_DMA_PRIORITY!"2"}
#define STM32_ADC_ADC3_DMA_PRIORITY ${doc.STM32_ADC_ADC3_DMA_PRIORITY!"2"}
#define STM32_ADC_ADC12_IRQ_PRIORITY ${doc.STM32_ADC_ADC12_IRQ_PRIORITY!"5"}
@ -225,8 +225,8 @@
#define STM32_DAC_DAC1_CH2_IRQ_PRIORITY ${doc.STM32_DAC_DAC1_CH2_IRQ_PRIORITY!"10"}
#define STM32_DAC_DAC1_CH1_DMA_PRIORITY ${doc.STM32_DAC_DAC1_CH1_DMA_PRIORITY!"2"}
#define STM32_DAC_DAC1_CH2_DMA_PRIORITY ${doc.STM32_DAC_DAC1_CH2_DMA_PRIORITY!"2"}
#define STM32_DAC_DAC1_CH1_DMA_CHANNEL ${doc.STM32_DAC_DAC1_CH1_DMA_CHANNEL!"STM32_DMA_STREAM_ID_ANY"}
#define STM32_DAC_DAC1_CH2_DMA_CHANNEL ${doc.STM32_DAC_DAC1_CH2_DMA_CHANNEL!"STM32_DMA_STREAM_ID_ANY"}
#define STM32_DAC_DAC1_CH1_DMA_STREAM ${doc.STM32_DAC_DAC1_CH1_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"}
#define STM32_DAC_DAC1_CH2_DMA_STREAM ${doc.STM32_DAC_DAC1_CH2_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"}
/*
* GPT driver system settings.
@ -264,14 +264,14 @@
#define STM32_I2C_USE_I2C3 ${doc.STM32_I2C_USE_I2C3!"FALSE"}
#define STM32_I2C_USE_I2C4 ${doc.STM32_I2C_USE_I2C4!"FALSE"}
#define STM32_I2C_BUSY_TIMEOUT ${doc.STM32_I2C_BUSY_TIMEOUT!"50"}
#define STM32_I2C_I2C1_RX_DMA_CHANNEL ${doc.STM32_I2C_I2C1_RX_DMA_CHANNEL!"STM32_DMA_STREAM_ID_ANY"}
#define STM32_I2C_I2C1_TX_DMA_CHANNEL ${doc.STM32_I2C_I2C1_TX_DMA_CHANNEL!"STM32_DMA_STREAM_ID_ANY"}
#define STM32_I2C_I2C2_RX_DMA_CHANNEL ${doc.STM32_I2C_I2C2_RX_DMA_CHANNEL!"STM32_DMA_STREAM_ID_ANY"}
#define STM32_I2C_I2C2_TX_DMA_CHANNEL ${doc.STM32_I2C_I2C2_TX_DMA_CHANNEL!"STM32_DMA_STREAM_ID_ANY"}
#define STM32_I2C_I2C3_RX_DMA_CHANNEL ${doc.STM32_I2C_I2C3_RX_DMA_CHANNEL!"STM32_DMA_STREAM_ID_ANY"}
#define STM32_I2C_I2C3_TX_DMA_CHANNEL ${doc.STM32_I2C_I2C3_TX_DMA_CHANNEL!"STM32_DMA_STREAM_ID_ANY"}
#define STM32_I2C_I2C4_RX_BDMA_CHANNEL ${doc.STM32_I2C_I2C4_RX_BDMA_CHANNEL!"STM32_BDMA_STREAM_ID_ANY"}
#define STM32_I2C_I2C4_TX_BDMA_CHANNEL ${doc.STM32_I2C_I2C4_TX_BDMA_CHANNEL!"STM32_BDMA_STREAM_ID_ANY"}
#define STM32_I2C_I2C1_RX_DMA_STREAM ${doc.STM32_I2C_I2C1_RX_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"}
#define STM32_I2C_I2C1_TX_DMA_STREAM ${doc.STM32_I2C_I2C1_TX_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"}
#define STM32_I2C_I2C2_RX_DMA_STREAM ${doc.STM32_I2C_I2C2_RX_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"}
#define STM32_I2C_I2C2_TX_DMA_STREAM ${doc.STM32_I2C_I2C2_TX_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"}
#define STM32_I2C_I2C3_RX_DMA_STREAM ${doc.STM32_I2C_I2C3_RX_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"}
#define STM32_I2C_I2C3_TX_DMA_STREAM ${doc.STM32_I2C_I2C3_TX_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"}
#define STM32_I2C_I2C4_RX_BDMA_STREAM ${doc.STM32_I2C_I2C4_RX_BDMA_STREAM!"STM32_BDMA_STREAM_ID_ANY"}
#define STM32_I2C_I2C4_TX_BDMA_STREAM ${doc.STM32_I2C_I2C4_TX_BDMA_STREAM!"STM32_BDMA_STREAM_ID_ANY"}
#define STM32_I2C_I2C1_IRQ_PRIORITY ${doc.STM32_I2C_I2C1_IRQ_PRIORITY!"5"}
#define STM32_I2C_I2C2_IRQ_PRIORITY ${doc.STM32_I2C_I2C2_IRQ_PRIORITY!"5"}
#define STM32_I2C_I2C3_IRQ_PRIORITY ${doc.STM32_I2C_I2C3_IRQ_PRIORITY!"5"}
@ -346,7 +346,7 @@
#define STM32_SDC_SDMMC_WRITE_TIMEOUT ${doc.STM32_SDC_SDMMC_WRITE_TIMEOUT!"1000"}
#define STM32_SDC_SDMMC_READ_TIMEOUT ${doc.STM32_SDC_SDMMC_READ_TIMEOUT!"1000"}
#define STM32_SDC_SDMMC_CLOCK_DELAY ${doc.STM32_SDC_SDMMC_CLOCK_DELAY!"10"}
#define STM32_SDC_SDMMC1_DMA_CHANNEL ${doc.STM32_SDC_SDMMC1_DMA_CHANNEL!"STM32_DMA_STREAM_ID_ANY"}
#define STM32_SDC_SDMMC1_DMA_STREAM ${doc.STM32_SDC_SDMMC1_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"}
#define STM32_SDC_SDMMC1_DMA_PRIORITY ${doc.STM32_SDC_SDMMC1_DMA_PRIORITY!"3"}
#define STM32_SDC_SDMMC1_IRQ_PRIORITY ${doc.STM32_SDC_SDMMC1_IRQ_PRIORITY!"9"}
@ -379,18 +379,18 @@
#define STM32_SPI_USE_SPI4 ${doc.STM32_SPI_USE_SPI4!"FALSE"}
#define STM32_SPI_USE_SPI5 ${doc.STM32_SPI_USE_SPI5!"FALSE"}
#define STM32_SPI_USE_SPI6 ${doc.STM32_SPI_USE_SPI6!"FALSE"}
#define STM32_SPI_SPI1_RX_DMA_CHANNEL ${doc.STM32_SPI_SPI1_RX_DMA_CHANNEL!"STM32_DMA_STREAM_ID_ANY"}
#define STM32_SPI_SPI1_TX_DMA_CHANNEL ${doc.STM32_SPI_SPI1_TX_DMA_CHANNEL!"STM32_DMA_STREAM_ID_ANY"}
#define STM32_SPI_SPI2_RX_DMA_CHANNEL ${doc.STM32_SPI_SPI2_RX_DMA_CHANNEL!"STM32_DMA_STREAM_ID_ANY"}
#define STM32_SPI_SPI2_TX_DMA_CHANNEL ${doc.STM32_SPI_SPI2_TX_DMA_CHANNEL!"STM32_DMA_STREAM_ID_ANY"}
#define STM32_SPI_SPI3_RX_DMA_CHANNEL ${doc.STM32_SPI_SPI3_RX_DMA_CHANNEL!"STM32_DMA_STREAM_ID_ANY"}
#define STM32_SPI_SPI3_TX_DMA_CHANNEL ${doc.STM32_SPI_SPI3_TX_DMA_CHANNEL!"STM32_DMA_STREAM_ID_ANY"}
#define STM32_SPI_SPI4_RX_DMA_CHANNEL ${doc.STM32_SPI_SPI4_RX_DMA_CHANNEL!"STM32_DMA_STREAM_ID_ANY"}
#define STM32_SPI_SPI4_TX_DMA_CHANNEL ${doc.STM32_SPI_SPI4_TX_DMA_CHANNEL!"STM32_DMA_STREAM_ID_ANY"}
#define STM32_SPI_SPI5_RX_DMA_CHANNEL ${doc.STM32_SPI_SPI5_RX_DMA_CHANNEL!"STM32_DMA_STREAM_ID_ANY"}
#define STM32_SPI_SPI5_TX_DMA_CHANNEL ${doc.STM32_SPI_SPI5_TX_DMA_CHANNEL!"STM32_DMA_STREAM_ID_ANY"}
#define STM32_SPI_SPI6_RX_BDMA_CHANNEL ${doc.STM32_SPI_SPI6_RX_BDMA_CHANNEL!"STM32_BDMA_STREAM_ID_ANY"}
#define STM32_SPI_SPI6_TX_BDMA_CHANNEL ${doc.STM32_SPI_SPI6_TX_BDMA_CHANNEL!"STM32_BDMA_STREAM_ID_ANY"}
#define STM32_SPI_SPI1_RX_DMA_STREAM ${doc.STM32_SPI_SPI1_RX_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"}
#define STM32_SPI_SPI1_TX_DMA_STREAM ${doc.STM32_SPI_SPI1_TX_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"}
#define STM32_SPI_SPI2_RX_DMA_STREAM ${doc.STM32_SPI_SPI2_RX_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"}
#define STM32_SPI_SPI2_TX_DMA_STREAM ${doc.STM32_SPI_SPI2_TX_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"}
#define STM32_SPI_SPI3_RX_DMA_STREAM ${doc.STM32_SPI_SPI3_RX_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"}
#define STM32_SPI_SPI3_TX_DMA_STREAM ${doc.STM32_SPI_SPI3_TX_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"}
#define STM32_SPI_SPI4_RX_DMA_STREAM ${doc.STM32_SPI_SPI4_RX_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"}
#define STM32_SPI_SPI4_TX_DMA_STREAM ${doc.STM32_SPI_SPI4_TX_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"}
#define STM32_SPI_SPI5_RX_DMA_STREAM ${doc.STM32_SPI_SPI5_RX_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"}
#define STM32_SPI_SPI5_TX_DMA_STREAM ${doc.STM32_SPI_SPI5_TX_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"}
#define STM32_SPI_SPI6_RX_BDMA_STREAM ${doc.STM32_SPI_SPI6_RX_BDMA_STREAM!"STM32_BDMA_STREAM_ID_ANY"}
#define STM32_SPI_SPI6_TX_BDMA_STREAM ${doc.STM32_SPI_SPI6_TX_BDMA_STREAM!"STM32_BDMA_STREAM_ID_ANY"}
#define STM32_SPI_SPI1_DMA_PRIORITY ${doc.STM32_SPI_SPI1_DMA_PRIORITY!"1"}
#define STM32_SPI_SPI2_DMA_PRIORITY ${doc.STM32_SPI_SPI2_DMA_PRIORITY!"1"}
#define STM32_SPI_SPI3_DMA_PRIORITY ${doc.STM32_SPI_SPI3_DMA_PRIORITY!"1"}
@ -422,22 +422,22 @@
#define STM32_UART_USE_USART6 ${doc.STM32_UART_USE_USART6!"FALSE"}
#define STM32_UART_USE_UART7 ${doc.STM32_UART_USE_UART7!"FALSE"}
#define STM32_UART_USE_UART8 ${doc.STM32_UART_USE_UART8!"FALSE"}
#define STM32_UART_USART1_RX_DMA_CHANNEL ${doc.STM32_UART_USART1_RX_DMA_CHANNEL!"STM32_DMA_STREAM_ID_ANY"}
#define STM32_UART_USART1_TX_DMA_CHANNEL ${doc.STM32_UART_USART1_TX_DMA_CHANNEL!"STM32_DMA_STREAM_ID_ANY"}
#define STM32_UART_USART2_RX_DMA_CHANNEL ${doc.STM32_UART_USART2_RX_DMA_CHANNEL!"STM32_DMA_STREAM_ID_ANY"}
#define STM32_UART_USART2_TX_DMA_CHANNEL ${doc.STM32_UART_USART2_TX_DMA_CHANNEL!"STM32_DMA_STREAM_ID_ANY"}
#define STM32_UART_USART3_RX_DMA_CHANNEL ${doc.STM32_UART_USART3_RX_DMA_CHANNEL!"STM32_DMA_STREAM_ID_ANY"}
#define STM32_UART_USART3_TX_DMA_CHANNEL ${doc.STM32_UART_USART3_TX_DMA_CHANNEL!"STM32_DMA_STREAM_ID_ANY"}
#define STM32_UART_UART4_RX_DMA_CHANNEL ${doc.STM32_UART_UART4_RX_DMA_CHANNEL!"STM32_DMA_STREAM_ID_ANY"}
#define STM32_UART_UART4_TX_DMA_CHANNEL ${doc.STM32_UART_UART4_TX_DMA_CHANNEL!"STM32_DMA_STREAM_ID_ANY"}
#define STM32_UART_UART5_RX_DMA_CHANNEL ${doc.STM32_UART_UART5_RX_DMA_CHANNEL!"STM32_DMA_STREAM_ID_ANY"}
#define STM32_UART_UART5_TX_DMA_CHANNEL ${doc.STM32_UART_UART5_TX_DMA_CHANNEL!"STM32_DMA_STREAM_ID_ANY"}
#define STM32_UART_USART6_RX_DMA_CHANNEL ${doc.STM32_UART_USART6_RX_DMA_CHANNEL!"STM32_DMA_STREAM_ID_ANY"}
#define STM32_UART_USART6_TX_DMA_CHANNEL ${doc.STM32_UART_USART6_TX_DMA_CHANNEL!"STM32_DMA_STREAM_ID_ANY"}
#define STM32_UART_UART7_RX_DMA_CHANNEL ${doc.STM32_UART_UART7_RX_DMA_CHANNEL!"STM32_DMA_STREAM_ID_ANY"}
#define STM32_UART_UART7_TX_DMA_CHANNEL ${doc.STM32_UART_UART7_TX_DMA_CHANNEL!"STM32_DMA_STREAM_ID_ANY"}
#define STM32_UART_UART8_RX_DMA_CHANNEL ${doc.STM32_UART_UART8_RX_DMA_CHANNEL!"STM32_DMA_STREAM_ID_ANY"}
#define STM32_UART_UART8_TX_DMA_CHANNEL ${doc.STM32_UART_UART8_TX_DMA_CHANNEL!"STM32_DMA_STREAM_ID_ANY"}
#define STM32_UART_USART1_RX_DMA_STREAM ${doc.STM32_UART_USART1_RX_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"}
#define STM32_UART_USART1_TX_DMA_STREAM ${doc.STM32_UART_USART1_TX_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"}
#define STM32_UART_USART2_RX_DMA_STREAM ${doc.STM32_UART_USART2_RX_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"}
#define STM32_UART_USART2_TX_DMA_STREAM ${doc.STM32_UART_USART2_TX_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"}
#define STM32_UART_USART3_RX_DMA_STREAM ${doc.STM32_UART_USART3_RX_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"}
#define STM32_UART_USART3_TX_DMA_STREAM ${doc.STM32_UART_USART3_TX_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"}
#define STM32_UART_UART4_RX_DMA_STREAM ${doc.STM32_UART_UART4_RX_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"}
#define STM32_UART_UART4_TX_DMA_STREAM ${doc.STM32_UART_UART4_TX_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"}
#define STM32_UART_UART5_RX_DMA_STREAM ${doc.STM32_UART_UART5_RX_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"}
#define STM32_UART_UART5_TX_DMA_STREAM ${doc.STM32_UART_UART5_TX_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"}
#define STM32_UART_USART6_RX_DMA_STREAM ${doc.STM32_UART_USART6_RX_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"}
#define STM32_UART_USART6_TX_DMA_STREAM ${doc.STM32_UART_USART6_TX_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"}
#define STM32_UART_UART7_RX_DMA_STREAM ${doc.STM32_UART_UART7_RX_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"}
#define STM32_UART_UART7_TX_DMA_STREAM ${doc.STM32_UART_UART7_TX_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"}
#define STM32_UART_UART8_RX_DMA_STREAM ${doc.STM32_UART_UART8_RX_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"}
#define STM32_UART_UART8_TX_DMA_STREAM ${doc.STM32_UART_UART8_TX_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"}
#define STM32_UART_USART1_IRQ_PRIORITY ${doc.STM32_UART_USART1_IRQ_PRIORITY!"12"}
#define STM32_UART_USART2_IRQ_PRIORITY ${doc.STM32_UART_USART2_IRQ_PRIORITY!"12"}
#define STM32_UART_USART3_IRQ_PRIORITY ${doc.STM32_UART_USART3_IRQ_PRIORITY!"12"}

54
tools/ftl/processors/conf/mcuconf_stm32l4rxxx/mcuconf.h.ftl
View File

@ -139,7 +139,7 @@
*/
#define STM32_ADC_COMPACT_SAMPLES ${doc.STM32_ADC_COMPACT_SAMPLES!"FALSE"}
#define STM32_ADC_USE_ADC1 ${doc.STM32_ADC_USE_ADC1!"FALSE"}
#define STM32_ADC_ADC1_DMA_CHANNEL ${doc.STM32_ADC_ADC1_DMA_CHANNEL!"10"}
#define STM32_ADC_ADC1_DMA_STREAM ${doc.STM32_ADC_ADC1_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"}
#define STM32_ADC_ADC1_DMA_PRIORITY ${doc.STM32_ADC_ADC1_DMA_PRIORITY!"2"}
#define STM32_ADC_ADC12_IRQ_PRIORITY ${doc.STM32_ADC_ADC12_IRQ_PRIORITY!"5"}
#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY ${doc.STM32_ADC_ADC1_DMA_IRQ_PRIORITY!"5"}
@ -161,8 +161,8 @@
#define STM32_DAC_DAC1_CH2_IRQ_PRIORITY ${doc.STM32_DAC_DAC1_CH2_IRQ_PRIORITY!"10"}
#define STM32_DAC_DAC1_CH1_DMA_PRIORITY ${doc.STM32_DAC_DAC1_CH1_DMA_PRIORITY!"2"}
#define STM32_DAC_DAC1_CH2_DMA_PRIORITY ${doc.STM32_DAC_DAC1_CH2_DMA_PRIORITY!"2"}
#define STM32_DAC_DAC1_CH1_DMA_CHANNEL ${doc.STM32_DAC_DAC1_CH1_DMA_CHANNEL!"11"}
#define STM32_DAC_DAC1_CH2_DMA_CHANNEL ${doc.STM32_DAC_DAC1_CH2_DMA_CHANNEL!"12"}
#define STM32_DAC_DAC1_CH1_DMA_STREAM ${doc.STM32_DAC_DAC1_CH1_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"}
#define STM32_DAC_DAC1_CH2_DMA_STREAM ${doc.STM32_DAC_DAC1_CH2_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"}
/*
* GPT driver system settings.
@ -191,12 +191,12 @@
#define STM32_I2C_USE_I2C2 ${doc.STM32_I2C_USE_I2C2!"FALSE"}
#define STM32_I2C_USE_I2C3 ${doc.STM32_I2C_USE_I2C3!"FALSE"}
#define STM32_I2C_BUSY_TIMEOUT ${doc.STM32_I2C_BUSY_TIMEOUT!"50"}
#define STM32_I2C_I2C1_RX_DMA_CHANNEL ${doc.STM32_I2C_I2C1_RX_DMA_CHANNEL!"6"}
#define STM32_I2C_I2C1_TX_DMA_CHANNEL ${doc.STM32_I2C_I2C1_TX_DMA_CHANNEL!"7"}
#define STM32_I2C_I2C2_RX_DMA_CHANNEL ${doc.STM32_I2C_I2C2_RX_DMA_CHANNEL!"8"}
#define STM32_I2C_I2C2_TX_DMA_CHANNEL ${doc.STM32_I2C_I2C2_TX_DMA_CHANNEL!"9"}
#define STM32_I2C_I2C3_RX_DMA_CHANNEL ${doc.STM32_I2C_I2C3_RX_DMA_CHANNEL!"8"}
#define STM32_I2C_I2C3_TX_DMA_CHANNEL ${doc.STM32_I2C_I2C3_TX_DMA_CHANNEL!"9"}
#define STM32_I2C_I2C1_RX_DMA_STREAM ${doc.STM32_I2C_I2C1_RX_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"}
#define STM32_I2C_I2C1_TX_DMA_STREAM ${doc.STM32_I2C_I2C1_TX_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"}
#define STM32_I2C_I2C2_RX_DMA_STREAM ${doc.STM32_I2C_I2C2_RX_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"}
#define STM32_I2C_I2C2_TX_DMA_STREAM ${doc.STM32_I2C_I2C2_TX_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"}
#define STM32_I2C_I2C3_RX_DMA_STREAM ${doc.STM32_I2C_I2C3_RX_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"}
#define STM32_I2C_I2C3_TX_DMA_STREAM ${doc.STM32_I2C_I2C3_TX_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"}
#define STM32_I2C_I2C1_IRQ_PRIORITY ${doc.STM32_I2C_I2C1_IRQ_PRIORITY!"5"}
#define STM32_I2C_I2C2_IRQ_PRIORITY ${doc.STM32_I2C_I2C2_IRQ_PRIORITY!"5"}
#define STM32_I2C_I2C3_IRQ_PRIORITY ${doc.STM32_I2C_I2C3_IRQ_PRIORITY!"5"}
@ -272,12 +272,12 @@
#define STM32_SPI_USE_SPI1 ${doc.STM32_SPI_USE_SPI1!"FALSE"}
#define STM32_SPI_USE_SPI2 ${doc.STM32_SPI_USE_SPI2!"FALSE"}
#define STM32_SPI_USE_SPI3 ${doc.STM32_SPI_USE_SPI3!"FALSE"}
#define STM32_SPI_SPI1_RX_DMA_CHANNEL ${doc.STM32_SPI_SPI1_RX_DMA_CHANNEL!"0"}
#define STM32_SPI_SPI1_TX_DMA_CHANNEL ${doc.STM32_SPI_SPI1_TX_DMA_CHANNEL!"1"}
#define STM32_SPI_SPI2_RX_DMA_CHANNEL ${doc.STM32_SPI_SPI2_RX_DMA_CHANNEL!"2"}
#define STM32_SPI_SPI2_TX_DMA_CHANNEL ${doc.STM32_SPI_SPI2_TX_DMA_CHANNEL!"3"}
#define STM32_SPI_SPI3_RX_DMA_CHANNEL ${doc.STM32_SPI_SPI3_RX_DMA_CHANNEL!"4"}
#define STM32_SPI_SPI3_TX_DMA_CHANNEL ${doc.STM32_SPI_SPI3_TX_DMA_CHANNEL!"5"}
#define STM32_SPI_SPI1_RX_DMA_STREAM ${doc.STM32_SPI_SPI1_RX_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"}
#define STM32_SPI_SPI1_TX_DMA_STREAM ${doc.STM32_SPI_SPI1_TX_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"}
#define STM32_SPI_SPI2_RX_DMA_STREAM ${doc.STM32_SPI_SPI2_RX_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"}
#define STM32_SPI_SPI2_TX_DMA_STREAM ${doc.STM32_SPI_SPI2_TX_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"}
#define STM32_SPI_SPI3_RX_DMA_STREAM ${doc.STM32_SPI_SPI3_RX_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"}
#define STM32_SPI_SPI3_TX_DMA_STREAM ${doc.STM32_SPI_SPI3_TX_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"}
#define STM32_SPI_SPI1_DMA_PRIORITY ${doc.STM32_SPI_SPI1_DMA_PRIORITY!"1"}
#define STM32_SPI_SPI2_DMA_PRIORITY ${doc.STM32_SPI_SPI2_DMA_PRIORITY!"1"}
#define STM32_SPI_SPI3_DMA_PRIORITY ${doc.STM32_SPI_SPI3_DMA_PRIORITY!"1"}
@ -305,16 +305,16 @@
#define STM32_UART_USE_USART3 ${doc.STM32_UART_USE_USART3!"FALSE"}
#define STM32_UART_USE_UART4 ${doc.STM32_UART_USE_UART4!"FALSE"}
#define STM32_UART_USE_UART5 ${doc.STM32_UART_USE_UART5!"FALSE"}
#define STM32_UART_USART1_RX_DMA_CHANNEL ${doc.STM32_UART_USART1_RX_DMA_CHANNEL!"13"}
#define STM32_UART_USART1_TX_DMA_CHANNEL ${doc.STM32_UART_USART1_TX_DMA_CHANNEL!"0"}
#define STM32_UART_USART2_RX_DMA_CHANNEL ${doc.STM32_UART_USART2_RX_DMA_CHANNEL!"1"}
#define STM32_UART_USART2_TX_DMA_CHANNEL ${doc.STM32_UART_USART2_TX_DMA_CHANNEL!"2"}
#define STM32_UART_USART3_RX_DMA_CHANNEL ${doc.STM32_UART_USART3_RX_DMA_CHANNEL!"3"}
#define STM32_UART_USART3_TX_DMA_CHANNEL ${doc.STM32_UART_USART3_TX_DMA_CHANNEL!"4"}
#define STM32_UART_UART4_RX_DMA_CHANNEL ${doc.STM32_UART_UART4_RX_DMA_CHANNEL!"5"}
#define STM32_UART_UART4_TX_DMA_CHANNEL ${doc.STM32_UART_UART4_TX_DMA_CHANNEL!"6"}
#define STM32_UART_UART5_RX_DMA_CHANNEL ${doc.STM32_UART_UART5_RX_DMA_CHANNEL!"7"}
#define STM32_UART_UART5_TX_DMA_CHANNEL ${doc.STM32_UART_UART5_TX_DMA_CHANNEL!"8"}
#define STM32_UART_USART1_RX_DMA_STREAM ${doc.STM32_UART_USART1_RX_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"}
#define STM32_UART_USART1_TX_DMA_STREAM ${doc.STM32_UART_USART1_TX_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"}
#define STM32_UART_USART2_RX_DMA_STREAM ${doc.STM32_UART_USART2_RX_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"}
#define STM32_UART_USART2_TX_DMA_STREAM ${doc.STM32_UART_USART2_TX_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"}
#define STM32_UART_USART3_RX_DMA_STREAM ${doc.STM32_UART_USART3_RX_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"}
#define STM32_UART_USART3_TX_DMA_STREAM ${doc.STM32_UART_USART3_TX_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"}
#define STM32_UART_UART4_RX_DMA_STREAM ${doc.STM32_UART_UART4_RX_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"}
#define STM32_UART_UART4_TX_DMA_STREAM ${doc.STM32_UART_UART4_TX_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"}
#define STM32_UART_UART5_RX_DMA_STREAM ${doc.STM32_UART_UART5_RX_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"}
#define STM32_UART_UART5_TX_DMA_STREAM ${doc.STM32_UART_UART5_TX_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"}
#define STM32_UART_USART1_IRQ_PRIORITY ${doc.STM32_UART_USART1_IRQ_PRIORITY!"12"}
#define STM32_UART_USART2_IRQ_PRIORITY ${doc.STM32_UART_USART2_IRQ_PRIORITY!"12"}
#define STM32_UART_USART3_IRQ_PRIORITY ${doc.STM32_UART_USART3_IRQ_PRIORITY!"12"}
@ -348,8 +348,8 @@
#define STM32_WSPI_OCTOSPI2_PRESCALER_VALUE ${doc.STM32_WSPI_OCTOSPI2_PRESCALER_VALUE!"1"}
#define STM32_WSPI_OCTOSPI1_IRQ_PRIORITY ${doc.STM32_WSPI_OCTOSPI1_IRQ_PRIORITY!"10"}
#define STM32_WSPI_OCTOSPI2_IRQ_PRIORITY ${doc.STM32_WSPI_OCTOSPI2_IRQ_PRIORITY!"10"}
#define STM32_WSPI_OCTOSPI1_DMA_CHANNEL ${doc.STM32_WSPI_OCTOSPI1_DMA_CHANNEL!"9"}
#define STM32_WSPI_OCTOSPI2_DMA_CHANNEL ${doc.STM32_WSPI_OCTOSPI2_DMA_CHANNEL!"10"}
#define STM32_WSPI_OCTOSPI1_DMA_STREAM ${doc.STM32_WSPI_OCTOSPI1_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"}
#define STM32_WSPI_OCTOSPI2_DMA_STREAM ${doc.STM32_WSPI_OCTOSPI2_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"}
#define STM32_WSPI_OCTOSPI1_DMA_PRIORITY ${doc.STM32_WSPI_OCTOSPI1_DMA_PRIORITY!"1"}
#define STM32_WSPI_OCTOSPI2_DMA_PRIORITY ${doc.STM32_WSPI_OCTOSPI2_DMA_PRIORITY!"1"}
#define STM32_WSPI_OCTOSPI1_DMA_IRQ_PRIORITY ${doc.STM32_WSPI_OCTOSPI1_DMA_IRQ_PRIORITY!"10"}