OCTOSPI driver initial setup.
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@12367 110e8d01-0319-4d1e-a829-52ad28d1bb01
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ifeq ($(USE_SMART_BUILD),yes)
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ifneq ($(findstring HAL_USE_WSPI TRUE,$(HALCONF)),)
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PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/OCTOSPIv1/hal_wspi_lld.c
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endif
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else
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PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/OCTOSPIv1/hal_wspi_lld.c
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endif
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PLATFORMINC += $(CHIBIOS)/os/hal/ports/STM32/LLD/OCTOSPIv1
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/*
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ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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/**
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* @file OCTOSPIv1/hal_wspi_lld.c
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* @brief STM32 WSPI subsystem low level driver source.
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*
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* @addtogroup WSPI
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* @{
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*/
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#include "hal.h"
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#if (HAL_USE_WSPI == TRUE) || defined(__DOXYGEN__)
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/*===========================================================================*/
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/* Driver local definitions. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver exported variables. */
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/*===========================================================================*/
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/** @brief OCTOSPI1 driver identifier.*/
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#if STM32_WSPI_USE_OCTOSPI1 || defined(__DOXYGEN__)
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WSPIDriver WSPID1;
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#endif
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/*===========================================================================*/
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/* Driver local variables and types. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver local functions. */
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/*===========================================================================*/
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/**
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* @brief Shared service routine.
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*
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* @param[in] wspip pointer to the @p WSPIDriver object
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* @param[in] flags pre-shifted content of the ISR register
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*/
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static void wspi_lld_serve_dma_interrupt(WSPIDriver *wspip, uint32_t flags) {
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(void)wspip;
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(void)flags;
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/* DMA errors handling.*/
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#if defined(STM32_WSPI_DMA_ERROR_HOOK)
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if ((flags & (STM32_DMA_ISR_TEIF | STM32_DMA_ISR_DMEIF)) != 0) {
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STM32_WSPI_DMA_ERROR_HOOK(wspip);
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}
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#endif
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}
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/**
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* @brief Shared service routine.
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*
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* @param[in] wspip pointer to the @p WSPIDriver object
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*/
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static void wspi_lld_serve_interrupt(WSPIDriver *wspip) {
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/* Portable WSPI ISR code defined in the high level driver, note, it is
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a macro.*/
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_wspi_isr_code(wspip);
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/* Stop everything, we need to give DMA enough time to complete the ongoing
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operation. Race condition hidden here.*/
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while (dmaStreamGetTransactionSize(wspip->dma) > 0U)
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;
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dmaStreamDisable(wspip->dma);
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}
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/*===========================================================================*/
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/* Driver interrupt handlers. */
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/*===========================================================================*/
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#if STM32_WSPI_USE_OCTOSPI1 || defined(__DOXYGEN__)
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#if !defined(STM32_OCTOSPI1_SUPPRESS_ISR)
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#if !defined(STM32_OCTOSPI1_HANDLER)
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#error "STM32_OCTOSPI1_HANDLER not defined"
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#endif
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/**
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* @brief STM32_OCTOSPI1_HANDLER interrupt handler.
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*
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* @isr
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*/
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OSAL_IRQ_HANDLER(STM32_OCTOSPI1_HANDLER) {
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OSAL_IRQ_PROLOGUE();
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OCTOSPI->FCR = OCTOSPI_FCR_CTEF | OCTOSPI_FCR_CTCF |
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OCTOSPI_FCR_CSMF | OCTOSPI_FCR_CTOF;
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wspi_lld_serve_interrupt(&WSPID1);
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OSAL_IRQ_EPILOGUE();
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}
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#endif /* !defined(STM32_OCTOSPI1_SUPPRESS_ISR) */
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#endif /* STM32_WSPI_USE_OCTOSPI1 */
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/*===========================================================================*/
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/* Driver exported functions. */
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/*===========================================================================*/
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/**
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* @brief Low level WSPI driver initialization.
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*
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* @notapi
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*/
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void wspi_lld_init(void) {
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#if STM32_WSPI_USE_OCTOSPI1
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wspiObjectInit(&WSPID1);
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WSPID1.ospi = OCTOSPI;
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WSPID1.dma = STM32_DMA_STREAM(STM32_WSPI_OCTOSPI1_DMA_STREAM);
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WSPID1.dmamode = STM32_DMA_CR_CHSEL(OCTOSPI1_DMA_CHANNEL) |
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STM32_DMA_CR_PL(STM32_WSPI_OCTOSPI1_DMA_PRIORITY) |
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STM32_DMA_CR_PSIZE_BYTE |
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STM32_DMA_CR_MSIZE_BYTE |
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STM32_DMA_CR_MINC |
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STM32_DMA_CR_DMEIE |
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STM32_DMA_CR_TEIE;
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nvicEnableVector(STM32_OCTOSPI1_NUMBER, STM32_WSPI_OCTOSPI1_IRQ_PRIORITY);
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#endif
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}
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/**
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* @brief Configures and activates the WSPI peripheral.
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*
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* @param[in] wspip pointer to the @p WSPIDriver object
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*
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* @notapi
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*/
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void wspi_lld_start(WSPIDriver *wspip) {
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/* If in stopped state then full initialization.*/
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if (wspip->state == WSPI_STOP) {
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#if STM32_WSPI_USE_OCTOSPI1
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if (&WSPID1 == wspip) {
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bool b = dmaStreamAllocate(wspip->dma,
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STM32_WSPI_OCTOSPI1_DMA_IRQ_PRIORITY,
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(stm32_dmaisr_t)wspi_lld_serve_dma_interrupt,
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(void *)wspip);
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osalDbgAssert(!b, "stream already allocated");
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rccEnableOCTOSPI1(true);
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}
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#endif
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/* Common initializations.*/
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dmaStreamSetPeripheral(wspip->dma, &wspip->ospi->DR);
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}
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/* WSPI setup and enable.*/
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wspip->ospi->DCR = wspip->config->dcr;
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wspip->ospi->CR = ((STM32_WSPI_OCTOSPI1_PRESCALER_VALUE - 1U) << 24U) |
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OCTOSPI_CR_TCIE | OCTOSPI_CR_DMAEN | OCTOSPI_CR_EN;
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wspip->ospi->FCR = OCTOSPI_FCR_CTEF | OCTOSPI_FCR_CTCF |
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OCTOSPI_FCR_CSMF | OCTOSPI_FCR_CTOF;
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}
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/**
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* @brief Deactivates the WSPI peripheral.
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*
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* @param[in] wspip pointer to the @p WSPIDriver object
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*
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* @notapi
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*/
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void wspi_lld_stop(WSPIDriver *wspip) {
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/* If in ready state then disables the OCTOSPI clock.*/
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if (wspip->state == WSPI_READY) {
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/* WSPI disable.*/
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wspip->ospi->CR = 0U;
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/* Releasing the DMA.*/
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dmaStreamRelease(wspip->dma);
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/* Stopping involved clocks.*/
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#if STM32_WSPI_USE_OCTOSPI1
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if (&WSPID1 == wspip) {
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rccDisableOCTOSPI1();
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}
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#endif
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}
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}
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/**
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* @brief Sends a command without data phase.
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* @post At the end of the operation the configured callback is invoked.
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*
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* @param[in] wspip pointer to the @p WSPIDriver object
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* @param[in] cmdp pointer to the command descriptor
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*
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* @notapi
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*/
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void wspi_lld_command(WSPIDriver *wspip, const wspi_command_t *cmdp) {
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#if STM32_USE_STM32_D1_WORKAROUND == TRUE
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/* If it is a command without address and alternate phases then the command
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is sent as an alternate byte, the command phase is suppressed.*/
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if ((cmdp->cfg & (WSPI_CFG_ADDR_MODE_MASK | WSPI_CFG_ALT_MODE_MASK)) == 0U) {
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/* The command mode field is copied in the alternate mode field. All
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other fields are not used in this scenario.*/
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wspip->ospi->DLR = 0U;
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wspip->ospi->ABR = cmdp->cmd;
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wspip->ospi->CCR = (cmdp->cfg & WSPI_CFG_CMD_MODE_MASK) << 6U;
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return;
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}
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#endif
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wspip->ospi->DLR = 0U;
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wspip->ospi->ABR = cmdp->alt;
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wspip->ospi->CCR = cmdp->cmd | cmdp->cfg;
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if ((cmdp->cfg & WSPI_CFG_ADDR_MODE_MASK) != WSPI_CFG_ADDR_MODE_NONE) {
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wspip->ospi->AR = cmdp->addr;
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}
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}
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/**
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* @brief Sends a command with data over the WSPI bus.
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* @post At the end of the operation the configured callback is invoked.
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*
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* @param[in] wspip pointer to the @p WSPIDriver object
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* @param[in] cmdp pointer to the command descriptor
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* @param[in] n number of bytes to send
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* @param[in] txbuf the pointer to the transmit buffer
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*
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* @notapi
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*/
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void wspi_lld_send(WSPIDriver *wspip, const wspi_command_t *cmdp,
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size_t n, const uint8_t *txbuf) {
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dmaStreamSetMemory0(wspip->dma, txbuf);
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dmaStreamSetTransactionSize(wspip->dma, n);
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dmaStreamSetMode(wspip->dma, wspip->dmamode | STM32_DMA_CR_DIR_M2P);
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wspip->ospi->DLR = n - 1;
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wspip->ospi->ABR = cmdp->alt;
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wspip->ospi->CCR = cmdp->cmd | cmdp->cfg;
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if ((cmdp->cfg & WSPI_CFG_ADDR_MODE_MASK) != WSPI_CFG_ADDR_MODE_NONE) {
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wspip->ospi->AR = cmdp->addr;
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}
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dmaStreamEnable(wspip->dma);
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}
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/**
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* @brief Sends a command then receives data over the WSPI bus.
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* @post At the end of the operation the configured callback is invoked.
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*
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* @param[in] wspip pointer to the @p WSPIDriver object
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* @param[in] cmdp pointer to the command descriptor
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* @param[in] n number of bytes to send
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* @param[out] rxbuf the pointer to the receive buffer
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*
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* @notapi
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*/
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void wspi_lld_receive(WSPIDriver *wspip, const wspi_command_t *cmdp,
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size_t n, uint8_t *rxbuf) {
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dmaStreamSetMemory0(wspip->dma, rxbuf);
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dmaStreamSetTransactionSize(wspip->dma, n);
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dmaStreamSetMode(wspip->dma, wspip->dmamode | STM32_DMA_CR_DIR_P2M);
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wspip->ospi->DLR = n - 1;
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wspip->ospi->ABR = cmdp->alt;
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wspip->ospi->CCR = cmdp->cmd | cmdp->cfg |
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OCTOSPI_CCR_DUMMY_CYCLES(cmdp->dummy) |
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OCTOSPI_CCR_FMODE_0;
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if ((cmdp->cfg & WSPI_CFG_ADDR_MODE_MASK) != WSPI_CFG_ADDR_MODE_NONE) {
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wspip->ospi->AR = cmdp->addr;
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}
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dmaStreamEnable(wspip->dma);
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}
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#if (WSPI_SUPPORTS_MEMMAP == TRUE) || defined(__DOXYGEN__)
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/**
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* @brief Maps in memory space a WSPI flash device.
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* @pre The memory flash device must be initialized appropriately
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* before mapping it in memory space.
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*
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* @param[in] wspip pointer to the @p WSPIDriver object
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* @param[in] cmdp pointer to the command descriptor
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* @param[out] addrp pointer to the memory start address of the mapped
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* flash or @p NULL
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*
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* @notapi
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*/
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void wspi_lld_map_flash(WSPIDriver *wspip,
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const wspi_command_t *cmdp,
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uint8_t **addrp) {
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/* Disabling the DMA request while in memory mapped mode.*/
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wspip->ospi->CR &= ~OCTOSPI_CR_DMAEN;
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/* Starting memory mapped mode using the passed parameters.*/
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wspip->ospi->DLR = 0;
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wspip->ospi->ABR = 0;
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wspip->ospi->AR = 0;
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wspip->ospi->CCR = cmdp->cmd | cmdp->cfg |
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OCTOSPI_CCR_FMODE_1 | OCTOSPI_CCR_FMODE_0;
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/* Mapped flash absolute base address.*/
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if (addrp != NULL) {
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*addrp = (uint8_t *)0x90000000;
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}
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}
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/**
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* @brief Unmaps from memory space a WSPI flash device.
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* @post The memory flash device must be re-initialized for normal
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* commands exchange.
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*
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* @param[in] wspip pointer to the @p WSPIDriver object
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*
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* @notapi
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*/
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void wspi_lld_unmap_flash(WSPIDriver *wspip) {
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/* Aborting memory mapped mode.*/
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wspip->ospi->CR |= OCTOSPI_CR_ABORT;
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while ((wspip->ospi->CR & OCTOSPI_CR_ABORT) != 0U) {
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}
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/* Re-enabling DMA request, we are going back to indirect mode.*/
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wspip->ospi->CR |= OCTOSPI_CR_DMAEN;
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}
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#endif /* WSPI_SUPPORTS_MEMMAP == TRUE */
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#endif /* HAL_USE_WSPI */
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/** @} */
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@ -0,0 +1,258 @@
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/*
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ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
|
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You may obtain a copy of the License at
|
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|
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http://www.apache.org/licenses/LICENSE-2.0
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|
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Unless required by applicable law or agreed to in writing, software
|
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distributed under the License is distributed on an "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
See the License for the specific language governing permissions and
|
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limitations under the License.
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*/
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/**
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* @file OCTOSPIv1/hal_wspi_lld.h
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* @brief STM32 WSPI subsystem low level driver header.
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*
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* @addtogroup WSPI
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* @{
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*/
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#ifndef HAL_WSPI_LLD_H
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#define HAL_WSPI_LLD_H
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#if (HAL_USE_WSPI == TRUE) || defined(__DOXYGEN__)
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/*===========================================================================*/
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/* Driver constants. */
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/*===========================================================================*/
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/**
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* @name WSPI implementation capabilities
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* @{
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*/
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#define WSPI_SUPPORTS_MEMMAP TRUE
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#define WSPI_DEFAULT_CFG_MASKS TRUE
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/** @} */
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/*===========================================================================*/
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/* Driver pre-compile time settings. */
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/*===========================================================================*/
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/**
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* @name Configuration options
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* @{
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*/
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/**
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* @brief WSPID1 driver enable switch.
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* @details If set to @p TRUE the support for OCTOSPI1 is included.
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* @note The default is @p FALSE.
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*/
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#if !defined(STM32_WSPI_USE_OCTOSPI1) || defined(__DOXYGEN__)
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#define STM32_WSPI_USE_OCTOSPI1 FALSE
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#endif
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/**
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* @brief OCTOSPI1 prescaler setting.
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* @note This is the prescaler divider value 1..256. The maximum frequency
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* varies depending on the STM32 model and operating conditions,
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* find the details in the data sheet.
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*/
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#if !defined(STM32_WSPI_OCTOSPI1_PRESCALER_VALUE) || defined(__DOXYGEN__)
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#define STM32_WSPI_OCTOSPI1_PRESCALER_VALUE 1
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#endif
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/**
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* @brief OCTOSPI1 interrupt priority level setting.
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*/
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#if !defined(STM32_WSPI_OCTOSPI1_IRQ_PRIORITY) || defined(__DOXYGEN__)
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#define STM32_WSPI_OCTOSPI1_IRQ_PRIORITY 10
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#endif
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/**
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* @brief OCTOSPI1 DMA priority (0..3|lowest..highest).
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*/
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#if !defined(STM32_WSPI_OCTOSPI1_DMA_PRIORITY) || defined(__DOXYGEN__)
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#define STM32_WSPI_OCTOSPI1_DMA_PRIORITY 1
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#endif
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/**
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* @brief OCTOSPI1 DMA interrupt priority level setting.
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*/
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#if !defined(STM32_WSPI_OCTOSPI1_DMA_IRQ_PRIORITY) || defined(__DOXYGEN__)
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#define STM32_WSPI_OCTOSPI1_DMA_IRQ_PRIORITY 10
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#endif
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/**
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* @brief OCTOSPI DMA error hook.
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*/
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#if !defined(STM32_WSPI_DMA_ERROR_HOOK) || defined(__DOXYGEN__)
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#define STM32_WSPI_DMA_ERROR_HOOK(qspip) osalSysHalt("DMA failure")
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#endif
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/** @} */
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/*===========================================================================*/
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/* Derived constants and error checks. */
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/*===========================================================================*/
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||||
|
||||
#if !defined(STM32_HAS_OCTOSPI1)
|
||||
#define STM32_HAS_OCTOSPI1 FALSE
|
||||
#endif
|
||||
|
||||
#if STM32_WSPI_USE_OCTOSPI1 && !STM32_HAS_OCTOSPI1
|
||||
#error "OCTOSPI1 not present in the selected device"
|
||||
#endif
|
||||
|
||||
#if !STM32_WSPI_USE_OCTOSPI1
|
||||
#error "WSPI driver activated but no OCTOSPI peripheral assigned"
|
||||
#endif
|
||||
|
||||
/* Check on OCTOSPI prescaler setting.*/
|
||||
#if (STM32_WSPI_OCTOSPI1_PRESCALER_VALUE < 1) || \
|
||||
(STM32_WSPI_OCTOSPI1_PRESCALER_VALUE > 256)
|
||||
#error "STM32_WSPI_OCTOSPI1_PRESCALER_VALUE not within 1..256"
|
||||
#endif
|
||||
|
||||
/* Check on IRQ priorities.*/
|
||||
#if STM32_WSPI_USE_OCTOSPI1 && \
|
||||
!OSAL_IRQ_IS_VALID_PRIORITY(STM32_WSPI_OCTOSPI1_IRQ_PRIORITY)
|
||||
#error "Invalid IRQ priority assigned to OCTOSPI1"
|
||||
#endif
|
||||
|
||||
#if STM32_WSPI_USE_OCTOSPI1 && \
|
||||
!OSAL_IRQ_IS_VALID_PRIORITY(STM32_WSPI_OCTOSPI1_DMA_IRQ_PRIORITY)
|
||||
#error "Invalid IRQ priority assigned to OCTOSPI1 DMA"
|
||||
#endif
|
||||
|
||||
/* Check on the presence of the DMA chennels settings in mcuconf.h.*/
|
||||
#if STM32_WSPI_USE_OCTOSPI1 && !defined(STM32_WSPI_OCTOSPI1_DMA_CHANNEL)
|
||||
#error "OCTOSPI1 DMA channel not defined"
|
||||
#endif
|
||||
|
||||
/* Check on the validity of the assigned DMA channels.*/
|
||||
#if STM32_WSPI_USE_OCTOSPI1 && \
|
||||
!STM32_DMA_IS_VALID_CHANNEL(STM32_OCTOSPI1_DMA_MSK)
|
||||
#error "invalid DMA stream associated to OCTOSPI1"
|
||||
#endif
|
||||
|
||||
/* Check on DMA channels priority.*/
|
||||
#if STM32_WSPI_USE_OCTOSPI1 && \
|
||||
!STM32_DMA_IS_VALID_PRIORITY(STM32_WSPI_OCTOSPI1_DMA_PRIORITY)
|
||||
#error "Invalid DMA priority assigned to OCTOSPI1"
|
||||
#endif
|
||||
|
||||
#if !defined(STM32_DMA_REQUIRED)
|
||||
#define STM32_DMA_REQUIRED
|
||||
#endif
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver data structures and types. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @brief Driver configuration structure.
|
||||
*/
|
||||
struct hal_wspi_config {
|
||||
/**
|
||||
* @brief Operation complete callback or @p NULL.
|
||||
*/
|
||||
wspicallback_t end_cb;
|
||||
/* End of the mandatory fields.*/
|
||||
/**
|
||||
* @brief DCR1 register initialization data.
|
||||
*/
|
||||
uint32_t dcr1;
|
||||
/**
|
||||
* @brief DCR2 register initialization data.
|
||||
*/
|
||||
uint32_t dcr2;
|
||||
/**
|
||||
* @brief DCR3 register initialization data.
|
||||
*/
|
||||
uint32_t dcr3;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief Structure representing an WSPI driver.
|
||||
*/
|
||||
struct hal_wspi_driver {
|
||||
/**
|
||||
* @brief Driver state.
|
||||
*/
|
||||
wspistate_t state;
|
||||
/**
|
||||
* @brief Current configuration data.
|
||||
*/
|
||||
const WSPIConfig *config;
|
||||
#if (WSPI_USE_WAIT == TRUE) || defined(__DOXYGEN__)
|
||||
/**
|
||||
* @brief Waiting thread.
|
||||
*/
|
||||
thread_reference_t thread;
|
||||
#endif /* WSPI_USE_WAIT */
|
||||
#if (WSPI_USE_MUTUAL_EXCLUSION == TRUE) || defined(__DOXYGEN__)
|
||||
/**
|
||||
* @brief Mutex protecting the peripheral.
|
||||
*/
|
||||
mutex_t mutex;
|
||||
#endif /* WSPI_USE_MUTUAL_EXCLUSION */
|
||||
#if defined(WSPI_DRIVER_EXT_FIELDS)
|
||||
WSPI_DRIVER_EXT_FIELDS
|
||||
#endif
|
||||
/* End of the mandatory fields.*/
|
||||
/**
|
||||
* @brief Pointer to the OCTOSPIx registers block.
|
||||
*/
|
||||
OCTOSPI_TypeDef *ospi;
|
||||
/**
|
||||
* @brief OCTOSPI DMA stream.
|
||||
*/
|
||||
const stm32_dma_stream_t *dma;
|
||||
/**
|
||||
* @brief OCTOSPI DMA mode bit mask.
|
||||
*/
|
||||
uint32_t dmamode;
|
||||
};
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver macros. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* External declarations. */
|
||||
/*===========================================================================*/
|
||||
|
||||
#if (STM32_WSPI_USE_OCTOSPI1 == TRUE) && !defined(__DOXYGEN__)
|
||||
extern WSPIDriver WSPID1;
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
void wspi_lld_init(void);
|
||||
void wspi_lld_start(WSPIDriver *wspip);
|
||||
void wspi_lld_stop(WSPIDriver *wspip);
|
||||
void wspi_lld_command(WSPIDriver *wspip, const wspi_command_t *cmdp);
|
||||
void wspi_lld_send(WSPIDriver *wspip, const wspi_command_t *cmdp,
|
||||
size_t n, const uint8_t *txbuf);
|
||||
void wspi_lld_receive(WSPIDriver *wspip, const wspi_command_t *cmdp,
|
||||
size_t n, uint8_t *rxbuf);
|
||||
#if WSPI_SUPPORTS_MEMMAP == TRUE
|
||||
void wspi_lld_map_flash(WSPIDriver *wspip,
|
||||
const wspi_command_t *cmdp,
|
||||
uint8_t **addrp);
|
||||
void wspi_lld_unmap_flash(WSPIDriver *wspip);
|
||||
#endif
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* HAL_USE_WSPI */
|
||||
|
||||
#endif /* HAL_WSPI_LLD_H */
|
||||
|
||||
/** @} */
|
|
@ -15,8 +15,8 @@
|
|||
*/
|
||||
|
||||
/**
|
||||
* @file hal_wspi_lld.c
|
||||
* @brief PLATFORM WSPI subsystem low level driver source.
|
||||
* @file QUADSPIv1//hal_wspi_lld.c
|
||||
* @brief STM32 WSPI subsystem low level driver source.
|
||||
*
|
||||
* @addtogroup WSPI
|
||||
* @{
|
||||
|
|
|
@ -15,8 +15,8 @@
|
|||
*/
|
||||
|
||||
/**
|
||||
* @file hal_wspi_lld.h
|
||||
* @brief PLATFORM WSPI subsystem low level driver header.
|
||||
* @file QUADSPIv1/hal_wspi_lld.h
|
||||
* @brief STM32 WSPI subsystem low level driver header.
|
||||
*
|
||||
* @addtogroup WSPI
|
||||
* @{
|
||||
|
@ -193,6 +193,10 @@
|
|||
/* Derived constants and error checks. */
|
||||
/*===========================================================================*/
|
||||
|
||||
#if !defined(STM32_HAS_QUADSPI1)
|
||||
#define STM32_HAS_QUADSPI1 FALSE
|
||||
#endif
|
||||
|
||||
#if STM32_WSPI_USE_QUADSPI1 && !STM32_HAS_QUADSPI1
|
||||
#error "QUADSPI1 not present in the selected device"
|
||||
#endif
|
||||
|
|
Loading…
Reference in New Issue