[KINETIS] Add PIT registers
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@7244 35acf78f-673a-0410-8e92-d51de3d6d3f4
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@ -200,6 +200,18 @@ typedef struct
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__IO uint8_t CHCFG[4];
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__IO uint8_t CHCFG[4];
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} DMAMUX_TypeDef;
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} DMAMUX_TypeDef;
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/** PIT - Peripheral register structure */
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typedef struct {
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__IO uint32_t MCR; /* PIT Module Control Register */
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uint8_t RESERVED0[252];
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struct PIT_CHANNEL {
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__IO uint32_t LDVAL; /* Timer Load Value Register */
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__IO uint32_t CVAL; /* Current Timer Value Register */
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__IO uint32_t TCTRL; /* Timer Control Register */
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__IO uint32_t TFLG; /* Timer Flag Register */
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} CHANNEL[4];
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} PIT_TypeDef;
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typedef struct
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typedef struct
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{
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{
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__IO uint32_t SC; /* Status and Control */
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__IO uint32_t SC; /* Status and Control */
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@ -493,6 +505,7 @@ typedef struct {
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#define DMA_BASE ((uint32_t)0x40008100)
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#define DMA_BASE ((uint32_t)0x40008100)
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#define DMAMUX_BASE ((uint32_t)0x40021000)
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#define DMAMUX_BASE ((uint32_t)0x40021000)
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#define SPI0_BASE ((uint32_t)0x4002C000)
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#define SPI0_BASE ((uint32_t)0x4002C000)
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#define PIT_BASE ((uint32_t)0x40037000)
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#define FTM0_BASE ((uint32_t)0x40038000)
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#define FTM0_BASE ((uint32_t)0x40038000)
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#define FTM1_BASE ((uint32_t)0x40039000)
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#define FTM1_BASE ((uint32_t)0x40039000)
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#define ADC0_BASE ((uint32_t)0x4003B000)
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#define ADC0_BASE ((uint32_t)0x4003B000)
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@ -524,6 +537,7 @@ typedef struct {
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/****************************************************************/
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/****************************************************************/
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#define DMA ((DMA_TypeDef *) DMA_BASE)
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#define DMA ((DMA_TypeDef *) DMA_BASE)
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#define DMAMUX ((DMAMUX_TypeDef *) DMAMUX_BASE)
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#define DMAMUX ((DMAMUX_TypeDef *) DMAMUX_BASE)
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#define PIT ((PIT_TypeDef *) PIT_BASE)
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#define FTM0 ((FTM_TypeDef *) FTM0_BASE)
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#define FTM0 ((FTM_TypeDef *) FTM0_BASE)
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#define FTM1 ((FTM_TypeDef *) FTM1_BASE)
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#define FTM1 ((FTM_TypeDef *) FTM1_BASE)
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#define ADC0 ((ADC_TypeDef *) ADC0_BASE)
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#define ADC0 ((ADC_TypeDef *) ADC0_BASE)
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@ -1261,6 +1275,28 @@ typedef struct {
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#define FTM_PWMLOAD_LDOK_MASK 0x200u
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#define FTM_PWMLOAD_LDOK_MASK 0x200u
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#define FTM_PWMLOAD_LDOK_SHIFT 9
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#define FTM_PWMLOAD_LDOK_SHIFT 9
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/****************************************************************/
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/* */
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/* Periodic Interrupt Timer (PIT) */
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/* */
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/****************************************************************/
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/* MCR Bit Fields */
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#define PIT_MCR_FRZ 0x1u
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#define PIT_MCR_MDIS 0x2u
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/* LDVAL Bit Fields */
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#define PIT_LDVAL_TSV_MASK 0xFFFFFFFFu
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#define PIT_LDVAL_TSV_SHIFT 0
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#define PIT_LDVAL_TSV(x) (((uint32_t)(((uint32_t)(x))<<PIT_LDVAL_TSV_SHIFT))&PIT_LDVAL_TSV_MASK)
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/* CVAL Bit Fields */
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#define PIT_CVAL_TVL_MASK 0xFFFFFFFFu
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#define PIT_CVAL_TVL_SHIFT 0
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#define PIT_CVAL_TVL(x) (((uint32_t)(((uint32_t)(x))<<PIT_CVAL_TVL_SHIFT))&PIT_CVAL_TVL_MASK)
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/* TCTRL Bit Fields */
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#define PIT_TCTRL_TEN 0x1u
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#define PIT_TCTRL_TIE 0x2u
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/* TFLG Bit Fields */
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#define PIT_TFLG_TIF 0x1u
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/****************************************************************/
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/****************************************************************/
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/* */
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/* */
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/* Analog-to-Digital Converter (ADC) */
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/* Analog-to-Digital Converter (ADC) */
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