From d82fa57b9cfb363cc6cc030c8d95f3d58fd5bfdb Mon Sep 17 00:00:00 2001 From: acirillo87 Date: Sat, 1 Jun 2013 14:55:08 +0000 Subject: [PATCH] git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@5790 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- .../platforms/SPC560BCxx/spc560bc_registry.h | 121 ++ os/hal/platforms/SPC560Pxx/spc560p_registry.h | 21 + os/hal/platforms/SPC56ELxx/spc56el_registry.h | 41 + os/hal/platforms/SPC5xx/FlexCAN_v1/can_lld.c | 1618 +++++++++++++++++ os/hal/platforms/SPC5xx/FlexCAN_v1/can_lld.h | 520 ++++++ .../SPC5xx/FlexCAN_v1/spc5_flexcan.h | 442 +++++ testhal/SPC560BCxx/CAN/Makefile | 140 ++ testhal/SPC560BCxx/CAN/chconf.h | 529 ++++++ testhal/SPC560BCxx/CAN/halconf.h | 371 ++++ testhal/SPC560BCxx/CAN/main.c | 149 ++ testhal/SPC560BCxx/CAN/mcuconf.h | 223 +++ testhal/SPC560BCxx/CAN/readme.txt | 27 + testhal/SPC560Pxx/CAN/.cproject | 51 + testhal/SPC560Pxx/CAN/.project | 38 + testhal/SPC560Pxx/CAN/Makefile | 140 ++ testhal/SPC560Pxx/CAN/chconf.h | 529 ++++++ testhal/SPC560Pxx/CAN/halconf.h | 371 ++++ testhal/SPC560Pxx/CAN/main.c | 149 ++ testhal/SPC560Pxx/CAN/mcuconf.h | 190 ++ testhal/SPC560Pxx/CAN/readme.txt | 27 + testhal/SPC56ELxx/CAN/.cproject | 51 + testhal/SPC56ELxx/CAN/.project | 38 + testhal/SPC56ELxx/CAN/Makefile | 139 ++ testhal/SPC56ELxx/CAN/chconf.h | 529 ++++++ testhal/SPC56ELxx/CAN/halconf.h | 371 ++++ testhal/SPC56ELxx/CAN/main.c | 149 ++ testhal/SPC56ELxx/CAN/mcuconf.h | 236 +++ testhal/SPC56ELxx/CAN/readme.txt | 27 + 28 files changed, 7237 insertions(+) create mode 100644 os/hal/platforms/SPC5xx/FlexCAN_v1/can_lld.c create mode 100644 os/hal/platforms/SPC5xx/FlexCAN_v1/can_lld.h create mode 100644 os/hal/platforms/SPC5xx/FlexCAN_v1/spc5_flexcan.h create mode 100644 testhal/SPC560BCxx/CAN/Makefile create mode 100644 testhal/SPC560BCxx/CAN/chconf.h create mode 100644 testhal/SPC560BCxx/CAN/halconf.h create mode 100644 testhal/SPC560BCxx/CAN/main.c create mode 100644 testhal/SPC560BCxx/CAN/mcuconf.h create mode 100644 testhal/SPC560BCxx/CAN/readme.txt create mode 100644 testhal/SPC560Pxx/CAN/.cproject create mode 100644 testhal/SPC560Pxx/CAN/.project create mode 100644 testhal/SPC560Pxx/CAN/Makefile create mode 100644 testhal/SPC560Pxx/CAN/chconf.h create mode 100644 testhal/SPC560Pxx/CAN/halconf.h create mode 100644 testhal/SPC560Pxx/CAN/main.c create mode 100644 testhal/SPC560Pxx/CAN/mcuconf.h create mode 100644 testhal/SPC560Pxx/CAN/readme.txt create mode 100644 testhal/SPC56ELxx/CAN/.cproject create mode 100644 testhal/SPC56ELxx/CAN/.project create mode 100644 testhal/SPC56ELxx/CAN/Makefile create mode 100644 testhal/SPC56ELxx/CAN/chconf.h create mode 100644 testhal/SPC56ELxx/CAN/halconf.h create mode 100644 testhal/SPC56ELxx/CAN/main.c create mode 100644 testhal/SPC56ELxx/CAN/mcuconf.h create mode 100644 testhal/SPC56ELxx/CAN/readme.txt diff --git a/os/hal/platforms/SPC560BCxx/spc560bc_registry.h b/os/hal/platforms/SPC560BCxx/spc560bc_registry.h index cfad96b5f..2d449a5b6 100644 --- a/os/hal/platforms/SPC560BCxx/spc560bc_registry.h +++ b/os/hal/platforms/SPC560BCxx/spc560bc_registry.h @@ -88,6 +88,127 @@ #define SPC5_SIUL_NUM_PCRS 123 #define SPC5_SIUL_NUM_PADSELS 32 #define SPC5_SIUL_SYSTEM_PINS 32,33,121,122 + +/* FlexCAN attributes.*/ +#define SPC5_HAS_FLEXCAN0 TRUE +#define SPC5_FLEXCAN0_PCTL 16 +#define SPC5_FLEXCAN0_MB 64 +#define SPC5_FLEXCAN0_FLEXCAN_ESR_ERR_INT_HANDLER vector65 +#define SPC5_FLEXCAN0_FLEXCAN_ESR_BOFF_HANDLER vector66 +#define SPC5_FLEXCAN0_FLEXCAN_BUF_00_03_HANDLER vector68 +#define SPC5_FLEXCAN0_FLEXCAN_BUF_04_07_HANDLER vector69 +#define SPC5_FLEXCAN0_FLEXCAN_BUF_08_11_HANDLER vector70 +#define SPC5_FLEXCAN0_FLEXCAN_BUF_12_15_HANDLER vector71 +#define SPC5_FLEXCAN0_FLEXCAN_BUF_16_31_HANDLER vector72 +#define SPC5_FLEXCAN0_FLEXCAN_BUF_32_63_HANDLER vector73 +#define SPC5_FLEXCAN0_FLEXCAN_ESR_ERR_INT_NUMBER 65 +#define SPC5_FLEXCAN0_FLEXCAN_ESR_BOFF_NUMBER 66 +#define SPC5_FLEXCAN0_FLEXCAN_BUF_00_03_NUMBER 68 +#define SPC5_FLEXCAN0_FLEXCAN_BUF_04_07_NUMBER 69 +#define SPC5_FLEXCAN0_FLEXCAN_BUF_08_11_NUMBER 70 +#define SPC5_FLEXCAN0_FLEXCAN_BUF_12_15_NUMBER 71 +#define SPC5_FLEXCAN0_FLEXCAN_BUF_16_31_NUMBER 72 +#define SPC5_FLEXCAN0_FLEXCAN_BUF_32_63_NUMBER 73 + +#define SPC5_HAS_FLEXCAN1 TRUE +#define SPC5_FLEXCAN1_PCTL 17 +#define SPC5_FLEXCAN1_MB 64 +#define SPC5_FLEXCAN1_FLEXCAN_ESR_ERR_INT_HANDLER vector85 +#define SPC5_FLEXCAN1_FLEXCAN_ESR_BOFF_HANDLER vector86 +#define SPC5_FLEXCAN1_FLEXCAN_BUF_00_03_HANDLER vector88 +#define SPC5_FLEXCAN1_FLEXCAN_BUF_04_07_HANDLER vector89 +#define SPC5_FLEXCAN1_FLEXCAN_BUF_08_11_HANDLER vector90 +#define SPC5_FLEXCAN1_FLEXCAN_BUF_12_15_HANDLER vector91 +#define SPC5_FLEXCAN1_FLEXCAN_BUF_16_31_HANDLER vector92 +#define SPC5_FLEXCAN1_FLEXCAN_BUF_32_63_HANDLER vector93 +#define SPC5_FLEXCAN1_FLEXCAN_ESR_ERR_INT_NUMBER 85 +#define SPC5_FLEXCAN1_FLEXCAN_ESR_BOFF_NUMBER 86 +#define SPC5_FLEXCAN1_FLEXCAN_BUF_00_03_NUMBER 88 +#define SPC5_FLEXCAN1_FLEXCAN_BUF_04_07_NUMBER 89 +#define SPC5_FLEXCAN1_FLEXCAN_BUF_08_11_NUMBER 90 +#define SPC5_FLEXCAN1_FLEXCAN_BUF_12_15_NUMBER 91 +#define SPC5_FLEXCAN1_FLEXCAN_BUF_16_31_NUMBER 92 +#define SPC5_FLEXCAN1_FLEXCAN_BUF_32_63_NUMBER 93 + +#define SPC5_HAS_FLEXCAN2 TRUE +#define SPC5_FLEXCAN2_PCTL 18 +#define SPC5_FLEXCAN2_MB 64 +#define SPC5_FLEXCAN2_FLEXCAN_ESR_ERR_INT_HANDLER vector105 +#define SPC5_FLEXCAN2_FLEXCAN_ESR_BOFF_HANDLER vector106 +#define SPC5_FLEXCAN2_FLEXCAN_BUF_00_03_HANDLER vector108 +#define SPC5_FLEXCAN2_FLEXCAN_BUF_04_07_HANDLER vector109 +#define SPC5_FLEXCAN2_FLEXCAN_BUF_08_11_HANDLER vector110 +#define SPC5_FLEXCAN2_FLEXCAN_BUF_12_15_HANDLER vector111 +#define SPC5_FLEXCAN2_FLEXCAN_BUF_16_31_HANDLER vector112 +#define SPC5_FLEXCAN2_FLEXCAN_BUF_32_63_HANDLER vector113 +#define SPC5_FLEXCAN2_FLEXCAN_ESR_ERR_INT_NUMBER 105 +#define SPC5_FLEXCAN2_FLEXCAN_ESR_BOFF_NUMBER 106 +#define SPC5_FLEXCAN2_FLEXCAN_BUF_00_03_NUMBER 108 +#define SPC5_FLEXCAN2_FLEXCAN_BUF_04_07_NUMBER 109 +#define SPC5_FLEXCAN2_FLEXCAN_BUF_08_11_NUMBER 110 +#define SPC5_FLEXCAN2_FLEXCAN_BUF_12_15_NUMBER 111 +#define SPC5_FLEXCAN2_FLEXCAN_BUF_16_31_NUMBER 112 +#define SPC5_FLEXCAN2_FLEXCAN_BUF_32_63_NUMBER 113 + +#define SPC5_HAS_FLEXCAN3 TRUE +#define SPC5_FLEXCAN3_PCTL 19 +#define SPC5_FLEXCAN3_MB 64 +#define SPC5_FLEXCAN3_FLEXCAN_ESR_ERR_INT_HANDLER vector173 +#define SPC5_FLEXCAN3_FLEXCAN_ESR_BOFF_HANDLER vector174 +#define SPC5_FLEXCAN3_FLEXCAN_BUF_00_03_HANDLER vector176 +#define SPC5_FLEXCAN3_FLEXCAN_BUF_04_07_HANDLER vector177 +#define SPC5_FLEXCAN3_FLEXCAN_BUF_08_11_HANDLER vector178 +#define SPC5_FLEXCAN3_FLEXCAN_BUF_12_15_HANDLER vector179 +#define SPC5_FLEXCAN3_FLEXCAN_BUF_16_31_HANDLER vector180 +#define SPC5_FLEXCAN3_FLEXCAN_BUF_32_63_HANDLER vector181 +#define SPC5_FLEXCAN3_FLEXCAN_ESR_ERR_INT_NUMBER 173 +#define SPC5_FLEXCAN3_FLEXCAN_ESR_BOFF_NUMBER 174 +#define SPC5_FLEXCAN3_FLEXCAN_BUF_00_03_NUMBER 176 +#define SPC5_FLEXCAN3_FLEXCAN_BUF_04_07_NUMBER 177 +#define SPC5_FLEXCAN3_FLEXCAN_BUF_08_11_NUMBER 178 +#define SPC5_FLEXCAN3_FLEXCAN_BUF_12_15_NUMBER 179 +#define SPC5_FLEXCAN3_FLEXCAN_BUF_16_31_NUMBER 180 +#define SPC5_FLEXCAN3_FLEXCAN_BUF_32_63_NUMBER 181 + +#define SPC5_HAS_FLEXCAN4 TRUE +#define SPC5_FLEXCAN4_PCTL 20 +#define SPC5_FLEXCAN4_MB 64 +#define SPC5_FLEXCAN4_FLEXCAN_ESR_ERR_INT_HANDLER vector190 +#define SPC5_FLEXCAN4_FLEXCAN_ESR_BOFF_HANDLER vector191 +#define SPC5_FLEXCAN4_FLEXCAN_BUF_00_03_HANDLER vector193 +#define SPC5_FLEXCAN4_FLEXCAN_BUF_04_07_HANDLER vector194 +#define SPC5_FLEXCAN4_FLEXCAN_BUF_08_11_HANDLER vector195 +#define SPC5_FLEXCAN4_FLEXCAN_BUF_12_15_HANDLER vector196 +#define SPC5_FLEXCAN4_FLEXCAN_BUF_16_31_HANDLER vector197 +#define SPC5_FLEXCAN4_FLEXCAN_BUF_32_63_HANDLER vector198 +#define SPC5_FLEXCAN4_FLEXCAN_ESR_ERR_INT_NUMBER 190 +#define SPC5_FLEXCAN4_FLEXCAN_ESR_BOFF_NUMBER 191 +#define SPC5_FLEXCAN4_FLEXCAN_BUF_00_03_NUMBER 193 +#define SPC5_FLEXCAN4_FLEXCAN_BUF_04_07_NUMBER 194 +#define SPC5_FLEXCAN4_FLEXCAN_BUF_08_11_NUMBER 195 +#define SPC5_FLEXCAN4_FLEXCAN_BUF_12_15_NUMBER 196 +#define SPC5_FLEXCAN4_FLEXCAN_BUF_16_31_NUMBER 197 +#define SPC5_FLEXCAN4_FLEXCAN_BUF_32_63_NUMBER 198 + +#define SPC5_HAS_FLEXCAN5 TRUE +#define SPC5_FLEXCAN5_PCTL 21 +#define SPC5_FLEXCAN5_MB 64 +#define SPC5_FLEXCAN5_FLEXCAN_ESR_ERR_INT_HANDLER vector202 +#define SPC5_FLEXCAN5_FLEXCAN_ESR_BOFF_HANDLER vector203 +#define SPC5_FLEXCAN5_FLEXCAN_BUF_00_03_HANDLER vector205 +#define SPC5_FLEXCAN5_FLEXCAN_BUF_04_07_HANDLER vector206 +#define SPC5_FLEXCAN5_FLEXCAN_BUF_08_11_HANDLER vector207 +#define SPC5_FLEXCAN5_FLEXCAN_BUF_12_15_HANDLER vector208 +#define SPC5_FLEXCAN5_FLEXCAN_BUF_16_31_HANDLER vector209 +#define SPC5_FLEXCAN5_FLEXCAN_BUF_32_63_HANDLER vector210 +#define SPC5_FLEXCAN5_FLEXCAN_ESR_ERR_INT_NUMBER 202 +#define SPC5_FLEXCAN5_FLEXCAN_ESR_BOFF_NUMBER 203 +#define SPC5_FLEXCAN5_FLEXCAN_BUF_00_03_NUMBER 205 +#define SPC5_FLEXCAN5_FLEXCAN_BUF_04_07_NUMBER 206 +#define SPC5_FLEXCAN5_FLEXCAN_BUF_08_11_NUMBER 207 +#define SPC5_FLEXCAN5_FLEXCAN_BUF_12_15_NUMBER 208 +#define SPC5_FLEXCAN5_FLEXCAN_BUF_16_31_NUMBER 209 +#define SPC5_FLEXCAN5_FLEXCAN_BUF_32_63_NUMBER 210 /** @} */ #endif /* _SPC560BC_REGISTRY_H_ */ diff --git a/os/hal/platforms/SPC560Pxx/spc560p_registry.h b/os/hal/platforms/SPC560Pxx/spc560p_registry.h index 077679ab1..a43b0ef2b 100644 --- a/os/hal/platforms/SPC560Pxx/spc560p_registry.h +++ b/os/hal/platforms/SPC560Pxx/spc560p_registry.h @@ -144,6 +144,27 @@ #define SPC5_ETIMER1_CLK SPC5_MCONTROL_CLK #define SPC5_HAS_ETIMER2 FALSE + +/* FlexCAN attributes.*/ +#define SPC5_HAS_FLEXCAN0 TRUE +#define SPC5_FLEXCAN0_PCTL 16 +#define SPC5_FLEXCAN0_MB 32 +#define SPC5_FLEXCAN0_FLEXCAN_ESR_ERR_INT_HANDLER vector65 +#define SPC5_FLEXCAN0_FLEXCAN_ESR_BOFF_HANDLER vector66 +#define SPC5_FLEXCAN0_FLEXCAN_ESR_WAK_HANDLER vector67 +#define SPC5_FLEXCAN0_FLEXCAN_BUF_00_03_HANDLER vector68 +#define SPC5_FLEXCAN0_FLEXCAN_BUF_04_07_HANDLER vector69 +#define SPC5_FLEXCAN0_FLEXCAN_BUF_08_11_HANDLER vector70 +#define SPC5_FLEXCAN0_FLEXCAN_BUF_12_15_HANDLER vector71 +#define SPC5_FLEXCAN0_FLEXCAN_BUF_16_31_HANDLER vector72 +#define SPC5_FLEXCAN0_FLEXCAN_ESR_ERR_INT_NUMBER 65 +#define SPC5_FLEXCAN0_FLEXCAN_ESR_BOFF_NUMBER 66 +#define SPC5_FLEXCAN0_FLEXCAN_ESR_WAK_NUMBER 67 +#define SPC5_FLEXCAN0_FLEXCAN_BUF_00_03_NUMBER 68 +#define SPC5_FLEXCAN0_FLEXCAN_BUF_04_07_NUMBER 69 +#define SPC5_FLEXCAN0_FLEXCAN_BUF_08_11_NUMBER 70 +#define SPC5_FLEXCAN0_FLEXCAN_BUF_12_15_NUMBER 71 +#define SPC5_FLEXCAN0_FLEXCAN_BUF_16_31_NUMBER 72 /** @} */ #endif /* _SPC560P_REGISTRY_H_ */ diff --git a/os/hal/platforms/SPC56ELxx/spc56el_registry.h b/os/hal/platforms/SPC56ELxx/spc56el_registry.h index 5b7bd34e3..8d5dd45fd 100644 --- a/os/hal/platforms/SPC56ELxx/spc56el_registry.h +++ b/os/hal/platforms/SPC56ELxx/spc56el_registry.h @@ -193,6 +193,47 @@ #define SPC5_ETIMER2_TC5IR_NUMBER 227 #define SPC5_ETIMER2_RCF_NUMBER 232 #define SPC5_ETIMER2_CLK SPC5_MCONTROL_CLK + +/* FlexCAN attributes.*/ +#define SPC5_HAS_FLEXCAN0 TRUE +#define SPC5_FLEXCAN0_PCTL 16 +#define SPC5_FLEXCAN0_MB 32 +#define SPC5_FLEXCAN0_FLEXCAN_ESR_ERR_INT_HANDLER vector65 +#define SPC5_FLEXCAN0_FLEXCAN_ESR_BOFF_HANDLER vector66 +#define SPC5_FLEXCAN0_FLEXCAN_ESR_WAK_HANDLER vector67 +#define SPC5_FLEXCAN0_FLEXCAN_BUF_00_03_HANDLER vector68 +#define SPC5_FLEXCAN0_FLEXCAN_BUF_04_07_HANDLER vector69 +#define SPC5_FLEXCAN0_FLEXCAN_BUF_08_11_HANDLER vector70 +#define SPC5_FLEXCAN0_FLEXCAN_BUF_12_15_HANDLER vector71 +#define SPC5_FLEXCAN0_FLEXCAN_BUF_16_31_HANDLER vector72 +#define SPC5_FLEXCAN0_FLEXCAN_ESR_ERR_INT_NUMBER 65 +#define SPC5_FLEXCAN0_FLEXCAN_ESR_BOFF_NUMBER 66 +#define SPC5_FLEXCAN0_FLEXCAN_ESR_WAK_NUMBER 67 +#define SPC5_FLEXCAN0_FLEXCAN_BUF_00_03_NUMBER 68 +#define SPC5_FLEXCAN0_FLEXCAN_BUF_04_07_NUMBER 69 +#define SPC5_FLEXCAN0_FLEXCAN_BUF_08_11_NUMBER 70 +#define SPC5_FLEXCAN0_FLEXCAN_BUF_12_15_NUMBER 71 +#define SPC5_FLEXCAN0_FLEXCAN_BUF_16_31_NUMBER 72 + +#define SPC5_HAS_FLEXCAN1 TRUE +#define SPC5_FLEXCAN1_PCTL 17 +#define SPC5_FLEXCAN1_MB 32 +#define SPC5_FLEXCAN1_FLEXCAN_ESR_ERR_INT_HANDLER vector85 +#define SPC5_FLEXCAN1_FLEXCAN_ESR_BOFF_HANDLER vector86 +#define SPC5_FLEXCAN1_FLEXCAN_ESR_WAK_HANDLER vector87 +#define SPC5_FLEXCAN1_FLEXCAN_BUF_00_03_HANDLER vector88 +#define SPC5_FLEXCAN1_FLEXCAN_BUF_04_07_HANDLER vector89 +#define SPC5_FLEXCAN1_FLEXCAN_BUF_08_11_HANDLER vector90 +#define SPC5_FLEXCAN1_FLEXCAN_BUF_12_15_HANDLER vector91 +#define SPC5_FLEXCAN1_FLEXCAN_BUF_16_31_HANDLER vector92 +#define SPC5_FLEXCAN1_FLEXCAN_ESR_ERR_INT_NUMBER 85 +#define SPC5_FLEXCAN1_FLEXCAN_ESR_BOFF_NUMBER 86 +#define SPC5_FLEXCAN1_FLEXCAN_ESR_WAK_NUMBER 87 +#define SPC5_FLEXCAN1_FLEXCAN_BUF_00_03_NUMBER 88 +#define SPC5_FLEXCAN1_FLEXCAN_BUF_04_07_NUMBER 89 +#define SPC5_FLEXCAN1_FLEXCAN_BUF_08_11_NUMBER 90 +#define SPC5_FLEXCAN1_FLEXCAN_BUF_12_15_NUMBER 91 +#define SPC5_FLEXCAN1_FLEXCAN_BUF_16_31_NUMBER 92 /** @} */ #endif /* _SPC56EL_REGISTRY_H_ */ diff --git a/os/hal/platforms/SPC5xx/FlexCAN_v1/can_lld.c b/os/hal/platforms/SPC5xx/FlexCAN_v1/can_lld.c new file mode 100644 index 000000000..2d8ceda5c --- /dev/null +++ b/os/hal/platforms/SPC5xx/FlexCAN_v1/can_lld.c @@ -0,0 +1,1618 @@ +/* + SPC5 HAL - Copyright (C) 2013 STMicroelectronics + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file FlexCAN_v1/can_lld.c + * @brief SPC5xx CAN subsystem low level driver source. + * + * @addtogroup CAN + * @{ + */ + +#include "ch.h" +#include "hal.h" + +#if HAL_USE_CAN || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/** @brief CAN1 driver identifier.*/ +#if SPC5_CAN_USE_FLEXCAN0 || defined(__DOXYGEN__) +CANDriver CAND1; +#endif + +/** @brief CAN2 driver identifier.*/ +#if SPC5_CAN_USE_FLEXCAN1 || defined(__DOXYGEN__) +CANDriver CAND2; +#endif + +/** @brief CAN3 driver identifier.*/ +#if SPC5_CAN_USE_FLEXCAN2 || defined(__DOXYGEN__) +CANDriver CAND3; +#endif + +/** @brief CAN4 driver identifier.*/ +#if SPC5_CAN_USE_FLEXCAN3 || defined(__DOXYGEN__) +CANDriver CAND4; +#endif + +/** @brief CAN5 driver identifier.*/ +#if SPC5_CAN_USE_FLEXCAN4 || defined(__DOXYGEN__) +CANDriver CAND5; +#endif + +/** @brief CAN6 driver identifier.*/ +#if SPC5_CAN_USE_FLEXCAN5 || defined(__DOXYGEN__) +CANDriver CAND6; +#endif + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/** + * @brief Common TX ISR handler. + * + * @param[in] canp pointer to the @p CANDriver object + * + * @notapi + */ +static void can_lld_tx_handler(CANDriver *canp) { + uint32_t iflag1; + + iflag1 = canp->flexcan->IFRL.R; + /* No more events until a message is transmitted.*/ + canp->flexcan->IFRL.R |= iflag1 & 0xFFFFFF00; + canp->flexcan->IFRH.R |= canp->flexcan->IFRH.R & 0xFFFFFFFF; + chSysLockFromIsr(); + while (chSemGetCounterI(&canp->txsem) < 0) + chSemSignalI(&canp->txsem); + chEvtBroadcastFlagsI(&canp->txempty_event, iflag1 & 0xFFFFFF00); + chSysUnlockFromIsr(); +} + +/** + * @brief Common RX ISR handler. + * + * @param[in] canp pointer to the @p CANDriver object + * + * @notapi + */ +static void can_lld_rx_handler(CANDriver *canp) { + uint32_t iflag1; + + iflag1 = canp->flexcan->IFRL.R; + if ((iflag1 & 0x000000FF) != 0) { + chSysLockFromIsr(); + while (chSemGetCounterI(&canp->rxsem) < 0) + chSemSignalI(&canp->rxsem); + chEvtBroadcastFlagsI(&canp->rxfull_event, iflag1 & 0x000000FF); + chSysUnlockFromIsr(); + + /* Release the mailbox.*/ + canp->flexcan->IFRL.R |= iflag1 & 0x000000FF; + } +} + +/** + * @brief Common error ISR handler. + * + * @param[in] canp pointer to the @p CANDriver object + * + * @notapi + */ +static void can_lld_err_handler(CANDriver *canp) { + + uint32_t esr = canp->flexcan->ESR.R; + flagsmask_t flags = 0; + + /* Error event.*/ + if ((esr & CAN_ESR_TWRN_INT) || (esr & CAN_ESR_RWRN_INT)) { + canp->flexcan->ESR.B.TXWRN = 1U; + canp->flexcan->ESR.B.RXWRN = 1U; + flags |= CAN_LIMIT_WARNING; + } + + if (esr & CAN_ESR_BOFF_INT) { + canp->flexcan->ESR.B.BOFFINT = 1U; + flags |= CAN_BUS_OFF_ERROR; + } + + if (esr & CAN_ESR_ERR_INT) { + canp->flexcan->ESR.B.ERRINT = 1U; + flags |= CAN_FRAMING_ERROR; + } + chSysLockFromIsr(); + chEvtBroadcastFlagsI(&canp->error_event, flags); + chSysUnlockFromIsr(); +} + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +#if SPC5_CAN_USE_FLEXCAN0 || defined(__DOXYGEN__) +/** + * @brief CAN1 TX interrupt handler for MB 8-11. + * + * @isr + */ +CH_IRQ_HANDLER(SPC5_FLEXCAN0_FLEXCAN_BUF_08_11_HANDLER) { + + + CH_IRQ_PROLOGUE(); + + can_lld_tx_handler(&CAND1); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief CAN1 TX interrupt handler for MB 12-15. + * + * @isr + */ +CH_IRQ_HANDLER(SPC5_FLEXCAN0_FLEXCAN_BUF_12_15_HANDLER) { + + CH_IRQ_PROLOGUE(); + + can_lld_tx_handler(&CAND1); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief CAN1 TX interrupt handler for MB 16-31. + * + * @isr + */ +CH_IRQ_HANDLER(SPC5_FLEXCAN0_FLEXCAN_BUF_16_31_HANDLER) { + + CH_IRQ_PROLOGUE(); + + can_lld_tx_handler(&CAND1); + + CH_IRQ_EPILOGUE(); +} + +#if (SPC5_FLEXCAN0_MB == 64) +/** + * @brief CAN1 TX interrupt handler for MB 32-63. + * + * @isr + */ +CH_IRQ_HANDLER(SPC5_FLEXCAN0_FLEXCAN_BUF_32_63_HANDLER) { + + CH_IRQ_PROLOGUE(); + + can_lld_tx_handler(&CAND1); + + CH_IRQ_EPILOGUE(); +} +#endif + +/* + * @brief CAN1 RX interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(SPC5_FLEXCAN0_FLEXCAN_BUF_00_03_HANDLER) { + + CH_IRQ_PROLOGUE(); + + can_lld_rx_handler(&CAND1); + + CH_IRQ_EPILOGUE(); +} + +/* + * @brief CAN1 RX interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(SPC5_FLEXCAN0_FLEXCAN_BUF_04_07_HANDLER) { + + CH_IRQ_PROLOGUE(); + + can_lld_rx_handler(&CAND1); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief CAN1 ESR_ERR_INT interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(SPC5_FLEXCAN0_FLEXCAN_ESR_ERR_INT_HANDLER) { + + CH_IRQ_PROLOGUE(); + + can_lld_err_handler(&CAND1); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief CAN1 ESR_BOFF interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(SPC5_FLEXCAN0_FLEXCAN_ESR_BOFF_HANDLER) { + + CH_IRQ_PROLOGUE(); + + can_lld_err_handler(&CAND1); + + CH_IRQ_EPILOGUE(); +} +#endif /* SPC5_CAN_USE_FLEXCAN0 */ + +#if SPC5_CAN_USE_FLEXCAN1 || defined(__DOXYGEN__) +/** + * @brief CAN2 TX interrupt handler for MB 8-11. + * + * @isr + */ +CH_IRQ_HANDLER(SPC5_FLEXCAN1_FLEXCAN_BUF_08_11_HANDLER) { + + CH_IRQ_PROLOGUE(); + + can_lld_tx_handler(&CAND2); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief CAN2 TX interrupt handler for MB 12-15. + * + * @isr + */ +CH_IRQ_HANDLER(SPC5_FLEXCAN1_FLEXCAN_BUF_12_15_HANDLER) { + + CH_IRQ_PROLOGUE(); + + can_lld_tx_handler(&CAND2); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief CAN2 TX interrupt handler for MB 16-31. + * + * @isr + */ +CH_IRQ_HANDLER(SPC5_FLEXCAN1_FLEXCAN_BUF_16_31_HANDLER) { + + CH_IRQ_PROLOGUE(); + + can_lld_tx_handler(&CAND2); + + CH_IRQ_EPILOGUE(); +} + +#if (SPC5_FLEXCAN1_MB == 64) +/** + * @brief CAN2 TX interrupt handler for MB 32-63. + * + * @isr + */ +CH_IRQ_HANDLER(SPC5_FLEXCAN1_FLEXCAN_BUF_32_63_HANDLER) { + + CH_IRQ_PROLOGUE(); + + can_lld_tx_handler(&CAND2); + + CH_IRQ_EPILOGUE(); +} +#endif + +/* + * @brief CAN2 RX interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(SPC5_FLEXCAN1_FLEXCAN_BUF_00_03_HANDLER) { + + CH_IRQ_PROLOGUE(); + + can_lld_rx_handler(&CAND2); + + CH_IRQ_EPILOGUE(); +} + +/* + * @brief CAN2 RX interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(SPC5_FLEXCAN1_FLEXCAN_BUF_04_07_HANDLER) { + + CH_IRQ_PROLOGUE(); + + can_lld_rx_handler(&CAND2); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief CAN2 ESR_ERR_INT interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(SPC5_FLEXCAN1_FLEXCAN_ESR_ERR_INT_HANDLER) { + + CH_IRQ_PROLOGUE(); + + can_lld_err_handler(&CAND2); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief CAN2 ESR_BOFF interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(SPC5_FLEXCAN1_FLEXCAN_ESR_BOFF_HANDLER) { + + CH_IRQ_PROLOGUE(); + + can_lld_err_handler(&CAND2); + + CH_IRQ_EPILOGUE(); +} +#endif /* SPC5_CAN_USE_FLEXCAN1 */ + +#if SPC5_CAN_USE_FLEXCAN2 || defined(__DOXYGEN__) +/** + * @brief CAN3 TX interrupt handler for MB 8-11. + * + * @isr + */ +CH_IRQ_HANDLER(SPC5_FLEXCAN2_FLEXCAN_BUF_08_11_HANDLER) { + + CH_IRQ_PROLOGUE(); + + can_lld_tx_handler(&CAND3); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief CAN3 TX interrupt handler for MB 12-15. + * + * @isr + */ +CH_IRQ_HANDLER(SPC5_FLEXCAN2_FLEXCAN_BUF_12_15_HANDLER) { + + CH_IRQ_PROLOGUE(); + + can_lld_tx_handler(&CAND3); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief CAN3 TX interrupt handler for MB 16-31. + * + * @isr + */ +CH_IRQ_HANDLER(SPC5_FLEXCAN2_FLEXCAN_BUF_16_31_HANDLER) { + + CH_IRQ_PROLOGUE(); + + can_lld_tx_handler(&CAND3); + + CH_IRQ_EPILOGUE(); +} + +#if (SPC5_FLEXCAN2_MB == 64) +/** + * @brief CAN3 TX interrupt handler for MB 32-63. + * + * @isr + */ +CH_IRQ_HANDLER(SPC5_FLEXCAN2_FLEXCAN_BUF_32_63_HANDLER) { + + CH_IRQ_PROLOGUE(); + + can_lld_tx_handler(&CAND3); + + CH_IRQ_EPILOGUE(); +} +#endif + +/* + * @brief CAN3 RX interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(SPC5_FLEXCAN2_FLEXCAN_BUF_00_03_HANDLER) { + + CH_IRQ_PROLOGUE(); + + can_lld_rx_handler(&CAND3); + + CH_IRQ_EPILOGUE(); +} + +/* + * @brief CAN3 RX interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(SPC5_FLEXCAN2_FLEXCAN_BUF_04_07_HANDLER) { + + CH_IRQ_PROLOGUE(); + + can_lld_rx_handler(&CAND3); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief CAN3 ESR_ERR_INT interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(SPC5_FLEXCAN2_FLEXCAN_ESR_ERR_INT_HANDLER) { + + CH_IRQ_PROLOGUE(); + + can_lld_err_handler(&CAND3); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief CAN3 ESR_BOFF interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(SPC5_FLEXCAN2_FLEXCAN_ESR_BOFF_HANDLER) { + + CH_IRQ_PROLOGUE(); + + can_lld_err_handler(&CAND3); + + CH_IRQ_EPILOGUE(); +} +#endif /* SPC5_CAN_USE_FLEXCAN2 */ + +#if SPC5_CAN_USE_FLEXCAN3 || defined(__DOXYGEN__) +/** + * @brief CAN4 TX interrupt handler for MB 8-11. + * + * @isr + */ +CH_IRQ_HANDLER(SPC5_FLEXCAN3_FLEXCAN_BUF_08_11_HANDLER) { + + CH_IRQ_PROLOGUE(); + + can_lld_tx_handler(&CAND4); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief CAN4 TX interrupt handler for MB 12-15. + * + * @isr + */ +CH_IRQ_HANDLER(SPC5_FLEXCAN3_FLEXCAN_BUF_12_15_HANDLER) { + + CH_IRQ_PROLOGUE(); + + can_lld_tx_handler(&CAND4); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief CAN4 TX interrupt handler for MB 16-31. + * + * @isr + */ +CH_IRQ_HANDLER(SPC5_FLEXCAN3_FLEXCAN_BUF_16_31_HANDLER) { + + CH_IRQ_PROLOGUE(); + + can_lld_tx_handler(&CAND4); + + CH_IRQ_EPILOGUE(); +} + +#if (SPC5_FLEXCAN3_MB == 64) +/** + * @brief CAN4 TX interrupt handler for MB 32-63. + * + * @isr + */ +CH_IRQ_HANDLER(SPC5_FLEXCAN3_FLEXCAN_BUF_32_63_HANDLER) { + + CH_IRQ_PROLOGUE(); + + can_lld_tx_handler(&CAND4); + + CH_IRQ_EPILOGUE(); +} +#endif + +/* + * @brief CAN4 RX interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(SPC5_FLEXCAN3_FLEXCAN_BUF_00_03_HANDLER) { + + CH_IRQ_PROLOGUE(); + + can_lld_rx_handler(&CAND4); + + CH_IRQ_EPILOGUE(); +} + +/* + * @brief CAN4 RX interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(SPC5_FLEXCAN3_FLEXCAN_BUF_04_07_HANDLER) { + + CH_IRQ_PROLOGUE(); + + can_lld_rx_handler(&CAND4); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief CAN4 ESR_ERR_INT interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(SPC5_FLEXCAN3_FLEXCAN_ESR_ERR_INT_HANDLER) { + + CH_IRQ_PROLOGUE(); + + can_lld_err_handler(&CAND4); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief CAN4 ESR_BOFF interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(SPC5_FLEXCAN3_FLEXCAN_ESR_BOFF_HANDLER) { + + CH_IRQ_PROLOGUE(); + + can_lld_err_handler(&CAND4); + + CH_IRQ_EPILOGUE(); +} +#endif /* SPC5_CAN_USE_FLEXCAN3 */ + +#if SPC5_CAN_USE_FLEXCAN4 || defined(__DOXYGEN__) +/** + * @brief CAN5 TX interrupt handler for MB 8-11. + * + * @isr + */ +CH_IRQ_HANDLER(SPC5_FLEXCAN4_FLEXCAN_BUF_08_11_HANDLER) { + + CH_IRQ_PROLOGUE(); + + can_lld_tx_handler(&CAND5); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief CAN5 TX interrupt handler for MB 12-15. + * + * @isr + */ +CH_IRQ_HANDLER(SPC5_FLEXCAN4_FLEXCAN_BUF_12_15_HANDLER) { + + CH_IRQ_PROLOGUE(); + + can_lld_tx_handler(&CAND5); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief CAN5 TX interrupt handler for MB 16-31. + * + * @isr + */ +CH_IRQ_HANDLER(SPC5_FLEXCAN4_FLEXCAN_BUF_16_31_HANDLER) { + + CH_IRQ_PROLOGUE(); + + can_lld_tx_handler(&CAND5); + + CH_IRQ_EPILOGUE(); +} + +#if (SPC5_FLEXCAN4_MB == 64) +/** + * @brief CAN5 TX interrupt handler for MB 32-63. + * + * @isr + */ +CH_IRQ_HANDLER(SPC5_FLEXCAN4_FLEXCAN_BUF_32_63_HANDLER) { + + CH_IRQ_PROLOGUE(); + + can_lld_tx_handler(&CAND5); + + CH_IRQ_EPILOGUE(); +} +#endif + +/* + * @brief CAN5 RX interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(SPC5_FLEXCAN4_FLEXCAN_BUF_00_03_HANDLER) { + + CH_IRQ_PROLOGUE(); + + can_lld_rx_handler(&CAND5); + + CH_IRQ_EPILOGUE(); +} + +/* + * @brief CAN5 RX interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(SPC5_FLEXCAN4_FLEXCAN_BUF_04_07_HANDLER) { + + CH_IRQ_PROLOGUE(); + + can_lld_rx_handler(&CAND5); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief CAN5 ESR_ERR_INT interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(SPC5_FLEXCAN4_FLEXCAN_ESR_ERR_INT_HANDLER) { + + CH_IRQ_PROLOGUE(); + + can_lld_err_handler(&CAND5); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief CAN5 ESR_BOFF interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(SPC5_FLEXCAN4_FLEXCAN_ESR_BOFF_HANDLER) { + + CH_IRQ_PROLOGUE(); + + can_lld_err_handler(&CAND5); + + CH_IRQ_EPILOGUE(); +} +#endif /* SPC5_CAN_USE_FLEXCAN4 */ + +#if SPC5_CAN_USE_FLEXCAN5 || defined(__DOXYGEN__) +/** + * @brief CAN6 TX interrupt handler for MB 8-11. + * + * @isr + */ +CH_IRQ_HANDLER(SPC5_FLEXCAN5_FLEXCAN_BUF_08_11_HANDLER) { + + CH_IRQ_PROLOGUE(); + + can_lld_tx_handler(&CAND6); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief CAN6 TX interrupt handler for MB 12-15. + * + * @isr + */ +CH_IRQ_HANDLER(SPC5_FLEXCAN5_FLEXCAN_BUF_12_15_HANDLER) { + + CH_IRQ_PROLOGUE(); + + can_lld_tx_handler(&CAND6); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief CAN6 TX interrupt handler for MB 16-31. + * + * @isr + */ +CH_IRQ_HANDLER(SPC5_FLEXCAN5_FLEXCAN_BUF_16_31_HANDLER) { + + CH_IRQ_PROLOGUE(); + + can_lld_tx_handler(&CAND6); + + CH_IRQ_EPILOGUE(); +} + +#if (SPC5_FLEXCAN5_MB == 64) +/** + * @brief CAN6 TX interrupt handler for MB 32-63. + * + * @isr + */ +CH_IRQ_HANDLER(SPC5_FLEXCAN5_FLEXCAN_BUF_32_63_HANDLER) { + + CH_IRQ_PROLOGUE(); + + can_lld_tx_handler(&CAND6); + + CH_IRQ_EPILOGUE(); +} +#endif + +/* + * @brief CAN6 RX interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(SPC5_FLEXCAN5_FLEXCAN_BUF_00_03_HANDLER) { + + CH_IRQ_PROLOGUE(); + + can_lld_rx_handler(&CAND6); + + CH_IRQ_EPILOGUE(); +} + +/* + * @brief CAN6 RX interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(SPC5_FLEXCAN5_FLEXCAN_BUF_04_07_HANDLER) { + + CH_IRQ_PROLOGUE(); + + can_lld_rx_handler(&CAND6); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief CAN6 ESR_ERR_INT interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(SPC5_FLEXCAN5_FLEXCAN_ESR_ERR_INT_HANDLER) { + + CH_IRQ_PROLOGUE(); + + can_lld_err_handler(&CAND6); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief CAN6 ESR_BOFF interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(SPC5_FLEXCAN5_FLEXCAN_ESR_BOFF_HANDLER) { + + CH_IRQ_PROLOGUE(); + + can_lld_err_handler(&CAND6); + + CH_IRQ_EPILOGUE(); +} +#endif /* SPC5_CAN_USE_FLEXCAN5 */ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level CAN driver initialization. + * + * @notapi + */ +void can_lld_init(void) { + +#if SPC5_CAN_USE_FLEXCAN0 + /* Driver initialization.*/ + canObjectInit(&CAND1); + CAND1.flexcan = &SPC5_FLEXCAN_0; + INTC.PSR[SPC5_FLEXCAN0_FLEXCAN_ESR_ERR_INT_NUMBER].R = + SPC5_CAN_FLEXCAN0_IRQ_PRIORITY; + INTC.PSR[SPC5_FLEXCAN0_FLEXCAN_ESR_BOFF_NUMBER].R = + SPC5_CAN_FLEXCAN0_IRQ_PRIORITY; + INTC.PSR[SPC5_FLEXCAN0_FLEXCAN_BUF_00_03_NUMBER].R = + SPC5_CAN_FLEXCAN0_IRQ_PRIORITY; + INTC.PSR[SPC5_FLEXCAN0_FLEXCAN_BUF_04_07_NUMBER].R = + SPC5_CAN_FLEXCAN0_IRQ_PRIORITY; + INTC.PSR[SPC5_FLEXCAN0_FLEXCAN_BUF_08_11_NUMBER].R = + SPC5_CAN_FLEXCAN0_IRQ_PRIORITY; + INTC.PSR[SPC5_FLEXCAN0_FLEXCAN_BUF_12_15_NUMBER].R = + SPC5_CAN_FLEXCAN0_IRQ_PRIORITY; + INTC.PSR[SPC5_FLEXCAN0_FLEXCAN_BUF_16_31_NUMBER].R = + SPC5_CAN_FLEXCAN0_IRQ_PRIORITY; +#endif + +#if SPC5_CAN_USE_FLEXCAN1 + /* Driver initialization.*/ + canObjectInit(&CAND2); + CAND2.flexcan = &SPC5_FLEXCAN_1; + INTC.PSR[SPC5_FLEXCAN1_FLEXCAN_ESR_ERR_INT_NUMBER].R = + SPC5_CAN_FLEXCAN1_IRQ_PRIORITY; + INTC.PSR[SPC5_FLEXCAN1_FLEXCAN_ESR_BOFF_NUMBER].R = + SPC5_CAN_FLEXCAN1_IRQ_PRIORITY; + INTC.PSR[SPC5_FLEXCAN1_FLEXCAN_BUF_00_03_NUMBER].R = + SPC5_CAN_FLEXCAN1_IRQ_PRIORITY; + INTC.PSR[SPC5_FLEXCAN1_FLEXCAN_BUF_04_07_NUMBER].R = + SPC5_CAN_FLEXCAN1_IRQ_PRIORITY; + INTC.PSR[SPC5_FLEXCAN1_FLEXCAN_BUF_08_11_NUMBER].R = + SPC5_CAN_FLEXCAN1_IRQ_PRIORITY; + INTC.PSR[SPC5_FLEXCAN1_FLEXCAN_BUF_12_15_NUMBER].R = + SPC5_CAN_FLEXCAN1_IRQ_PRIORITY; + INTC.PSR[SPC5_FLEXCAN1_FLEXCAN_BUF_16_31_NUMBER].R = + SPC5_CAN_FLEXCAN1_IRQ_PRIORITY; +#endif + +#if SPC5_CAN_USE_FLEXCAN2 + /* Driver initialization.*/ + canObjectInit(&CAND3); + CAND3.flexcan = &SPC5_FLEXCAN_2; + INTC.PSR[SPC5_FLEXCAN2_FLEXCAN_ESR_ERR_INT_NUMBER].R = + SPC5_CAN_FLEXCAN2_IRQ_PRIORITY; + INTC.PSR[SPC5_FLEXCAN2_FLEXCAN_ESR_BOFF_NUMBER].R = + SPC5_CAN_FLEXCAN2_IRQ_PRIORITY; + INTC.PSR[SPC5_FLEXCAN2_FLEXCAN_BUF_00_03_NUMBER].R = + SPC5_CAN_FLEXCAN2_IRQ_PRIORITY; + INTC.PSR[SPC5_FLEXCAN2_FLEXCAN_BUF_04_07_NUMBER].R = + SPC5_CAN_FLEXCAN2_IRQ_PRIORITY; + INTC.PSR[SPC5_FLEXCAN2_FLEXCAN_BUF_08_11_NUMBER].R = + SPC5_CAN_FLEXCAN2_IRQ_PRIORITY; + INTC.PSR[SPC5_FLEXCAN2_FLEXCAN_BUF_12_15_NUMBER].R = + SPC5_CAN_FLEXCAN2_IRQ_PRIORITY; + INTC.PSR[SPC5_FLEXCAN2_FLEXCAN_BUF_16_31_NUMBER].R = + SPC5_CAN_FLEXCAN2_IRQ_PRIORITY; +#endif + +#if SPC5_CAN_USE_FLEXCAN3 + /* Driver initialization.*/ + canObjectInit(&CAND4); + CAND4.flexcan = &SPC5_FLEXCAN_3; + INTC.PSR[SPC5_FLEXCAN3_FLEXCAN_ESR_ERR_INT_NUMBER].R = + SPC5_CAN_FLEXCAN3_IRQ_PRIORITY; + INTC.PSR[SPC5_FLEXCAN3_FLEXCAN_ESR_BOFF_NUMBER].R = + SPC5_CAN_FLEXCAN3_IRQ_PRIORITY; + INTC.PSR[SPC5_FLEXCAN3_FLEXCAN_ESR_WAK_NUMBER].R = + SPC5_CAN_FLEXCAN3_IRQ_PRIORITY; + INTC.PSR[SPC5_FLEXCAN3_FLEXCAN_BUF_00_03_NUMBER].R = + SPC5_CAN_FLEXCAN3_IRQ_PRIORITY; + INTC.PSR[SPC5_FLEXCAN3_FLEXCAN_BUF_04_07_NUMBER].R = + SPC5_CAN_FLEXCAN3_IRQ_PRIORITY; + INTC.PSR[SPC5_FLEXCAN3_FLEXCAN_BUF_08_11_NUMBER].R = + SPC5_CAN_FLEXCAN3_IRQ_PRIORITY; + INTC.PSR[SPC5_FLEXCAN3_FLEXCAN_BUF_12_15_NUMBER].R = + SPC5_CAN_FLEXCAN3_IRQ_PRIORITY; + INTC.PSR[SPC5_FLEXCAN3_FLEXCAN_BUF_16_31_NUMBER].R = + SPC5_CAN_FLEXCAN3_IRQ_PRIORITY; +#endif + +#if SPC5_CAN_USE_FLEXCAN4 + /* Driver initialization.*/ + canObjectInit(&CAND5); + CAND5.flexcan = &SPC5_FLEXCAN_4; + INTC.PSR[SPC5_FLEXCAN4_FLEXCAN_ESR_ERR_INT_NUMBER].R = + SPC5_CAN_FLEXCAN4_IRQ_PRIORITY; + INTC.PSR[SPC5_FLEXCAN4_FLEXCAN_ESR_BOFF_NUMBER].R = + SPC5_CAN_FLEXCAN4_IRQ_PRIORITY; + INTC.PSR[SPC5_FLEXCAN4_FLEXCAN_BUF_00_03_NUMBER].R = + SPC5_CAN_FLEXCAN4_IRQ_PRIORITY; + INTC.PSR[SPC5_FLEXCAN4_FLEXCAN_BUF_04_07_NUMBER].R = + SPC5_CAN_FLEXCAN4_IRQ_PRIORITY; + INTC.PSR[SPC5_FLEXCAN4_FLEXCAN_BUF_08_11_NUMBER].R = + SPC5_CAN_FLEXCAN4_IRQ_PRIORITY; + INTC.PSR[SPC5_FLEXCAN4_FLEXCAN_BUF_12_15_NUMBER].R = + SPC5_CAN_FLEXCAN4_IRQ_PRIORITY; + INTC.PSR[SPC5_FLEXCAN4_FLEXCAN_BUF_16_31_NUMBER].R = + SPC5_CAN_FLEXCAN4_IRQ_PRIORITY; +#endif + +#if SPC5_CAN_USE_FLEXCAN5 + /* Driver initialization.*/ + canObjectInit(&CAND6); + CAND6.flexcan = &SPC5_FLEXCAN_5; + INTC.PSR[SPC5_FLEXCAN5_FLEXCAN_ESR_ERR_INT_NUMBER].R = + SPC5_CAN_FLEXCAN5_IRQ_PRIORITY; + INTC.PSR[SPC5_FLEXCAN5_FLEXCAN_ESR_BOFF_NUMBER].R = + SPC5_CAN_FLEXCAN5_IRQ_PRIORITY; + INTC.PSR[SPC5_FLEXCAN5_FLEXCAN_BUF_00_03_NUMBER].R = + SPC5_CAN_FLEXCAN5_IRQ_PRIORITY; + INTC.PSR[SPC5_FLEXCAN5_FLEXCAN_BUF_04_07_NUMBER].R = + SPC5_CAN_FLEXCAN5_IRQ_PRIORITY; + INTC.PSR[SPC5_FLEXCAN5_FLEXCAN_BUF_08_11_NUMBER].R = + SPC5_CAN_FLEXCAN5_IRQ_PRIORITY; + INTC.PSR[SPC5_FLEXCAN5_FLEXCAN_BUF_12_15_NUMBER].R = + SPC5_CAN_FLEXCAN5_IRQ_PRIORITY; + INTC.PSR[SPC5_FLEXCAN5_FLEXCAN_BUF_16_31_NUMBER].R = + SPC5_CAN_FLEXCAN5_IRQ_PRIORITY; +#endif +} + +/** + * @brief Configures and activates the CAN peripheral. + * + * @param[in] canp pointer to the @p CANDriver object + * + * @notapi + */ +void can_lld_start(CANDriver *canp) { + + uint8_t mb_index = 0, id = 0; + + /* Clock activation.*/ +#if SPC5_CAN_USE_FLEXCAN0 + /* Set peripheral clock mode.*/ + if(&CAND1 == canp) + halSPCSetPeripheralClockMode(SPC5_FLEXCAN0_PCTL, + SPC5_CAN_FLEXCAN0_START_PCTL); +#endif + +#if SPC5_CAN_USE_FLEXCAN1 + /* Set peripheral clock mode.*/ + if(&CAND2 == canp) + halSPCSetPeripheralClockMode(SPC5_FLEXCAN1_PCTL, + SPC5_CAN_FLEXCAN1_START_PCTL); +#endif + +#if SPC5_CAN_USE_FLEXCAN2 + /* Set peripheral clock mode.*/ + if(&CAND3 == canp) + halSPCSetPeripheralClockMode(SPC5_FLEXCAN2_PCTL, + SPC5_CAN_FLEXCAN2_START_PCTL); +#endif + +#if SPC5_CAN_USE_FLEXCAN3 + /* Set peripheral clock mode.*/ + if(&CAND4 == canp) + halSPCSetPeripheralClockMode(SPC5_FLEXCAN3_PCTL, + SPC5_CAN_FLEXCAN3_START_PCTL); +#endif + +#if SPC5_CAN_USE_FLEXCAN4 + /* Set peripheral clock mode.*/ + if(&CAND5 == canp) + halSPCSetPeripheralClockMode(SPC5_FLEXCAN4_PCTL, + SPC5_CAN_FLEXCAN4_START_PCTL); +#endif + +#if SPC5_CAN_USE_FLEXCAN5 + /* Set peripheral clock mode.*/ + if(&CAND6 == canp) + halSPCSetPeripheralClockMode(SPC5_FLEXCAN5_PCTL, + SPC5_CAN_FLEXCAN5_START_PCTL); +#endif + + /* Entering initialization mode. */ + canp->state = CAN_STARTING; + canp->flexcan->CR.R |= CAN_CTRL_CLK_SRC; + canp->flexcan->MCR.R &= ~CAN_MCR_MDIS; + + /* + * Individual filtering per MB, disable frame self reception, + * disable the FIFO, enable SuperVisor mode. + */ +#if SPC5_CAN_USE_FLEXCAN0 + if(&CAND1 == canp) + canp->flexcan->MCR.R |= CAN_MCR_SUPV | CAN_MCR_MAXMB(SPC5_FLEXCAN0_MB - 1); +#endif + +#if SPC5_CAN_USE_FLEXCAN1 + if(&CAND2 == canp) + canp->flexcan->MCR.R |= CAN_MCR_SUPV | CAN_MCR_MAXMB(SPC5_FLEXCAN1_MB - 1); +#endif + +#if SPC5_CAN_USE_FLEXCAN2 + if(&CAND3 == canp) + canp->flexcan->MCR.R |= CAN_MCR_SUPV | CAN_MCR_MAXMB(SPC5_FLEXCAN2_MB - 1); +#endif + +#if SPC5_CAN_USE_FLEXCAN3 + if(&CAND4 == canp) + canp->flexcan->MCR.R |= CAN_MCR_SUPV | CAN_MCR_MAXMB(SPC5_FLEXCAN3_MB - 1); +#endif + +#if SPC5_CAN_USE_FLEXCAN4 + if(&CAND5 == canp) + canp->flexcan->MCR.R |= CAN_MCR_SUPV | CAN_MCR_MAXMB(SPC5_FLEXCAN4_MB - 1); +#endif + +#if SPC5_CAN_USE_FLEXCAN5 + if(&CAND6 == canp) + canp->flexcan->MCR.R |= CAN_MCR_SUPV | CAN_MCR_MAXMB(SPC5_FLEXCAN5_MB - 1); +#endif + + canp->flexcan->CR.R |= CAN_CTRL_TSYN | CAN_CTRL_RJW(3); + + /* TX MB initialization.*/ +#if SPC5_CAN_USE_FLEXCAN0 + if(&CAND1 == canp) { + for(mb_index = 0; mb_index < (SPC5_FLEXCAN0_MB - CAN_RX_MAILBOXES); + mb_index++) { + canp->flexcan->BUF[mb_index + CAN_RX_MAILBOXES].CS.B.CODE = 8U; + } + } +#endif +#if SPC5_CAN_USE_FLEXCAN1 + if(&CAND2 == canp) { + for(mb_index = 0; mb_index < (SPC5_FLEXCAN1_MB - CAN_RX_MAILBOXES); + mb_index++) { + canp->flexcan->BUF[mb_index + CAN_RX_MAILBOXES].CS.B.CODE = 8U; + } + } +#endif +#if SPC5_CAN_USE_FLEXCAN2 + if(&CAND3 == canp) { + for(mb_index = 0; mb_index < (SPC5_FLEXCAN2_MB - CAN_RX_MAILBOXES); + mb_index++) { + canp->flexcan->BUF[mb_index + CAN_RX_MAILBOXES].CS.B.CODE = 8U; + } + } +#endif +#if SPC5_CAN_USE_FLEXCAN3 + if(&CAND4 == canp) { + for(mb_index = 0; mb_index < (SPC5_FLEXCAN3_MB - CAN_RX_MAILBOXES); + mb_index++) { + canp->flexcan->BUF[mb_index + CAN_RX_MAILBOXES].CS.B.CODE = 8U; + } + } +#endif +#if SPC5_CAN_USE_FLEXCAN4 + if(&CAND5 == canp) { + for(mb_index = 0; mb_index < (SPC5_FLEXCAN4_MB - CAN_RX_MAILBOXES); + mb_index++) { + canp->flexcan->BUF[mb_index + CAN_RX_MAILBOXES].CS.B.CODE = 8U; + } + } +#endif +#if SPC5_CAN_USE_FLEXCAN5 + if(&CAND6 == canp) { + for(mb_index = 0; mb_index < (SPC5_FLEXCAN5_MB - CAN_RX_MAILBOXES); + mb_index++) { + canp->flexcan->BUF[mb_index + CAN_RX_MAILBOXES].CS.B.CODE = 8U; + } + } +#endif + + /* Unlock Message buffers.*/ + (void) canp->flexcan->TIMER.R; + + /* MCR initialization.*/ + canp->flexcan->MCR.R |= canp->config->mcr; + + /* CTRL initialization.*/ + canp->flexcan->CR.R |= canp->config->ctrl; + + /* Interrupt sources initialization.*/ + canp->flexcan->MCR.R |= CAN_MCR_WRN_EN; + + canp->flexcan->CR.R |= CAN_CTRL_BOFF_MSK | CAN_CTRL_ERR_MSK | + CAN_CTRL_TWRN_MSK | CAN_CTRL_RWRN_MSK; + +#if !SPC5_CAN_USE_FILTERS + /* RX MB initialization.*/ + for(mb_index = 0; mb_index < CAN_RX_MAILBOXES; mb_index++) { + canp->flexcan->BUF[mb_index].CS.B.CODE = 0U; + canp->flexcan->BUF[mb_index].ID.R = 0U; + canp->flexcan->BUF[mb_index].CS.B.CODE = 4U; + } + + /* Receive all.*/ + canp->flexcan->RXGMASK.R = 0x00000000; +#else + for (id = 0; id < CAN_RX_MAILBOXES; id++) { + canp->flexcan->BUF[id].CS.B.CODE = 0U; + if (canp->config->RxFilter[id].scale) { + canp->flexcan->BUF[id].CS.B.IDE = 1U; + canp->flexcan->BUF[id].ID.R = canp->config->RxFilter[id].register1; + } + else { + canp->flexcan->BUF[id].CS.B.IDE = 0U; + canp->flexcan->BUF[id].ID.B.STD_ID = canp->config->RxFilter[id].register1; + canp->flexcan->BUF[id].ID.B.EXT_ID = 0U; + } + /* RX MB initialization.*/ + canp->flexcan->BUF[id].CS.B.CODE = 4U; + } + canp->flexcan->RXGMASK.R = 0x0FFFFFFF; +#endif + + /* Enable MBs interrupts.*/ +#if SPC5_CAN_USE_FLEXCAN0 + if(&CAND1 == canp) { + if(SPC5_FLEXCAN0_MB == 32) { + canp->flexcan->IMRL.R = 0xFFFFFFFF; + } + else if(SPC5_FLEXCAN0_MB == 64) { + canp->flexcan->IMRL.R = 0xFFFFFFFF; + canp->flexcan->IMRH.R = 0xFFFFFFFF; + } + } +#endif +#if SPC5_CAN_USE_FLEXCAN1 + if(&CAND2 == canp) { + if(SPC5_FLEXCAN1_MB == 32) { + canp->flexcan->IMRL.R = 0xFFFFFFFF; + } + else if(SPC5_FLEXCAN1_MB == 64) { + canp->flexcan->IMRL.R = 0xFFFFFFFF; + canp->flexcan->IMRH.R = 0xFFFFFFFF; + } + } +#endif +#if SPC5_CAN_USE_FLEXCAN2 + if(&CAND3 == canp) { + if(SPC5_FLEXCAN2_MB == 32) { + canp->flexcan->IMRL.R = 0xFFFFFFFF; + } + else if(SPC5_FLEXCAN2_MB == 64) { + canp->flexcan->IMRL.R = 0xFFFFFFFF; + canp->flexcan->IMRH.R = 0xFFFFFFFF; + } + } +#endif +#if SPC5_CAN_USE_FLEXCAN3 + if(&CAND4 == canp) { + if(SPC5_FLEXCAN3_MB == 32) { + canp->flexcan->IMRL.R = 0xFFFFFFFF; + } + else if(SPC5_FLEXCAN3_MB == 64) { + canp->flexcan->IMRL.R = 0xFFFFFFFF; + canp->flexcan->IMRH.R = 0xFFFFFFFF; + } + } +#endif +#if SPC5_CAN_USE_FLEXCAN4 + if(&CAND5 == canp) { + if(SPC5_FLEXCAN4_MB == 32) { + canp->flexcan->IMRL.R = 0xFFFFFFFF; + } + else if(SPC5_FLEXCAN4_MB == 64) { + canp->flexcan->IMRL.R = 0xFFFFFFFF; + canp->flexcan->IMRH.R = 0xFFFFFFFF; + } + } +#endif +#if SPC5_CAN_USE_FLEXCAN5 + if(&CAND6 == canp) { + if(SPC5_FLEXCAN5_MB == 32) { + canp->flexcan->IMRL.R = 0xFFFFFFFF; + } + else if(SPC5_FLEXCAN5_MB == 64) { + canp->flexcan->IMRL.R = 0xFFFFFFFF; + canp->flexcan->IMRH.R = 0xFFFFFFFF; + } + } +#endif + + /* CAN BUS synchronization.*/ + canp->flexcan->MCR.B.HALT = 0; +} + +/** + * @brief Deactivates the CAN peripheral. + * + * @param[in] canp pointer to the @p CANDriver object + * + * @notapi + */ +void can_lld_stop(CANDriver *canp) { + + /* If in ready state then disables the CAN peripheral.*/ + if (canp->state == CAN_READY) { + + /* Disable Interrupt sources.*/ + canp->flexcan->MCR.R &= ~CAN_MCR_WRN_EN; + canp->flexcan->CR.R &= ~(CAN_CTRL_BOFF_MSK | CAN_CTRL_ERR_MSK | + CAN_CTRL_TWRN_MSK | CAN_CTRL_RWRN_MSK); + canp->flexcan->IMRL.R = 0x00000000; + + canp->flexcan->MCR.R &= ~CAN_MCR_MDIS; + +#if SPC5_CAN_USE_FLEXCAN0 + /* Set peripheral clock mode.*/ + if(&CAND1 == canp) + halSPCSetPeripheralClockMode(SPC5_FLEXCAN0_PCTL, + SPC5_CAN_FLEXCAN0_STOP_PCTL); +#endif +#if SPC5_CAN_USE_FLEXCAN1 + /* Set peripheral clock mode.*/ + if(&CAND2 == canp) + halSPCSetPeripheralClockMode(SPC5_FLEXCAN1_PCTL, + SPC5_CAN_FLEXCAN1_STOP_PCTL); +#endif +#if SPC5_CAN_USE_FLEXCAN2 + /* Set peripheral clock mode.*/ + if(&CAND3 == canp) + halSPCSetPeripheralClockMode(SPC5_FLEXCAN2_PCTL, + SPC5_CAN_FLEXCAN2_STOP_PCTL); +#endif +#if SPC5_CAN_USE_FLEXCAN3 + /* Set peripheral clock mode.*/ + if(&CAND4 == canp) + halSPCSetPeripheralClockMode(SPC5_FLEXCAN3_PCTL, + SPC5_CAN_FLEXCAN3_STOP_PCTL); +#endif +#if SPC5_CAN_USE_FLEXCAN4 + /* Set peripheral clock mode.*/ + if(&CAND5 == canp) + halSPCSetPeripheralClockMode(SPC5_FLEXCAN4_PCTL, + SPC5_CAN_FLEXCAN4_STOP_PCTL); +#endif +#if SPC5_CAN_USE_FLEXCAN5 + /* Set peripheral clock mode.*/ + if(&CAND6 == canp) + halSPCSetPeripheralClockMode(SPC5_FLEXCAN5_PCTL, + SPC5_CAN_FLEXCAN5_STOP_PCTL); +#endif + } +} + +/** + * @brief Determines whether a frame can be transmitted. + * + * @param[in] canp pointer to the @p CANDriver object + * @param[in] mailbox mailbox number, @p CAN_ANY_MAILBOX for any mailbox + * + * @return The queue space availability. + * @retval FALSE no space in the transmit queue. + * @retval TRUE transmit slot available. + * + * @notapi + */ +bool_t can_lld_is_tx_empty(CANDriver *canp, canmbx_t mailbox) { + + uint8_t mbid = 0; + + if(mailbox == CAN_ANY_MAILBOX) { +#if SPC5_CAN_USE_FLEXCAN0 + if(&CAND1 == canp) { + for (mbid = 8; mbid < SPC5_FLEXCAN0_MB; mbid++) { + if (canp->flexcan->BUF[mbid].CS.B.CODE == 0x08) { + return TRUE; + } + } + return FALSE; + } +#endif +#if SPC5_CAN_USE_FLEXCAN1 + if(&CAND2 == canp) { + for (mbid = 8; mbid < SPC5_FLEXCAN1_MB; mbid++) { + if (canp->flexcan->BUF[mbid].CS.B.CODE == 0x08) { + return TRUE; + } + } + return FALSE; + } +#endif +#if SPC5_CAN_USE_FLEXCAN2 + if(&CAND3 == canp) { + for (mbid = 8; mbid < SPC5_FLEXCAN2_MB; mbid++) { + if (canp->flexcan->BUF[mbid].CS.B.CODE == 0x08) { + return TRUE; + } + } + return FALSE; + } +#endif +#if SPC5_CAN_USE_FLEXCAN3 + if(&CAND4 == canp) { + for (mbid = 8; mbid < SPC5_FLEXCAN3_MB; mbid++) { + if (canp->flexcan->BUF[mbid].CS.B.CODE == 0x08) { + return TRUE; + } + } + return FALSE; + } +#endif +#if SPC5_CAN_USE_FLEXCAN4 + if(&CAND5 == canp) { + for (mbid = 8; mbid < SPC5_FLEXCAN4_MB; mbid++) { + if (canp->flexcan->BUF[mbid].CS.B.CODE == 0x08) { + return TRUE; + } + } + return FALSE; + } +#endif +#if SPC5_CAN_USE_FLEXCAN5 + if(&CAND6 == canp) { + for (mbid = 8; mbid < SPC5_FLEXCAN5_MB; mbid++) { + if (canp->flexcan->BUF[mbid].CS.B.CODE == 0x08) { + return TRUE; + } + } + return FALSE; + } +#endif + } + else { + return canp->flexcan->BUF[mailbox + 7].CS.B.CODE == 0x08; + } + return FALSE; +} + +/** + * @brief Inserts a frame into the transmit queue. + * + * @param[in] canp pointer to the @p CANDriver object + * @param[in] ctfp pointer to the CAN frame to be transmitted + * @param[in] mailbox mailbox number, @p CAN_ANY_MAILBOX for any mailbox + * + * @notapi + */ +void can_lld_transmit(CANDriver *canp, + canmbx_t mailbox, + const CANTxFrame *ctfp) { + + CAN_TxMailBox_TypeDef *tmbp = NULL; + uint8_t mbid = 0; + + /* Pointer to a free transmission mailbox.*/ + if (mailbox == CAN_ANY_MAILBOX) { +#if SPC5_CAN_USE_FLEXCAN0 + if(&CAND1 == canp) { + for (mbid = 8; mbid < SPC5_FLEXCAN0_MB; mbid++) { + if ((canp->flexcan->BUF[mbid].CS.B.CODE & 8U) == 1) { + tmbp = (CAN_TxMailBox_TypeDef *)&canp->flexcan->BUF[mbid]; + break; + } + } + } +#endif +#if SPC5_CAN_USE_FLEXCAN1 + if(&CAND2 == canp) { + for (mbid = 8; mbid < SPC5_FLEXCAN1_MB; mbid++) { + if ((canp->flexcan->BUF[mbid].CS.B.CODE & 8U) == 1) { + tmbp = (CAN_TxMailBox_TypeDef *)&canp->flexcan->BUF[mbid]; + break; + } + } + } +#endif +#if SPC5_CAN_USE_FLEXCAN2 + if(&CAND3 == canp) { + for (mbid = 8; mbid < SPC5_FLEXCAN2_MB; mbid++) { + if ((canp->flexcan->BUF[mbid].CS.B.CODE & 8U) == 1) { + tmbp = (CAN_TxMailBox_TypeDef *)&canp->flexcan->BUF[mbid]; + break; + } + } + } +#endif +#if SPC5_CAN_USE_FLEXCAN3 + if(&CAND4 == canp) { + for (mbid = 8; mbid < SPC5_FLEXCAN3_MB; mbid++) { + if ((canp->flexcan->BUF[mbid].CS.B.CODE & 8U) == 1) { + tmbp = (CAN_TxMailBox_TypeDef *)&canp->flexcan->BUF[mbid]; + break; + } + } + } +#endif +#if SPC5_CAN_USE_FLEXCAN4 + if(&CAND5 == canp) { + for (mbid = 8; mbid < SPC5_FLEXCAN4_MB; mbid++) { + if ((canp->flexcan->BUF[mbid].CS.B.CODE & 8U) == 1) { + tmbp = (CAN_TxMailBox_TypeDef *)&canp->flexcan->BUF[mbid]; + break; + } + } + } +#endif +#if SPC5_CAN_USE_FLEXCAN5 + if(&CAND6 == canp) { + for (mbid = 8; mbid < SPC5_FLEXCAN5_MB; mbid++) { + if ((canp->flexcan->BUF[mbid].CS.B.CODE & 8U) == 1) { + tmbp = (CAN_TxMailBox_TypeDef *)&canp->flexcan->BUF[mbid]; + break; + } + } + } +#endif + } + else { + tmbp = (CAN_TxMailBox_TypeDef *)&canp->flexcan->BUF[mailbox + 7]; + } + + /* Preparing the message.*/ + if (ctfp->IDE) { + tmbp->CS.B.IDE = 1U; + tmbp->CS.B.RTR = 0U; + tmbp->ID.R = ctfp->EID; + } + else { + tmbp->CS.B.IDE = 0U; + tmbp->CS.B.RTR = 0U; + tmbp->ID.R = ctfp->SID << 18; + } + tmbp->CS.B.LENGTH = ctfp->LENGTH; + tmbp->DATA[0] = ctfp->data32[0]; + tmbp->DATA[1] = ctfp->data32[1]; + tmbp->CS.B.CODE = 0x0C; +} + +/** + * + * @brief Determines whether a frame has been received. + * + * @param[in] canp pointer to the @p CANDriver object + * @param[in] mailbox mailbox number, @p CAN_ANY_MAILBOX for any mailbox + * + * @return The queue space availability. + * @retval FALSE no space in the transmit queue. + * @retval TRUE transmit slot available. + * + * @notapi + */ + +bool_t can_lld_is_rx_nonempty(CANDriver *canp, canmbx_t mailbox) { + + uint8_t mbid = 0; + bool_t mb_status = FALSE; + + switch (mailbox) { + case CAN_ANY_MAILBOX: + for (mbid = 0; mbid < CAN_RX_MAILBOXES; mbid++) { + if(canp->flexcan->BUF[mbid].CS.B.CODE == 2U) { + mb_status = TRUE; + } + } + return mb_status; + case 1: + return (canp->flexcan->BUF[0].CS.B.CODE == 2U); + case 2: + return (canp->flexcan->BUF[1].CS.B.CODE == 2U); + case 3: + return (canp->flexcan->BUF[2].CS.B.CODE == 2U); + case 4: + return (canp->flexcan->BUF[3].CS.B.CODE == 2U); + case 5: + return (canp->flexcan->BUF[4].CS.B.CODE == 2U); + case 6: + return (canp->flexcan->BUF[5].CS.B.CODE == 2U); + case 7: + return (canp->flexcan->BUF[6].CS.B.CODE == 2U); + case 8: + return (canp->flexcan->BUF[7].CS.B.CODE == 2U); + default: + return FALSE; + } +} + +/** + * @brief Receives a frame from the input queue. + * + * @param[in] canp pointer to the @p CANDriver object + * @param[in] mailbox mailbox number, @p CAN_ANY_MAILBOX for any mailbox + * @param[out] crfp pointer to the buffer where the CAN frame is copied + * + * @notapi + */ +void can_lld_receive(CANDriver *canp, + canmbx_t mailbox, + CANRxFrame *crfp) { + + uint32_t mbid = 0, index = 0; + + if(mailbox != CAN_ANY_MAILBOX) { + mbid = mailbox; + } + else { + for (index = 0; index < CAN_RX_MAILBOXES; index++) { + if(canp->flexcan->BUF[index].CS.B.CODE == 2U) { + mbid = index; + break; + } + } + } + + /* Lock the RX MB.*/ + (void) canp->flexcan->BUF[mbid].CS.B.CODE; + + /* Fetches the message.*/ + crfp->data32[0] = canp->flexcan->BUF[mbid].DATA.W[0]; + crfp->data32[1] = canp->flexcan->BUF[mbid].DATA.W[1]; + + /* Decodes the various fields in the RX frame.*/ + crfp->RTR = canp->flexcan->BUF[mbid].CS.B.RTR; + crfp->IDE = canp->flexcan->BUF[mbid].CS.B.IDE; + if (crfp->IDE) + crfp->EID = canp->flexcan->BUF[mbid].ID.B.EXT_ID; + else + crfp->SID = canp->flexcan->BUF[mbid].ID.B.STD_ID; + crfp->LENGTH = canp->flexcan->BUF[mbid].CS.B.LENGTH; + crfp->TIME = canp->flexcan->BUF[mbid].CS.B.TIMESTAMP; + + /* Unlock the RX MB.*/ + (void) canp->flexcan->TIMER.R; + + /* Reconfigure the RX MB in empty status.*/ + canp->flexcan->BUF[mbid].CS.B.CODE = 4U; +} + +#if CAN_USE_SLEEP_MODE || defined(__DOXYGEN__) +/** + * @brief Enters the sleep mode. + * + * @param[in] canp pointer to the @p CANDriver object + * + * @notapi + */ +void can_lld_sleep(CANDriver *canp) { + + /*canp->can->MCR |= CAN_MCR_SLEEP;*/ +} + +/** + * @brief Enforces leaving the sleep mode. + * + * @param[in] canp pointer to the @p CANDriver object + * + * @notapi + */ +void can_lld_wakeup(CANDriver *canp) { + + /*canp->can->MCR &= ~CAN_MCR_SLEEP;*/ +} +#endif /* CAN_USE_SLEEP_MODE */ + +#endif /* HAL_USE_CAN */ + +/** @} */ diff --git a/os/hal/platforms/SPC5xx/FlexCAN_v1/can_lld.h b/os/hal/platforms/SPC5xx/FlexCAN_v1/can_lld.h new file mode 100644 index 000000000..ad67c97da --- /dev/null +++ b/os/hal/platforms/SPC5xx/FlexCAN_v1/can_lld.h @@ -0,0 +1,520 @@ +/* + SPC5 HAL - Copyright (C) 2013 STMicroelectronics + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file FlexCAN_v1/can_lld.h + * @brief SPC5xx CAN subsystem low level driver header. + * + * @addtogroup CAN + * @{ + */ + +#ifndef _CAN_LLD_H_ +#define _CAN_LLD_H_ + +#if HAL_USE_CAN || defined(__DOXYGEN__) + +#include "spc5_flexcan.h" + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/** + * @brief This switch defines whether the driver implementation supports + * a low power switch mode with an automatic wakeup feature. + */ +#define CAN_SUPPORTS_SLEEP FALSE + +/** + * @brief This implementation supports 24 transmit mailboxes. + */ +#define CAN_TX_MAILBOXES 24 + +/** + * @brief This implementation supports one FIFO receive mailbox. + */ +#define CAN_RX_MAILBOXES 8 + +/** + * @brief This implementation supports eight FIFO receive filters. + */ +#define SPC5_CAN_MAX_FILTERS 8 + +/** + * @brief Enable filters. + */ +#define SPC5_CAN_FILTER_ON 1 + +/** + * @brief Disable filters. + */ +#define SPC5_CAN_FILTER_OFF 0 +/** + * @name CAN registers helper macros + * @{ + */ +#define CAN_MCR_MAXMB(n) (n) +#define CAN_MCR_AEN (1 << 12) +#define CAN_MCR_LPRIO_EN (1 << 13) +#define CAN_MCR_BCC (1 << 16) +#define CAN_MCR_SRX_DIS (1 << 17) +#define CAN_MCR_LPM_ACK (1 << 20) +#define CAN_MCR_WRN_EN (1 << 21) +#define CAN_MCR_SUPV (1 << 23) +#define CAN_MCR_FRZ_ACK (1 << 24) +#define CAN_MCR_WAK_MSK (1 << 26) +#define CAN_MCR_NOT_RDY (1 << 27) +#define CAN_MCR_HALT (1 << 28) +#define CAN_MCR_FEN (1 << 29) +#define CAN_MCR_FRZ (1 << 30) +#define CAN_MCR_MDIS (1 << 31) + +#define CAN_CTRL_PROPSEG(n) (n) +#define CAN_CTRL_LOM (1 << 3) +#define CAN_CTRL_TSYN (1 << 5) +#define CAN_CTRL_BOFF_REC (1 << 6) +#define CAN_CTRL_SMP (1 << 7) +#define CAN_CTRL_RWRN_MSK (1 << 10) +#define CAN_CTRL_TWRN_MSK (1 << 11) +#define CAN_CTRL_LPB (1 << 12) +#define CAN_CTRL_CLK_SRC (1 << 13) +#define CAN_CTRL_ERR_MSK (1 << 14) +#define CAN_CTRL_BOFF_MSK (1 << 15) +#define CAN_CTRL_PSEG2(n) ((n) << 16) +#define CAN_CTRL_PSEG1(n) ((n) << 19) +#define CAN_CTRL_RJW(n) ((n) << 22) +#define CAN_CTRL_PRESDIV(n) ((n) << 24) + +#define CAN_IDE_STD 0 /**< @brief Standard id. */ +#define CAN_IDE_EXT 1 /**< @brief Extended id. */ + +#define CAN_RTR_DATA 0 /**< @brief Data frame. */ +#define CAN_RTR_REMOTE 1 /**< @brief Remote frame. */ + +#define CAN_ESR_ERR_INT (1 << 1) +#define CAN_ESR_BOFF_INT (1 << 2) +#define CAN_ESR_TWRN_INT (1 << 14) +#define CAN_ESR_RWRN_INT (1 << 15) +/** @} */ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @name Configuration options + * @{ + */ +/** + * @brief CAN1 driver enable switch. + * @details If set to @p TRUE the support for CAN1 is included. + */ +#if !defined(SPC5_CAN_USE_FLEXCAN0) || defined(__DOXYGEN__) +#define SPC5_CAN_USE_FLEXCAN0 FALSE +#endif + +/** + * @brief CAN2 driver enable switch. + * @details If set to @p TRUE the support for CAN2 is included. + */ +#if !defined(SPC5_CAN_USE_FLEXCAN1) || defined(__DOXYGEN__) +#define SPC5_CAN_USE_FLEXCAN1 FALSE +#endif + +/** + * @brief CAN3 driver enable switch. + * @details If set to @p TRUE the support for CAN3 is included. + */ +#if !defined(SPC5_CAN_USE_FLEXCAN2) || defined(__DOXYGEN__) +#define SPC5_CAN_USE_FLEXCAN2 FALSE +#endif + +/** + * @brief CAN4 driver enable switch. + * @details If set to @p TRUE the support for CAN4 is included. + */ +#if !defined(SPC5_CAN_USE_FLEXCAN3) || defined(__DOXYGEN__) +#define SPC5_CAN_USE_FLEXCAN3 FALSE +#endif + +/** + * @brief CAN5 driver enable switch. + * @details If set to @p TRUE the support for CAN5 is included. + */ +#if !defined(SPC5_CAN_USE_FLEXCAN4) || defined(__DOXYGEN__) +#define SPC5_CAN_USE_FLEXCAN4 FALSE +#endif + +/** + * @brief CAN6 driver enable switch. + * @details If set to @p TRUE the support for CAN6 is included. + */ +#if !defined(SPC5_CAN_USE_FLEXCAN5) || defined(__DOXYGEN__) +#define SPC5_CAN_USE_FLEXCAN5 FALSE +#endif + +/** + * @brief CAN1 interrupt priority level setting. + */ +#if !defined(SPC5_CAN_FLEXCAN0_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define SPC5_CAN_FLEXCAN0_IRQ_PRIORITY 11 +#endif +/** @} */ + +/** + * @brief CAN2 interrupt priority level setting. + */ +#if !defined(SPC5_CAN_FLEXCAN1_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define SPC5_CAN_FLEXCAN1_IRQ_PRIORITY 11 +#endif +/** @} */ + +/** + * @brief CAN3 interrupt priority level setting. + */ +#if !defined(SPC5_CAN_FLEXCAN2_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define SPC5_CAN_FLEXCAN2_IRQ_PRIORITY 11 +#endif +/** @} */ + +/** + * @brief CAN4 interrupt priority level setting. + */ +#if !defined(SPC5_CAN_FLEXCAN3_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define SPC5_CAN_FLEXCAN3_IRQ_PRIORITY 11 +#endif +/** @} */ + +/** + * @brief CAN5 interrupt priority level setting. + */ +#if !defined(SPC5_CAN_FLEXCAN4_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define SPC5_CAN_FLEXCAN4_IRQ_PRIORITY 11 +#endif +/** @} */ + +/** + * @brief CAN6 interrupt priority level setting. + */ +#if !defined(SPC5_CAN_FLEXCAN5_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define SPC5_CAN_FLEXCAN5_IRQ_PRIORITY 11 +#endif +/** @} */ + +/** + * @brief CAN filters enable setting. + */ +#if !defined(SPC5_CAN_USE_FILTERS) || defined(__DOXYGEN__) +#define SPC5_CAN_USE_FILTERS FALSE +#endif +/** @} */ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +#if SPC5_CAN_USE_FLEXCAN0 && !SPC5_HAS_FLEXCAN0 +#error "CAN1 not present in the selected device" +#endif + +#if SPC5_CAN_USE_FLEXCAN1 && !SPC5_HAS_FLEXCAN1 +#error "CAN2 not present in the selected device" +#endif + +#if SPC5_CAN_USE_FLEXCAN2 && !SPC5_HAS_FLEXCAN2 +#error "CAN3 not present in the selected device" +#endif + +#if SPC5_CAN_USE_FLEXCAN3 && !SPC5_HAS_FLEXCAN3 +#error "CAN4 not present in the selected device" +#endif + +#if SPC5_CAN_USE_FLEXCAN4 && !SPC5_HAS_FLEXCAN4 +#error "CAN5 not present in the selected device" +#endif + +#if SPC5_CAN_USE_FLEXCAN5 && !SPC5_HAS_FLEXCAN5 +#error "CAN6 not present in the selected device" +#endif + +#if !SPC5_CAN_USE_FLEXCAN0 && !SPC5_CAN_USE_FLEXCAN1 \ + && !SPC5_CAN_USE_FLEXCAN2 && !SPC5_CAN_USE_FLEXCAN3 \ + && !SPC5_CAN_USE_FLEXCAN4 && !SPC5_CAN_USE_FLEXCAN5 +#error "CAN driver activated but no CAN peripheral assigned" +#endif + +#if CAN_USE_SLEEP_MODE && !CAN_SUPPORTS_SLEEP +#error "CAN sleep mode not supported in this architecture" +#endif + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief Type of a transmission mailbox index. + */ +typedef uint32_t canmbx_t; + +/** + * @brief CAN TX MB structure. + */ +typedef struct { + union { + vuint32_t R; + struct { + vuint8_t:4; + vuint8_t CODE:4; + vuint8_t:1; + vuint8_t SRR:1; + vuint8_t IDE:1; + vuint8_t RTR:1; + vuint8_t LENGTH:4; + vuint16_t TIMESTAMP:16; + } B; + } CS; + + union { + vuint32_t R; + struct { + vuint8_t PRIO:3; + vuint32_t ID:29; + } B; + } ID; + vuint32_t DATA[2]; /* Data buffer in words (32 bits) */ +} CAN_TxMailBox_TypeDef; + +/** + * @brief CAN transmission frame. + * @note Accessing the frame data as word16 or word32 is not portable because + * machine data endianness, it can be still useful for a quick filling. + */ +typedef struct { + struct { + uint8_t LENGTH:4; /**< @brief Data length. */ + uint8_t RTR:1; /**< @brief Frame type. */ + uint8_t IDE:1; /**< @brief Identifier type. */ + }; + union { + struct { + uint32_t SID:11; /**< @brief Standard identifier.*/ + }; + struct { + uint32_t EID:29; /**< @brief Extended identifier.*/ + }; + }; + union { + uint8_t data8[8]; /**< @brief Frame data. */ + uint16_t data16[4]; /**< @brief Frame data. */ + uint32_t data32[2]; /**< @brief Frame data. */ + }; +} CANTxFrame; + +/** + * @brief CAN received frame. + * @note Accessing the frame data as word16 or word32 is not portable because + * machine data endianness, it can be still useful for a quick filling. + */ +typedef struct { + struct { + uint16_t TIME; /**< @brief Time stamp. */ + }; + struct { + uint8_t LENGTH:4; /**< @brief Data length. */ + uint8_t RTR:1; /**< @brief Frame type. */ + uint8_t IDE:1; /**< @brief Identifier type. */ + }; + union { + struct { + uint32_t SID:11; /**< @brief Standard identifier.*/ + }; + struct { + uint32_t EID:29; /**< @brief Extended identifier.*/ + }; + }; + union { + uint8_t data8[8]; /**< @brief Frame data. */ + uint16_t data16[4]; /**< @brief Frame data. */ + uint32_t data32[2]; /**< @brief Frame data. */ + }; +} CANRxFrame; + +/** + * @brief CAN filter. + * @note Refer to the SPC5 reference manual for info about filters. + */ +typedef struct { + /** + * @brief Filter scale. + * @note This bit represents the EXT bit associated to this + * filter (0=standard ID mode, 1=extended ID mode). + */ + uint32_t scale:1; + /** + * @brief Filter register (identifier). + */ + uint32_t register1; +} CANFilter; + +/** + * @brief Driver configuration structure. + */ +typedef struct { + /** + * @brief CAN MCR register initialization data. + * @note Some bits in this register are enforced by the driver regardless + * their status in this field. + */ + uint32_t mcr; + /** + * @brief CAN CTRL register initialization data. + * @note Some bits in this register are enforced by the driver regardless + * their status in this field. + */ + uint32_t ctrl; +#if SPC5_CAN_USE_FILTERS + /** + * @brief CAN filters structure. + */ + CANFilter RxFilter[CAN_RX_MAILBOXES]; +#endif +} CANConfig; + +/** + * @brief Structure representing an CAN driver. + */ +typedef struct { + /** + * @brief Driver state. + */ + canstate_t state; + /** + * @brief Current configuration data. + */ + const CANConfig *config; + /** + * @brief Transmission queue semaphore. + */ + Semaphore txsem; + /** + * @brief Receive queue semaphore. + */ + Semaphore rxsem; + /** + * @brief One or more frames become available. + * @note After broadcasting this event it will not be broadcasted again + * until the received frames queue has been completely emptied. It + * is not broadcasted for each received frame. It is + * responsibility of the application to empty the queue by + * repeatedly invoking @p chReceive() when listening to this event. + * This behavior minimizes the interrupt served by the system + * because CAN traffic. + * @note The flags associated to the listeners will indicate which + * receive mailboxes become non-empty. + */ + EventSource rxfull_event; + /** + * @brief One or more transmission mailbox become available. + * @note The flags associated to the listeners will indicate which + * transmit mailboxes become empty. + * + */ + EventSource txempty_event; + /** + * @brief A CAN bus error happened. + * @note The flags associated to the listeners will indicate the + * error(s) that have occurred. + */ + EventSource error_event; +#if CAN_USE_SLEEP_MODE || defined (__DOXYGEN__) + /** + * @brief Entering sleep state event. + */ + EventSource sleep_event; + /** + * @brief Exiting sleep state event. + */ + EventSource wakeup_event; +#endif /* CAN_USE_SLEEP_MODE */ + /* End of the mandatory fields.*/ + /** + * @brief Pointer to the CAN registers. + */ + volatile struct spc5_flexcan *flexcan; +} CANDriver; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if SPC5_CAN_USE_FLEXCAN0 && !defined(__DOXYGEN__) +extern CANDriver CAND1; +#endif + +#if SPC5_CAN_USE_FLEXCAN1 && !defined(__DOXYGEN__) +extern CANDriver CAND2; +#endif + +#if SPC5_CAN_USE_FLEXCAN2 && !defined(__DOXYGEN__) +extern CANDriver CAND3; +#endif + +#if SPC5_CAN_USE_FLEXCAN3 && !defined(__DOXYGEN__) +extern CANDriver CAND4; +#endif + +#if SPC5_CAN_USE_FLEXCAN4 && !defined(__DOXYGEN__) +extern CANDriver CAND5; +#endif + +#if SPC5_CAN_USE_FLEXCAN5 && !defined(__DOXYGEN__) +extern CANDriver CAND6; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void can_lld_init(void); + void can_lld_start(CANDriver *canp); + void can_lld_stop(CANDriver *canp); + bool_t can_lld_is_tx_empty(CANDriver *canp, + canmbx_t mailbox); + void can_lld_transmit(CANDriver *canp, + canmbx_t mailbox, + const CANTxFrame *crfp); + bool_t can_lld_is_rx_nonempty(CANDriver *canp, + canmbx_t mailbox); + void can_lld_receive(CANDriver *canp, + canmbx_t mailbox, + CANRxFrame *ctfp); +#if CAN_USE_SLEEP_MODE + void can_lld_sleep(CANDriver *canp); + void can_lld_wakeup(CANDriver *canp); +#endif /* CAN_USE_SLEEP_MODE */ +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_CAN */ + +#endif /* _CAN_LLD_H_ */ + +/** @} */ diff --git a/os/hal/platforms/SPC5xx/FlexCAN_v1/spc5_flexcan.h b/os/hal/platforms/SPC5xx/FlexCAN_v1/spc5_flexcan.h new file mode 100644 index 000000000..580f78827 --- /dev/null +++ b/os/hal/platforms/SPC5xx/FlexCAN_v1/spc5_flexcan.h @@ -0,0 +1,442 @@ +/* + * Licensed under ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/** + * @file FlexCAN_v1/spc5_flexcan.h + * @brief SPC5xx FlexCAN header file. + * + * @addtogroup PWM + * @{ + */ + +#ifndef _SPC5_FLEXCAN_H_ +#define _SPC5_FLEXCAN_H_ + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief SPC5 FlexCAN registers block. + * @note Redefined from the SPC5 headers because the non uniform + * declaration of the SubModules registers among the various + * sub-families. + */ +struct FLEXCAN_BUFFER_t { + union { + vuint32_t R; + struct { + vuint32_t:4; + vuint32_t CODE:4; + vuint32_t:1; + vuint32_t SRR:1; + vuint32_t IDE:1; + vuint32_t RTR:1; + vuint32_t LENGTH:4; + vuint32_t TIMESTAMP:16; + } B; + } CS; + + union { + vuint32_t R; + struct { + vuint32_t PRIO:3; + vuint32_t STD_ID:11; + vuint32_t EXT_ID:18; + } B; + } ID; + + union { + /*vuint8_t B[8]; *//* Data buffer in Bytes (8 bits) */ + /*vuint16_t H[4]; *//* Data buffer in Half-words (16 bits) */ + vuint32_t W[2]; /* Data buffer in words (32 bits) */ + /*vuint32_t R[2]; *//* Data buffer in words (32 bits) */ + } DATA; + +}; /* end of FLEXCAN_BUF_t */ + +struct FLEXCAN_RXFIFO_BUFFER_t { + union { + vuint32_t R; + struct { + vuint32_t:9; + vuint32_t SRR:1; + vuint32_t IDE:1; + vuint32_t RTR:1; + vuint32_t LENGTH:4; + vuint32_t TIMESTAMP:16; + } B; + } CS; + + union { + vuint32_t R; + struct { + vuint32_t:3; + vuint32_t STD_ID:11; + vuint32_t EXT_ID:18; + } B; + } ID; + + union { + /*vuint8_t B[8]; *//* Data buffer in Bytes (8 bits) */ + /*vuint16_t H[4]; *//* Data buffer in Half-words (16 bits) */ + vuint32_t W[2]; /* Data buffer in words (32 bits) */ + /*vuint32_t R[2]; *//* Data buffer in words (32 bits) */ + } DATA; + + uint32_t FLEXCAN_RXFIFO_reserved[20]; /* {0x00E0-0x0090}/0x4 = 0x14 */ + + union { + vuint32_t R; + } IDTABLE[8]; + +}; /* end of FLEXCAN_RXFIFO_t */ + +struct spc5_flexcan { + union { + vuint32_t R; + struct { + vuint32_t MDIS:1; + vuint32_t FRZ:1; + vuint32_t FEN:1; + vuint32_t HALT:1; + vuint32_t NOTRDY:1; + vuint32_t WAKMSK:1; + vuint32_t SOFTRST:1; + vuint32_t FRZACK:1; + vuint32_t SUPV:1; + vuint32_t SLFWAK:1; + vuint32_t WRNEN:1; + vuint32_t LPMACK:1; + vuint32_t WAKSRC:1; + vuint32_t:1; + vuint32_t SRXDIS:1; + vuint32_t BCC:1; + vuint32_t:2; + vuint32_t LPRIO_EN:1; + vuint32_t AEN:1; + vuint32_t:2; + vuint32_t IDAM:2; + vuint32_t:2; + vuint32_t MAXMB:6; + } B; + } MCR; /* Module Configuration Register */ + + union { + vuint32_t R; + struct { + vuint32_t PRESDIV:8; + vuint32_t RJW:2; + vuint32_t PSEG1:3; + vuint32_t PSEG2:3; + vuint32_t BOFFMSK:1; + vuint32_t ERRMSK:1; + vuint32_t CLKSRC:1; + vuint32_t LPB:1; + vuint32_t TWRNMSK:1; + vuint32_t RWRNMSK:1; + vuint32_t:2; + vuint32_t SMP:1; + vuint32_t BOFFREC:1; + vuint32_t TSYN:1; + vuint32_t LBUF:1; + vuint32_t LOM:1; + vuint32_t PROPSEG:3; + } B; + } CR; /* Control Register */ + + union { + vuint32_t R; + } TIMER; /* Free Running Timer */ + + uint32_t FLEXCAN_reserved1; + + union { + vuint32_t R; + struct { + vuint32_t MI:32; + } B; + } RXGMASK; /* RX Global Mask */ + + union { + vuint32_t R; + struct { + vuint32_t MI:32; + } B; + } RX14MASK; /* RX 14 Mask */ + + union { + vuint32_t R; + struct { + vuint32_t MI:32; + } B; + } RX15MASK; /* RX 15 Mask */ + + union { + vuint32_t R; + struct { + vuint32_t:16; + vuint32_t RXECNT:8; + vuint32_t TXECNT:8; + } B; + } ECR; /* Error Counter Register */ + + union { + vuint32_t R; + struct { + vuint32_t:14; + vuint32_t TWRNINT:1; + vuint32_t RWRNINT:1; + vuint32_t BIT1ERR:1; + vuint32_t BIT0ERR:1; + vuint32_t ACKERR:1; + vuint32_t CRCERR:1; + vuint32_t FRMERR:1; + vuint32_t STFERR:1; + vuint32_t TXWRN:1; + vuint32_t RXWRN:1; + vuint32_t IDLE:1; + vuint32_t TXRX:1; + vuint32_t FLTCONF:2; + vuint32_t:1; + vuint32_t BOFFINT:1; + vuint32_t ERRINT:1; + vuint32_t WAKINT:1; + } B; + } ESR; /* Error and Status Register */ + + union { + vuint32_t R; + struct { + vuint32_t BUF63M:1; + vuint32_t BUF62M:1; + vuint32_t BUF61M:1; + vuint32_t BUF60M:1; + vuint32_t BUF59M:1; + vuint32_t BUF58M:1; + vuint32_t BUF57M:1; + vuint32_t BUF56M:1; + vuint32_t BUF55M:1; + vuint32_t BUF54M:1; + vuint32_t BUF53M:1; + vuint32_t BUF52M:1; + vuint32_t BUF51M:1; + vuint32_t BUF50M:1; + vuint32_t BUF49M:1; + vuint32_t BUF48M:1; + vuint32_t BUF47M:1; + vuint32_t BUF46M:1; + vuint32_t BUF45M:1; + vuint32_t BUF44M:1; + vuint32_t BUF43M:1; + vuint32_t BUF42M:1; + vuint32_t BUF41M:1; + vuint32_t BUF40M:1; + vuint32_t BUF39M:1; + vuint32_t BUF38M:1; + vuint32_t BUF37M:1; + vuint32_t BUF36M:1; + vuint32_t BUF35M:1; + vuint32_t BUF34M:1; + vuint32_t BUF33M:1; + vuint32_t BUF32M:1; + } B; + } IMRH; /* Interruput Masks Register */ + + union { + vuint32_t R; + struct { + vuint32_t BUF31M:1; + vuint32_t BUF30M:1; + vuint32_t BUF29M:1; + vuint32_t BUF28M:1; + vuint32_t BUF27M:1; + vuint32_t BUF26M:1; + vuint32_t BUF25M:1; + vuint32_t BUF24M:1; + vuint32_t BUF23M:1; + vuint32_t BUF22M:1; + vuint32_t BUF21M:1; + vuint32_t BUF20M:1; + vuint32_t BUF19M:1; + vuint32_t BUF18M:1; + vuint32_t BUF17M:1; + vuint32_t BUF16M:1; + vuint32_t BUF15M:1; + vuint32_t BUF14M:1; + vuint32_t BUF13M:1; + vuint32_t BUF12M:1; + vuint32_t BUF11M:1; + vuint32_t BUF10M:1; + vuint32_t BUF09M:1; + vuint32_t BUF08M:1; + vuint32_t BUF07M:1; + vuint32_t BUF06M:1; + vuint32_t BUF05M:1; + vuint32_t BUF04M:1; + vuint32_t BUF03M:1; + vuint32_t BUF02M:1; + vuint32_t BUF01M:1; + vuint32_t BUF00M:1; + } B; + } IMRL; /* Interruput Masks Register */ + + union { + vuint32_t R; + struct { + vuint32_t BUF63I:1; + vuint32_t BUF62I:1; + vuint32_t BUF61I:1; + vuint32_t BUF60I:1; + vuint32_t BUF59I:1; + vuint32_t BUF58I:1; + vuint32_t BUF57I:1; + vuint32_t BUF56I:1; + vuint32_t BUF55I:1; + vuint32_t BUF54I:1; + vuint32_t BUF53I:1; + vuint32_t BUF52I:1; + vuint32_t BUF51I:1; + vuint32_t BUF50I:1; + vuint32_t BUF49I:1; + vuint32_t BUF48I:1; + vuint32_t BUF47I:1; + vuint32_t BUF46I:1; + vuint32_t BUF45I:1; + vuint32_t BUF44I:1; + vuint32_t BUF43I:1; + vuint32_t BUF42I:1; + vuint32_t BUF41I:1; + vuint32_t BUF40I:1; + vuint32_t BUF39I:1; + vuint32_t BUF38I:1; + vuint32_t BUF37I:1; + vuint32_t BUF36I:1; + vuint32_t BUF35I:1; + vuint32_t BUF34I:1; + vuint32_t BUF33I:1; + vuint32_t BUF32I:1; + } B; + } IFRH; /* Interruput Flag Register */ + + union { + vuint32_t R; + struct { + vuint32_t BUF31I:1; + vuint32_t BUF30I:1; + vuint32_t BUF29I:1; + vuint32_t BUF28I:1; + vuint32_t BUF27I:1; + vuint32_t BUF26I:1; + vuint32_t BUF25I:1; + vuint32_t BUF24I:1; + vuint32_t BUF23I:1; + vuint32_t BUF22I:1; + vuint32_t BUF21I:1; + vuint32_t BUF20I:1; + vuint32_t BUF19I:1; + vuint32_t BUF18I:1; + vuint32_t BUF17I:1; + vuint32_t BUF16I:1; + vuint32_t BUF15I:1; + vuint32_t BUF14I:1; + vuint32_t BUF13I:1; + vuint32_t BUF12I:1; + vuint32_t BUF11I:1; + vuint32_t BUF10I:1; + vuint32_t BUF09I:1; + vuint32_t BUF08I:1; + vuint32_t BUF07I:1; + vuint32_t BUF06I:1; + vuint32_t BUF05I:1; + vuint32_t BUF04I:1; + vuint32_t BUF03I:1; + vuint32_t BUF02I:1; + vuint32_t BUF01I:1; + vuint32_t BUF00I:1; + } B; + } IFRL; /* Interruput Flag Register */ + + uint32_t FLEXCAN_reserved2[19]; /* {0x0080-0x0034}/0x4 = 0x13 */ + +/****************************************************************************/ +/* Use either Standard Buffer Structure OR RX FIFO and Buffer Structure */ +/****************************************************************************/ + /* Standard Buffer Structure */ + struct FLEXCAN_BUFFER_t BUF[64]; + + /* RX FIFO and Buffer Structure */ + /*struct FLEXCAN_RXFIFO_BUFFER_t RXFIFO; + struct FLEXCAN_BUFFER_t BUF[56];*/ +/****************************************************************************/ + + uint32_t FLEXCAN_reserved3[256]; /* {0x0880-0x0480}/0x4 = 0x100 */ + + union { + vuint32_t R; + struct { + vuint32_t MI:32; + } B; + } RXIMR[64]; /* RX Individual Mask Registers */ + + }; /* end of FLEXCAN_tag */ + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/** + * @name FlexCAN units references + * @{ + */ +#if SPC5_HAS_FLEXCAN0 || defined(__DOXYGEN__) +#define SPC5_FLEXCAN_0 (*(volatile struct spc5_flexcan *)0xFFFC0000UL) +#endif + +#if SPC5_HAS_FLEXCAN1 || defined(__DOXYGEN__) +#define SPC5_FLEXCAN_1 (*(volatile struct spc5_flexcan *)0xFFFC4000UL) +#endif + +#if SPC5_HAS_FLEXCAN2 || defined(__DOXYGEN__) +#define SPC5_FLEXCAN_2 (*(volatile struct spc5_flexcan *)0xFFFC8000UL) +#endif + +#if SPC5_HAS_FLEXCAN3 || defined(__DOXYGEN__) +#define SPC5_FLEXCAN_3 (*(volatile struct spc5_flexcan *)0xFFFCC000UL) +#endif + +#if SPC5_HAS_FLEXCAN4 || defined(__DOXYGEN__) +#define SPC5_FLEXCAN_4 (*(volatile struct spc5_flexcan *)0xFFFD0000UL) +#endif + +#if SPC5_HAS_FLEXCAN5 || defined(__DOXYGEN__) +#define SPC5_FLEXCAN_5 (*(volatile struct spc5_flexcan *)0xFFFD4000UL) +#endif +/** @} */ + +#endif /* _SPC5_FLEXCAN_H_ */ + +/** @} */ diff --git a/testhal/SPC560BCxx/CAN/Makefile b/testhal/SPC560BCxx/CAN/Makefile new file mode 100644 index 000000000..97618eebb --- /dev/null +++ b/testhal/SPC560BCxx/CAN/Makefile @@ -0,0 +1,140 @@ +############################################################################## +# This file is automatically generated and can be overwritten, do no change +# this file manually. +############################################################################## +# Build global options +# NOTE: Can be overridden externally. +# + +# Compiler options here. +ifeq ($(USE_OPT),) + USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16 +endif + +# C specific options here (added to USE_OPT). +ifeq ($(USE_COPT),) + USE_COPT = +endif + +# C++ specific options here (added to USE_OPT). +ifeq ($(USE_CPPOPT),) + USE_CPPOPT = -fno-rtti +endif + +# Enable this if you want the linker to remove unused code and data. +ifeq ($(USE_LINK_GC),) + USE_LINK_GC = yes +endif + +# If enabled, this option allows to compile the application in VLE mode. +ifeq ($(USE_VLE),) + USE_VLE = yes +endif + +# Enable this if you want to see the full log while compiling. +ifeq ($(USE_VERBOSE_COMPILE),) + USE_VERBOSE_COMPILE = no +endif + +# +# Build global options +############################################################################## + +############################################################################## +# Project, sources and paths +# + +# Define project name here +PROJECT = out + +# Imported source files +include components/components.mak + +# Checks if there is a user mak file in the project directory. +ifneq ($(wildcard user.mak),) + include user.mak +endif + +# Define linker script file here +LDSCRIPT= application.ld + +# C sources here. +CSRC = $(LIB_C_SRC) \ + $(APP_C_SRC) \ + $(U_C_SRC) \ + ./components/components.c \ + ./main.c + +# C++ sources here. +CPPSRC = $(LIB_CPP_SRC) \ + $(APP_CPP_SRC) \ + $(U_CPP_SRC) + +# List ASM source files here +ASMSRC = $(LIB_ASM_SRC) \ + $(APP_ASM_SRC) \ + $(U_ASM_SRC) + +INCDIR = $(LIB_INCLUDES) \ + $(APP_INCLUDES) \ + ./components + +# +# Project, sources and paths +############################################################################## + +############################################################################## +# Compiler settings +# + +#MCU = e500mc -meabi -msdata=none -mnew-mnemonics -mregnames +MCU = e200zx -meabi -msdata=none -mnew-mnemonics -mregnames + +TRGT = ppc-vle- +CC = $(TRGT)gcc +CPPC = $(TRGT)g++ +# Enable loading with g++ only if you need C++ runtime support. +# NOTE: You can use C++ even without C++ support if you are careful. C++ +# runtime support makes code size explode. +LD = $(TRGT)gcc +#LD = $(TRGT)g++ +CP = $(TRGT)objcopy +AS = $(TRGT)gcc -x assembler-with-cpp +OD = $(TRGT)objdump +HEX = $(CP) -O ihex +BIN = $(CP) -O binary + +# Define C warning options here +CWARN = -Wall -Wextra -Wstrict-prototypes + +# Define C++ warning options here +CPPWARN = -Wall -Wextra + +# +# Compiler settings +############################################################################## + +############################################################################## +# Start of default section +# + +# List all default C defines here, like -D_DEBUG=1 +DDEFS = -DSPC560B50L5 + +# List all default ASM defines here, like -D_DEBUG=1 +DADEFS = + +# List all default directories to look for include files here +DINCDIR = + +# List the default directory to look for the libraries here +DLIBDIR = + +# List all default libraries here +DLIBS = + +# +# End of default section +############################################################################## + +include C:/SPC5Studio/eclipse/plugins/com.st.tools.spc5.components.platform.spc560bcxx_1.0.0.201302201417/component/lib/rsc/rules.mk diff --git a/testhal/SPC560BCxx/CAN/chconf.h b/testhal/SPC560BCxx/CAN/chconf.h new file mode 100644 index 000000000..8800269d4 --- /dev/null +++ b/testhal/SPC560BCxx/CAN/chconf.h @@ -0,0 +1,529 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef _CHCONF_H_ +#define _CHCONF_H_ + +/*===========================================================================*/ +/** + * @name Kernel parameters and options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#if !defined(CH_FREQUENCY) || defined(__DOXYGEN__) +#define CH_FREQUENCY 1000 +#endif + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + */ +#if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__) +#define CH_TIME_QUANTUM 20 +#endif + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_USE_MEMCORE. + */ +#if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__) +#define CH_MEMCORE_SIZE 0 +#endif + +/** + * @brief Idle thread automatic spawn suppression. + * @details When this option is activated the function @p chSysInit() + * does not spawn the idle thread automatically. The application has + * then the responsibility to do one of the following: + * - Spawn a custom idle thread at priority @p IDLEPRIO. + * - Change the main() thread priority to @p IDLEPRIO then enter + * an endless loop. In this scenario the @p main() thread acts as + * the idle thread. + * . + * @note Unless an idle thread is spawned the @p main() thread must not + * enter a sleep state. + */ +#if !defined(CH_NO_IDLE_THREAD) || defined(__DOXYGEN__) +#define CH_NO_IDLE_THREAD FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Performance options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__) +#define CH_OPTIMIZE_SPEED TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Subsystem options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_REGISTRY) || defined(__DOXYGEN__) +#define CH_USE_REGISTRY TRUE +#endif + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__) +#define CH_USE_WAITEXIT TRUE +#endif + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES TRUE +#endif + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES_PRIORITY FALSE +#endif + +/** + * @brief Atomic semaphore API. + * @details If enabled then the semaphores the @p chSemSignalWait() API + * is included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__) +#define CH_USE_SEMSW TRUE +#endif + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__) +#define CH_USE_MUTEXES TRUE +#endif + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MUTEXES. + */ +#if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS TRUE +#endif + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_CONDVARS. + */ +#if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS_TIMEOUT TRUE +#endif + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__) +#define CH_USE_EVENTS TRUE +#endif + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_EVENTS. + */ +#if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_EVENTS_TIMEOUT TRUE +#endif + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES TRUE +#endif + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_MESSAGES. + */ +#if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES_PRIORITY FALSE +#endif + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__) +#define CH_USE_MAILBOXES TRUE +#endif + +/** + * @brief I/O Queues APIs. + * @details If enabled then the I/O queues APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__) +#define CH_USE_QUEUES TRUE +#endif + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__) +#define CH_USE_MEMCORE TRUE +#endif + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MEMCORE and either @p CH_USE_MUTEXES or + * @p CH_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) +#define CH_USE_HEAP TRUE +#endif + +/** + * @brief C-runtime allocator. + * @details If enabled the the heap allocator APIs just wrap the C-runtime + * @p malloc() and @p free() functions. + * + * @note The default is @p FALSE. + * @note Requires @p CH_USE_HEAP. + * @note The C-runtime may or may not require @p CH_USE_MEMCORE, see the + * appropriate documentation. + */ +#if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__) +#define CH_USE_MALLOC_HEAP FALSE +#endif + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__) +#define CH_USE_MEMPOOLS TRUE +#endif + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_WAITEXIT. + * @note Requires @p CH_USE_HEAP and/or @p CH_USE_MEMPOOLS. + */ +#if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__) +#define CH_USE_DYNAMIC TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Debug options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Debug option, system state check. + * @details If enabled the correct call protocol for system APIs is checked + * at runtime. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_SYSTEM_STATE_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_SYSTEM_STATE_CHECK FALSE +#endif + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_CHECKS FALSE +#endif + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_ASSERTS FALSE +#endif + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the context switch circular trace buffer is + * activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_TRACE FALSE +#endif + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_STACK_CHECK FALSE +#endif + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__) +#define CH_DBG_FILL_THREADS FALSE +#endif + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p Thread structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p TRUE. + * @note This debug option is defaulted to TRUE because it is required by + * some test cases into the test suite. + */ +#if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__) +#define CH_DBG_THREADS_PROFILING TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel hooks + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads descriptor structure extension. + * @details User fields added to the end of the @p Thread structure. + */ +#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) +#define THREAD_EXT_FIELDS \ + +#endif + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p chThdInit() API. + * + * @note It is invoked from within @p chThdInit() and implicitly from all + * the threads creation APIs. + */ +#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_INIT_HOOK(tp) { \ +} +#endif + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + * + * @note It is inserted into lock zone. + * @note It is also invoked when the threads simply return in order to + * terminate. + */ +#if !defined(THREAD_EXT_EXIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_EXIT_HOOK(tp) { \ +} +#endif + +/** + * @brief Context switch hook. + * @details This hook is invoked just before switching between threads. + */ +#if !defined(THREAD_CONTEXT_SWITCH_HOOK) || defined(__DOXYGEN__) +#define THREAD_CONTEXT_SWITCH_HOOK(ntp, otp) { \ +} +#endif + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) +#define IDLE_LOOP_HOOK() { \ +} +#endif + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#if !defined(SYSTEM_TICK_EVENT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_TICK_EVENT_HOOK() { \ +} +#endif + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#if !defined(SYSTEM_HALT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_HALT_HOOK() { \ +} +#endif + +/** @} */ + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + +#endif /* _CHCONF_H_ */ + +/** @} */ diff --git a/testhal/SPC560BCxx/CAN/halconf.h b/testhal/SPC560BCxx/CAN/halconf.h new file mode 100644 index 000000000..c316bb385 --- /dev/null +++ b/testhal/SPC560BCxx/CAN/halconf.h @@ -0,0 +1,371 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * + * @addtogroup HAL_CONF + * @{ + */ + +#ifndef _HALCONF_H_ +#define _HALCONF_H_ + +#include "mcuconf.h" + +/** + * @name Drivers enable switches + */ +/** + * @brief Enables the TM subsystem. + */ +#if !defined(HAL_USE_TM) || defined(__DOXYGEN__) +#define HAL_USE_TM FALSE +#endif + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC FALSE +#endif + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN TRUE +#endif + +/** + * @brief Enables the EXT subsystem. + */ +#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__) +#define HAL_USE_EXT FALSE +#endif + +/** + * @brief Enables the GPT subsystem. + */ +#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) +#define HAL_USE_GPT FALSE +#endif + +/** + * @brief Enables the I2C subsystem. + */ +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C FALSE +#endif + +/** + * @brief Enables the ICU subsystem. + */ +#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) +#define HAL_USE_ICU FALSE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM FALSE +#endif + +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC FALSE +#endif + +/** + * @brief Enables the SDC subsystem. + */ +#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) +#define HAL_USE_SDC FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL TRUE +#endif + +/** + * @brief Enables the SERIAL over USB subsystem. + */ +#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL_USB FALSE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI FALSE +#endif + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART FALSE +#endif + +/** + * @brief Enables the USB subsystem. + */ +#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) +#define HAL_USE_USB FALSE +#endif +/** @} */ + +/*===========================================================================*/ +/** + * @name ADC driver related setting + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION FALSE +#endif +/** @} */ + +/*===========================================================================*/ +/** + * @name CAN driver related setting + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Sleep mode related APIs inclusion switch. + */ +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE FALSE +#endif +/** @} */ + +/*===========================================================================*/ +/** + * @name I2C driver related setting + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Enables the mutual exclusion APIs on the I2C bus. + */ +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION FALSE +#endif +/** @} */ + +/*===========================================================================*/ +/** + * @name MAC driver related setting + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) +#define MAC_USE_ZERO_COPY FALSE +#endif + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif +/** @} */ + +/*===========================================================================*/ +/** + * @name MMC_SPI driver related setting + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + * This option is recommended also if the SPI driver does not + * use a DMA channel and heavily loads the CPU. + */ +#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) +#define MMC_NICE_WAITING TRUE +#endif +/** @} */ + +/*===========================================================================*/ +/** + * @name SDC driver related setting + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Number of initialization attempts before rejecting the card. + * @note Attempts are performed at 10mS intervals. + */ +#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) +#define SDC_INIT_RETRY 1 +#endif + +/** + * @brief Include support for MMC cards. + * @note MMC support is not yet implemented so this option must be kept + * at @p FALSE. + */ +#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) +#define SDC_MMC_SUPPORT FALSE +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + */ +#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) +#define SDC_NICE_WAITING TRUE +#endif +/** @} */ + +/*===========================================================================*/ +/** + * @name SERIAL driver related setting + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 64 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif +/** @} */ + +/*===========================================================================*/ +/** + * @name SERIAL_USB driver related setting + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Serial over USB buffers size. + * @details Configuration parameter, the buffer size must be a multiple of + * the USB data endpoint maximum packet size. + * @note The default is 64 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_USB_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_USB_BUFFERS_SIZE 64 +#endif +/** @} */ + +/*===========================================================================*/ +/** + * @name SPI driver related setting + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION FALSE +#endif +/** @} */ + +#endif /* _HALCONF_H_ */ + +/** @} */ diff --git a/testhal/SPC560BCxx/CAN/main.c b/testhal/SPC560BCxx/CAN/main.c new file mode 100644 index 000000000..e375dbc1a --- /dev/null +++ b/testhal/SPC560BCxx/CAN/main.c @@ -0,0 +1,149 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include "ch.h" +#include "hal.h" + +struct can_instance { + CANDriver *canp; + uint32_t led; +}; + +static const struct can_instance can1 = {&CAND5, PE_LED1}; + +/* + * Internal loopback mode, 1MBaud. + * See chapter 25 on the SPC5 reference manual. + */ +static const CANConfig cancfg = { + CAN_MCR_WRN_EN, + CAN_CTRL_LPB | CAN_CTRL_PROPSEG(2) | CAN_CTRL_PSEG2(7) | + CAN_CTRL_PSEG1(3) | CAN_CTRL_PRESDIV(3) +#if SPC5_CAN_USE_FILTERS + , + { + {0, 0x00000001}, + {1, 0x01234567}, + {0, 0x00000000}, + {0, 0x00000003}, + {0, 0x00000004}, + {0, 0x00000005}, + {0, 0x00000006}, + {0, 0x00000007} + } +#endif +}; + +#if SPC5_CAN_USE_FILTERS +flagsmask_t rxFlag; +#endif + +/* + * Receiver thread. + */ +static WORKING_AREA(can_rx_wa, 256); +static msg_t can_rx(void *p) { + struct can_instance *cip = p; + EventListener el; + CANRxFrame rxmsg; + (void)p; + chRegSetThreadName("receiver"); + chEvtRegister(&cip->canp->rxfull_event, &el, 0); +#if SPC5_CAN_USE_FILTERS + rxFlag = chEvtGetAndClearFlagsI(&el); +#endif + while(!chThdShouldTerminate()) { + if (chEvtWaitAnyTimeout(ALL_EVENTS, MS2ST(100)) == 0) + continue; +#if !SPC5_CAN_USE_FILTERS + while (canReceive(cip->canp, CAN_ANY_MAILBOX, + &rxmsg, TIME_IMMEDIATE) == RDY_OK) { + /* Process message.*/ + palTogglePad(PORT_E, cip->led); + } +#else + while (canReceive(cip->canp, rxFlag, + &rxmsg, TIME_IMMEDIATE) == RDY_OK) { + /* Process message.*/ + palTogglePad(PORT_E, cip->led); + } +#endif + } + chEvtUnregister(&CAND5.rxfull_event, &el); + return 0; +} + +/* + * Transmitter thread. + */ +static WORKING_AREA(can_tx_wa, 256); +static msg_t can_tx(void * p) { + CANTxFrame txmsg; + + (void)p; + chRegSetThreadName("transmitter"); + txmsg.IDE = CAN_IDE_EXT; + txmsg.EID = 0x01234567; + txmsg.RTR = CAN_RTR_DATA; + txmsg.LENGTH = 8; + txmsg.data32[0] = 0x55AA55AA; + txmsg.data32[1] = 0x00FF00FF; + + while (!chThdShouldTerminate()) { + canTransmit(&CAND5, 1, &txmsg, MS2ST(100)); + palTogglePad(PORT_E, PE_LED2); + chThdSleepMilliseconds(500); + } + return 0; +} + +/* + * Application entry point. + */ +int main(void) { + + /* + * System initializations. + * - HAL initialization, this also initializes the configured device drivers + * and performs the board-specific initializations. + * - Kernel initialization, the main() function becomes a thread and the + * RTOS is active. + */ + halInit(); + chSysInit(); + + /* + * Activates the CAN driver 1. + */ + canStart(&CAND5, &cancfg); + + /* + * Starting the transmitter and receiver threads. + */ + chThdCreateStatic(can_rx_wa, sizeof(can_rx_wa), NORMALPRIO + 7, + can_rx, (void *)&can1); + chThdCreateStatic(can_tx_wa, sizeof(can_tx_wa), NORMALPRIO + 7, + can_tx, NULL); + + /* + * Normal main() thread activity, in this demo it does nothing. + */ + while (TRUE) { + chThdSleepMilliseconds(500); + } + return 0; +} + diff --git a/testhal/SPC560BCxx/CAN/mcuconf.h b/testhal/SPC560BCxx/CAN/mcuconf.h new file mode 100644 index 000000000..dc667bb74 --- /dev/null +++ b/testhal/SPC560BCxx/CAN/mcuconf.h @@ -0,0 +1,223 @@ +/* + * Licensed under ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * SPC560B/Cxx drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the whole + * driver is enabled in halconf.h. + * + * IRQ priorities: + * 1...15 Lowest...Highest. + */ + +#define SPC560BCxx_MCUCONF + +/* + * HAL driver system settings. + */ +#define SPC5_NO_INIT FALSE +#define SPC5_ALLOW_OVERCLOCK FALSE +#define SPC5_DISABLE_WATCHDOG TRUE +#define SPC5_FMPLL0_IDF_VALUE 1 +#define SPC5_FMPLL0_NDIV_VALUE 32 +#define SPC5_FMPLL0_ODF SPC5_FMPLL_ODF_DIV4 +#define SPC5_XOSCDIV_VALUE 1 +#define SPC5_IRCDIV_VALUE 1 +#define SPC5_PERIPHERAL1_CLK_DIV_VALUE 2 +#define SPC5_PERIPHERAL2_CLK_DIV_VALUE 2 +#define SPC5_PERIPHERAL3_CLK_DIV_VALUE 2 +#define SPC5_ME_ME_BITS (SPC5_ME_ME_RUN1 | \ + SPC5_ME_ME_RUN2 | \ + SPC5_ME_ME_RUN3 | \ + SPC5_ME_ME_HALT0 | \ + SPC5_ME_ME_STOP0 | \ + SPC5_ME_ME_STANDBY0) +#define SPC5_ME_TEST_MC_BITS (SPC5_ME_MC_SYSCLK_IRC | \ + SPC5_ME_MC_IRCON | \ + SPC5_ME_MC_XOSC0ON | \ + SPC5_ME_MC_PLL0ON | \ + SPC5_ME_MC_CFLAON_NORMAL | \ + SPC5_ME_MC_DFLAON_NORMAL | \ + SPC5_ME_MC_MVRON) +#define SPC5_ME_SAFE_MC_BITS (SPC5_ME_MC_PDO) +#define SPC5_ME_DRUN_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \ + SPC5_ME_MC_IRCON | \ + SPC5_ME_MC_XOSC0ON | \ + SPC5_ME_MC_PLL0ON | \ + SPC5_ME_MC_CFLAON_NORMAL | \ + SPC5_ME_MC_DFLAON_NORMAL | \ + SPC5_ME_MC_MVRON) +#define SPC5_ME_RUN0_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \ + SPC5_ME_MC_IRCON | \ + SPC5_ME_MC_XOSC0ON | \ + SPC5_ME_MC_PLL0ON | \ + SPC5_ME_MC_CFLAON_NORMAL | \ + SPC5_ME_MC_DFLAON_NORMAL | \ + SPC5_ME_MC_MVRON) +#define SPC5_ME_RUN1_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \ + SPC5_ME_MC_IRCON | \ + SPC5_ME_MC_XOSC0ON | \ + SPC5_ME_MC_PLL0ON | \ + SPC5_ME_MC_CFLAON_NORMAL | \ + SPC5_ME_MC_DFLAON_NORMAL | \ + SPC5_ME_MC_MVRON) +#define SPC5_ME_RUN2_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \ + SPC5_ME_MC_IRCON | \ + SPC5_ME_MC_XOSC0ON | \ + SPC5_ME_MC_PLL0ON | \ + SPC5_ME_MC_CFLAON_NORMAL | \ + SPC5_ME_MC_DFLAON_NORMAL | \ + SPC5_ME_MC_MVRON) +#define SPC5_ME_RUN3_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \ + SPC5_ME_MC_IRCON | \ + SPC5_ME_MC_XOSC0ON | \ + SPC5_ME_MC_PLL0ON | \ + SPC5_ME_MC_CFLAON_NORMAL | \ + SPC5_ME_MC_DFLAON_NORMAL | \ + SPC5_ME_MC_MVRON) +#define SPC5_ME_HALT0_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \ + SPC5_ME_MC_IRCON | \ + SPC5_ME_MC_XOSC0ON | \ + SPC5_ME_MC_PLL0ON | \ + SPC5_ME_MC_CFLAON_NORMAL | \ + SPC5_ME_MC_DFLAON_NORMAL | \ + SPC5_ME_MC_MVRON) +#define SPC5_ME_STOP0_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \ + SPC5_ME_MC_IRCON | \ + SPC5_ME_MC_XOSC0ON | \ + SPC5_ME_MC_PLL0ON | \ + SPC5_ME_MC_CFLAON_NORMAL | \ + SPC5_ME_MC_DFLAON_NORMAL | \ + SPC5_ME_MC_MVRON) +#define SPC5_ME_STANDBY0_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \ + SPC5_ME_MC_IRCON | \ + SPC5_ME_MC_XOSC0ON | \ + SPC5_ME_MC_PLL0ON | \ + SPC5_ME_MC_CFLAON_NORMAL | \ + SPC5_ME_MC_DFLAON_NORMAL | \ + SPC5_ME_MC_MVRON) +#define SPC5_ME_RUN_PC0_BITS 0 +#define SPC5_ME_RUN_PC1_BITS (SPC5_ME_RUN_PC_TEST | \ + SPC5_ME_RUN_PC_SAFE | \ + SPC5_ME_RUN_PC_DRUN | \ + SPC5_ME_RUN_PC_RUN0 | \ + SPC5_ME_RUN_PC_RUN1 | \ + SPC5_ME_RUN_PC_RUN2 | \ + SPC5_ME_RUN_PC_RUN3) +#define SPC5_ME_RUN_PC2_BITS (SPC5_ME_RUN_PC_DRUN | \ + SPC5_ME_RUN_PC_RUN0 | \ + SPC5_ME_RUN_PC_RUN1 | \ + SPC5_ME_RUN_PC_RUN2 | \ + SPC5_ME_RUN_PC_RUN3) +#define SPC5_ME_RUN_PC3_BITS (SPC5_ME_RUN_PC_RUN0 | \ + SPC5_ME_RUN_PC_RUN1 | \ + SPC5_ME_RUN_PC_RUN2 | \ + SPC5_ME_RUN_PC_RUN3) +#define SPC5_ME_RUN_PC4_BITS (SPC5_ME_RUN_PC_RUN0 | \ + SPC5_ME_RUN_PC_RUN1 | \ + SPC5_ME_RUN_PC_RUN2 | \ + SPC5_ME_RUN_PC_RUN3) +#define SPC5_ME_RUN_PC5_BITS (SPC5_ME_RUN_PC_RUN0 | \ + SPC5_ME_RUN_PC_RUN1 | \ + SPC5_ME_RUN_PC_RUN2 | \ + SPC5_ME_RUN_PC_RUN3) +#define SPC5_ME_RUN_PC6_BITS (SPC5_ME_RUN_PC_RUN0 | \ + SPC5_ME_RUN_PC_RUN1 | \ + SPC5_ME_RUN_PC_RUN2 | \ + SPC5_ME_RUN_PC_RUN3) +#define SPC5_ME_RUN_PC7_BITS (SPC5_ME_RUN_PC_RUN0 | \ + SPC5_ME_RUN_PC_RUN1 | \ + SPC5_ME_RUN_PC_RUN2 | \ + SPC5_ME_RUN_PC_RUN3) +#define SPC5_ME_LP_PC0_BITS 0 +#define SPC5_ME_LP_PC1_BITS (SPC5_ME_LP_PC_HALT0 | \ + SPC5_ME_LP_PC_STOP0 | \ + SPC5_ME_LP_PC_STANDBY0) +#define SPC5_ME_LP_PC2_BITS (SPC5_ME_LP_PC_HALT0) +#define SPC5_ME_LP_PC3_BITS (SPC5_ME_LP_PC_STOP0) +#define SPC5_ME_LP_PC4_BITS (SPC5_ME_LP_PC_HALT0 | \ + SPC5_ME_LP_PC_STOP0) +#define SPC5_ME_LP_PC5_BITS (SPC5_ME_LP_PC_HALT0 | \ + SPC5_ME_LP_PC_STOP0) +#define SPC5_ME_LP_PC6_BITS (SPC5_ME_LP_PC_HALT0 | \ + SPC5_ME_LP_PC_STOP0) +#define SPC5_ME_LP_PC7_BITS (SPC5_ME_LP_PC_HALT0 | \ + SPC5_ME_LP_PC_STOP0) +#define SPC5_PIT0_IRQ_PRIORITY 4 +#define SPC5_CLOCK_FAILURE_HOOK() chSysHalt() + +/* + * SERIAL driver system settings. + */ +#define SPC5_SERIAL_USE_LINFLEX0 TRUE +#define SPC5_SERIAL_USE_LINFLEX1 TRUE +#define SPC5_SERIAL_LINFLEX0_PRIORITY 8 +#define SPC5_SERIAL_LINFLEX1_PRIORITY 8 +#define SPC5_SERIAL_LINFLEX0_START_PCTL (SPC5_ME_PCTL_RUN(1) | \ + SPC5_ME_PCTL_LP(2)) +#define SPC5_SERIAL_LINFLEX0_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \ + SPC5_ME_PCTL_LP(0)) +#define SPC5_SERIAL_LINFLEX1_START_PCTL (SPC5_ME_PCTL_RUN(1) | \ + SPC5_ME_PCTL_LP(2)) +#define SPC5_SERIAL_LINFLEX1_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \ + SPC5_ME_PCTL_LP(0)) + +/* + * CAN driver system settings. + */ +#define SPC5_CAN_USE_FILTERS TRUE + +#define SPC5_CAN_USE_FLEXCAN0 FALSE +#define SPC5_CAN_FLEXCAN0_PRIORITY 11 +#define SPC5_CAN_FLEXCAN0_START_PCTL (SPC5_ME_PCTL_RUN(1) | \ + SPC5_ME_PCTL_LP(2)) +#define SPC5_CAN_FLEXCAN0_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \ + SPC5_ME_PCTL_LP(0)) + +#define SPC5_CAN_USE_FLEXCAN1 FALSE +#define SPC5_CAN_FLEXCAN1_PRIORITY 11 +#define SPC5_CAN_FLEXCAN1_START_PCTL (SPC5_ME_PCTL_RUN(1) | \ + SPC5_ME_PCTL_LP(2)) +#define SPC5_CAN_FLEXCAN1_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \ + SPC5_ME_PCTL_LP(0)) + +#define SPC5_CAN_USE_FLEXCAN2 FALSE +#define SPC5_CAN_FLEXCAN2_PRIORITY 11 +#define SPC5_CAN_FLEXCAN2_START_PCTL (SPC5_ME_PCTL_RUN(1) | \ + SPC5_ME_PCTL_LP(2)) +#define SPC5_CAN_FLEXCAN2_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \ + SPC5_ME_PCTL_LP(0)) + +#define SPC5_CAN_USE_FLEXCAN3 FALSE +#define SPC5_CAN_FLEXCAN3_PRIORITY 11 +#define SPC5_CAN_FLEXCAN3_START_PCTL (SPC5_ME_PCTL_RUN(1) | \ + SPC5_ME_PCTL_LP(2)) +#define SPC5_CAN_FLEXCAN3_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \ + SPC5_ME_PCTL_LP(0)) + +#define SPC5_CAN_USE_FLEXCAN4 TRUE +#define SPC5_CAN_FLEXCAN4_PRIORITY 11 +#define SPC5_CAN_FLEXCAN4_START_PCTL (SPC5_ME_PCTL_RUN(1) | \ + SPC5_ME_PCTL_LP(2)) +#define SPC5_CAN_FLEXCAN4_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \ + SPC5_ME_PCTL_LP(0)) + +#define SPC5_CAN_USE_FLEXCAN5 FALSE +#define SPC5_CAN_FLEXCAN5_PRIORITY 11 +#define SPC5_CAN_FLEXCAN5_START_PCTL (SPC5_ME_PCTL_RUN(1) | \ + SPC5_ME_PCTL_LP(2)) +#define SPC5_CAN_FLEXCAN5_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \ + SPC5_ME_PCTL_LP(0)) diff --git a/testhal/SPC560BCxx/CAN/readme.txt b/testhal/SPC560BCxx/CAN/readme.txt new file mode 100644 index 000000000..78f7e7cd5 --- /dev/null +++ b/testhal/SPC560BCxx/CAN/readme.txt @@ -0,0 +1,27 @@ +***************************************************************************** +** ChibiOS/RT HAL - CAN drivers demo for SPC560BCxx. ** +***************************************************************************** + +** TARGET ** + +The demo runs on an STMicroelectronics SPC560BCxx microcontroller installed on +XPC56xx EVB Motherboard. + +** The Demo ** + +The application demonstrates the use of the SPC560BCxx CAN drivers. + +** Board Setup ** + +- Enable LED1 and LED2. + +** Build Procedure ** + +The demo has been tested using HighTec compiler. + +** Notes ** + +Some files used by the demo are not part of ChibiOS/RT but are copyright of +ST Microelectronics and are licensed under a different license. + + http://www.st.com diff --git a/testhal/SPC560Pxx/CAN/.cproject b/testhal/SPC560Pxx/CAN/.cproject new file mode 100644 index 000000000..18c26cafe --- /dev/null +++ b/testhal/SPC560Pxx/CAN/.cproject @@ -0,0 +1,51 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/testhal/SPC560Pxx/CAN/.project b/testhal/SPC560Pxx/CAN/.project new file mode 100644 index 000000000..4c2d806c5 --- /dev/null +++ b/testhal/SPC560Pxx/CAN/.project @@ -0,0 +1,38 @@ + + + SPC560Pxx-PWM-ICU + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + board + 2 + CHIBIOS/boards/ST_EVB_SPC560P + + + os + 2 + CHIBIOS/os + + + diff --git a/testhal/SPC560Pxx/CAN/Makefile b/testhal/SPC560Pxx/CAN/Makefile new file mode 100644 index 000000000..33ab47686 --- /dev/null +++ b/testhal/SPC560Pxx/CAN/Makefile @@ -0,0 +1,140 @@ +############################################################################## +# This file is automatically generated and can be overwritten, do no change +# this file manually. +############################################################################## +# Build global options +# NOTE: Can be overridden externally. +# + +# Compiler options here. +ifeq ($(USE_OPT),) + USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16 +endif + +# C specific options here (added to USE_OPT). +ifeq ($(USE_COPT),) + USE_COPT = +endif + +# C++ specific options here (added to USE_OPT). +ifeq ($(USE_CPPOPT),) + USE_CPPOPT = -fno-rtti +endif + +# Enable this if you want the linker to remove unused code and data. +ifeq ($(USE_LINK_GC),) + USE_LINK_GC = yes +endif + +# If enabled, this option allows to compile the application in VLE mode. +ifeq ($(USE_VLE),) + USE_VLE = yes +endif + +# Enable this if you want to see the full log while compiling. +ifeq ($(USE_VERBOSE_COMPILE),) + USE_VERBOSE_COMPILE = no +endif + +# +# Build global options +############################################################################## + +############################################################################## +# Project, sources and paths +# + +# Define project name here +PROJECT = out + +# Imported source files +include components/components.mak + +# Checks if there is a user mak file in the project directory. +ifneq ($(wildcard user.mak),) + include user.mak +endif + +# Define linker script file here +LDSCRIPT= application.ld + +# C sources here. +CSRC = $(LIB_C_SRC) \ + $(APP_C_SRC) \ + $(U_C_SRC) \ + ./components/components.c \ + ./main.c + +# C++ sources here. +CPPSRC = $(LIB_CPP_SRC) \ + $(APP_CPP_SRC) \ + $(U_CPP_SRC) + +# List ASM source files here +ASMSRC = $(LIB_ASM_SRC) \ + $(APP_ASM_SRC) \ + $(U_ASM_SRC) + +INCDIR = $(LIB_INCLUDES) \ + $(APP_INCLUDES) \ + ./components + +# +# Project, sources and paths +############################################################################## + +############################################################################## +# Compiler settings +# + +#MCU = e500mc -meabi -msdata=none -mnew-mnemonics -mregnames +MCU = e200zx -meabi -msdata=none -mnew-mnemonics -mregnames + +TRGT = ppc-vle- +CC = $(TRGT)gcc +CPPC = $(TRGT)g++ +# Enable loading with g++ only if you need C++ runtime support. +# NOTE: You can use C++ even without C++ support if you are careful. C++ +# runtime support makes code size explode. +LD = $(TRGT)gcc +#LD = $(TRGT)g++ +CP = $(TRGT)objcopy +AS = $(TRGT)gcc -x assembler-with-cpp +OD = $(TRGT)objdump +HEX = $(CP) -O ihex +BIN = $(CP) -O binary + +# Define C warning options here +CWARN = -Wall -Wextra -Wstrict-prototypes + +# Define C++ warning options here +CPPWARN = -Wall -Wextra + +# +# Compiler settings +############################################################################## + +############################################################################## +# Start of default section +# + +# List all default C defines here, like -D_DEBUG=1 +DDEFS = -DSPC560P50L5 + +# List all default ASM defines here, like -D_DEBUG=1 +DADEFS = + +# List all default directories to look for include files here +DINCDIR = + +# List the default directory to look for the libraries here +DLIBDIR = + +# List all default libraries here +DLIBS = + +# +# End of default section +############################################################################## + +include C:/SPC5Studio/eclipse/plugins/com.st.tools.spc5.components.platform.spc560pxx_1.0.0.201302201417/component/lib/rsc/rules.mk diff --git a/testhal/SPC560Pxx/CAN/chconf.h b/testhal/SPC560Pxx/CAN/chconf.h new file mode 100644 index 000000000..8800269d4 --- /dev/null +++ b/testhal/SPC560Pxx/CAN/chconf.h @@ -0,0 +1,529 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef _CHCONF_H_ +#define _CHCONF_H_ + +/*===========================================================================*/ +/** + * @name Kernel parameters and options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#if !defined(CH_FREQUENCY) || defined(__DOXYGEN__) +#define CH_FREQUENCY 1000 +#endif + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + */ +#if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__) +#define CH_TIME_QUANTUM 20 +#endif + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_USE_MEMCORE. + */ +#if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__) +#define CH_MEMCORE_SIZE 0 +#endif + +/** + * @brief Idle thread automatic spawn suppression. + * @details When this option is activated the function @p chSysInit() + * does not spawn the idle thread automatically. The application has + * then the responsibility to do one of the following: + * - Spawn a custom idle thread at priority @p IDLEPRIO. + * - Change the main() thread priority to @p IDLEPRIO then enter + * an endless loop. In this scenario the @p main() thread acts as + * the idle thread. + * . + * @note Unless an idle thread is spawned the @p main() thread must not + * enter a sleep state. + */ +#if !defined(CH_NO_IDLE_THREAD) || defined(__DOXYGEN__) +#define CH_NO_IDLE_THREAD FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Performance options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__) +#define CH_OPTIMIZE_SPEED TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Subsystem options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_REGISTRY) || defined(__DOXYGEN__) +#define CH_USE_REGISTRY TRUE +#endif + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__) +#define CH_USE_WAITEXIT TRUE +#endif + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES TRUE +#endif + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES_PRIORITY FALSE +#endif + +/** + * @brief Atomic semaphore API. + * @details If enabled then the semaphores the @p chSemSignalWait() API + * is included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__) +#define CH_USE_SEMSW TRUE +#endif + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__) +#define CH_USE_MUTEXES TRUE +#endif + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MUTEXES. + */ +#if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS TRUE +#endif + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_CONDVARS. + */ +#if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS_TIMEOUT TRUE +#endif + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__) +#define CH_USE_EVENTS TRUE +#endif + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_EVENTS. + */ +#if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_EVENTS_TIMEOUT TRUE +#endif + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES TRUE +#endif + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_MESSAGES. + */ +#if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES_PRIORITY FALSE +#endif + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__) +#define CH_USE_MAILBOXES TRUE +#endif + +/** + * @brief I/O Queues APIs. + * @details If enabled then the I/O queues APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__) +#define CH_USE_QUEUES TRUE +#endif + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__) +#define CH_USE_MEMCORE TRUE +#endif + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MEMCORE and either @p CH_USE_MUTEXES or + * @p CH_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) +#define CH_USE_HEAP TRUE +#endif + +/** + * @brief C-runtime allocator. + * @details If enabled the the heap allocator APIs just wrap the C-runtime + * @p malloc() and @p free() functions. + * + * @note The default is @p FALSE. + * @note Requires @p CH_USE_HEAP. + * @note The C-runtime may or may not require @p CH_USE_MEMCORE, see the + * appropriate documentation. + */ +#if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__) +#define CH_USE_MALLOC_HEAP FALSE +#endif + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__) +#define CH_USE_MEMPOOLS TRUE +#endif + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_WAITEXIT. + * @note Requires @p CH_USE_HEAP and/or @p CH_USE_MEMPOOLS. + */ +#if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__) +#define CH_USE_DYNAMIC TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Debug options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Debug option, system state check. + * @details If enabled the correct call protocol for system APIs is checked + * at runtime. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_SYSTEM_STATE_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_SYSTEM_STATE_CHECK FALSE +#endif + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_CHECKS FALSE +#endif + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_ASSERTS FALSE +#endif + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the context switch circular trace buffer is + * activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_TRACE FALSE +#endif + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_STACK_CHECK FALSE +#endif + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__) +#define CH_DBG_FILL_THREADS FALSE +#endif + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p Thread structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p TRUE. + * @note This debug option is defaulted to TRUE because it is required by + * some test cases into the test suite. + */ +#if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__) +#define CH_DBG_THREADS_PROFILING TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel hooks + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads descriptor structure extension. + * @details User fields added to the end of the @p Thread structure. + */ +#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) +#define THREAD_EXT_FIELDS \ + +#endif + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p chThdInit() API. + * + * @note It is invoked from within @p chThdInit() and implicitly from all + * the threads creation APIs. + */ +#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_INIT_HOOK(tp) { \ +} +#endif + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + * + * @note It is inserted into lock zone. + * @note It is also invoked when the threads simply return in order to + * terminate. + */ +#if !defined(THREAD_EXT_EXIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_EXIT_HOOK(tp) { \ +} +#endif + +/** + * @brief Context switch hook. + * @details This hook is invoked just before switching between threads. + */ +#if !defined(THREAD_CONTEXT_SWITCH_HOOK) || defined(__DOXYGEN__) +#define THREAD_CONTEXT_SWITCH_HOOK(ntp, otp) { \ +} +#endif + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) +#define IDLE_LOOP_HOOK() { \ +} +#endif + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#if !defined(SYSTEM_TICK_EVENT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_TICK_EVENT_HOOK() { \ +} +#endif + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#if !defined(SYSTEM_HALT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_HALT_HOOK() { \ +} +#endif + +/** @} */ + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + +#endif /* _CHCONF_H_ */ + +/** @} */ diff --git a/testhal/SPC560Pxx/CAN/halconf.h b/testhal/SPC560Pxx/CAN/halconf.h new file mode 100644 index 000000000..c316bb385 --- /dev/null +++ b/testhal/SPC560Pxx/CAN/halconf.h @@ -0,0 +1,371 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * + * @addtogroup HAL_CONF + * @{ + */ + +#ifndef _HALCONF_H_ +#define _HALCONF_H_ + +#include "mcuconf.h" + +/** + * @name Drivers enable switches + */ +/** + * @brief Enables the TM subsystem. + */ +#if !defined(HAL_USE_TM) || defined(__DOXYGEN__) +#define HAL_USE_TM FALSE +#endif + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC FALSE +#endif + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN TRUE +#endif + +/** + * @brief Enables the EXT subsystem. + */ +#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__) +#define HAL_USE_EXT FALSE +#endif + +/** + * @brief Enables the GPT subsystem. + */ +#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) +#define HAL_USE_GPT FALSE +#endif + +/** + * @brief Enables the I2C subsystem. + */ +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C FALSE +#endif + +/** + * @brief Enables the ICU subsystem. + */ +#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) +#define HAL_USE_ICU FALSE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM FALSE +#endif + +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC FALSE +#endif + +/** + * @brief Enables the SDC subsystem. + */ +#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) +#define HAL_USE_SDC FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL TRUE +#endif + +/** + * @brief Enables the SERIAL over USB subsystem. + */ +#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL_USB FALSE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI FALSE +#endif + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART FALSE +#endif + +/** + * @brief Enables the USB subsystem. + */ +#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) +#define HAL_USE_USB FALSE +#endif +/** @} */ + +/*===========================================================================*/ +/** + * @name ADC driver related setting + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION FALSE +#endif +/** @} */ + +/*===========================================================================*/ +/** + * @name CAN driver related setting + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Sleep mode related APIs inclusion switch. + */ +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE FALSE +#endif +/** @} */ + +/*===========================================================================*/ +/** + * @name I2C driver related setting + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Enables the mutual exclusion APIs on the I2C bus. + */ +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION FALSE +#endif +/** @} */ + +/*===========================================================================*/ +/** + * @name MAC driver related setting + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) +#define MAC_USE_ZERO_COPY FALSE +#endif + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif +/** @} */ + +/*===========================================================================*/ +/** + * @name MMC_SPI driver related setting + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + * This option is recommended also if the SPI driver does not + * use a DMA channel and heavily loads the CPU. + */ +#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) +#define MMC_NICE_WAITING TRUE +#endif +/** @} */ + +/*===========================================================================*/ +/** + * @name SDC driver related setting + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Number of initialization attempts before rejecting the card. + * @note Attempts are performed at 10mS intervals. + */ +#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) +#define SDC_INIT_RETRY 1 +#endif + +/** + * @brief Include support for MMC cards. + * @note MMC support is not yet implemented so this option must be kept + * at @p FALSE. + */ +#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) +#define SDC_MMC_SUPPORT FALSE +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + */ +#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) +#define SDC_NICE_WAITING TRUE +#endif +/** @} */ + +/*===========================================================================*/ +/** + * @name SERIAL driver related setting + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 64 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif +/** @} */ + +/*===========================================================================*/ +/** + * @name SERIAL_USB driver related setting + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Serial over USB buffers size. + * @details Configuration parameter, the buffer size must be a multiple of + * the USB data endpoint maximum packet size. + * @note The default is 64 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_USB_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_USB_BUFFERS_SIZE 64 +#endif +/** @} */ + +/*===========================================================================*/ +/** + * @name SPI driver related setting + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION FALSE +#endif +/** @} */ + +#endif /* _HALCONF_H_ */ + +/** @} */ diff --git a/testhal/SPC560Pxx/CAN/main.c b/testhal/SPC560Pxx/CAN/main.c new file mode 100644 index 000000000..a56000ff9 --- /dev/null +++ b/testhal/SPC560Pxx/CAN/main.c @@ -0,0 +1,149 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include "ch.h" +#include "hal.h" + +struct can_instance { + CANDriver *canp; + uint32_t led; +}; + +static const struct can_instance can1 = {&CAND1, PD_LED1}; + +/* + * Internal loopback mode, 1MBaud. + * See chapter 25 on the SPC5 reference manual. + */ +static const CANConfig cancfg = { + CAN_MCR_WRN_EN, + CAN_CTRL_LPB | CAN_CTRL_PROPSEG(2) | CAN_CTRL_PSEG2(7) | + CAN_CTRL_PSEG1(3) | CAN_CTRL_PRESDIV(3) +#if SPC5_CAN_USE_FILTERS + , + { + {0, 0x00000001}, + {1, 0x01234567}, + {0, 0x00000000}, + {0, 0x00000003}, + {0, 0x00000004}, + {0, 0x00000005}, + {0, 0x00000006}, + {0, 0x00000007} + } +#endif +}; + +#if SPC5_CAN_USE_FILTERS +flagsmask_t rxFlag; +#endif + +/* + * Receiver thread. + */ +static WORKING_AREA(can_rx_wa, 256); +static msg_t can_rx(void *p) { + struct can_instance *cip = p; + EventListener el; + CANRxFrame rxmsg; + (void)p; + chRegSetThreadName("receiver"); + chEvtRegister(&cip->canp->rxfull_event, &el, 0); +#if SPC5_CAN_USE_FILTERS + rxFlag = chEvtGetAndClearFlagsI(&el); +#endif + while(!chThdShouldTerminate()) { + if (chEvtWaitAnyTimeout(ALL_EVENTS, MS2ST(100)) == 0) + continue; +#if !SPC5_CAN_USE_FILTERS + while (canReceive(cip->canp, CAN_ANY_MAILBOX, + &rxmsg, TIME_IMMEDIATE) == RDY_OK) { + /* Process message.*/ + palTogglePad(PORT_D, cip->led); + } +#else + while (canReceive(cip->canp, rxFlag, + &rxmsg, TIME_IMMEDIATE) == RDY_OK) { + /* Process message.*/ + palTogglePad(PORT_D, cip->led); + } +#endif + } + chEvtUnregister(&CAND1.rxfull_event, &el); + return 0; +} + +/* + * Transmitter thread. + */ +static WORKING_AREA(can_tx_wa, 256); +static msg_t can_tx(void * p) { + CANTxFrame txmsg; + + (void)p; + chRegSetThreadName("transmitter"); + txmsg.IDE = CAN_IDE_EXT; + txmsg.EID = 0x01234567; + txmsg.RTR = CAN_RTR_DATA; + txmsg.LENGTH = 8; + txmsg.data32[0] = 0x55AA55AA; + txmsg.data32[1] = 0x00FF00FF; + + while (!chThdShouldTerminate()) { + canTransmit(&CAND1, 1, &txmsg, MS2ST(100)); + palTogglePad(PORT_D, PD_LED2); + chThdSleepMilliseconds(500); + } + return 0; +} + +/* + * Application entry point. + */ +int main(void) { + + /* + * System initializations. + * - HAL initialization, this also initializes the configured device drivers + * and performs the board-specific initializations. + * - Kernel initialization, the main() function becomes a thread and the + * RTOS is active. + */ + halInit(); + chSysInit(); + + /* + * Activates the CAN driver 1. + */ + canStart(&CAND1, &cancfg); + + /* + * Starting the transmitter and receiver threads. + */ + chThdCreateStatic(can_rx_wa, sizeof(can_rx_wa), NORMALPRIO + 7, + can_rx, (void *)&can1); + chThdCreateStatic(can_tx_wa, sizeof(can_tx_wa), NORMALPRIO + 7, + can_tx, NULL); + + /* + * Normal main() thread activity, in this demo it does nothing. + */ + while (TRUE) { + chThdSleepMilliseconds(500); + } + return 0; +} + diff --git a/testhal/SPC560Pxx/CAN/mcuconf.h b/testhal/SPC560Pxx/CAN/mcuconf.h new file mode 100644 index 000000000..bdd11f6ae --- /dev/null +++ b/testhal/SPC560Pxx/CAN/mcuconf.h @@ -0,0 +1,190 @@ +/* + * Licensed under ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * SPC560Pxx drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the whole + * driver is enabled in halconf.h. + * + * IRQ priorities: + * 1...15 Lowest...Highest. + */ + +#define SPC560Pxx_MCUCONF + +/* + * HAL driver system settings. + */ +#define SPC5_NO_INIT FALSE +#define SPC5_ALLOW_OVERCLOCK FALSE +#define SPC5_DISABLE_WATCHDOG TRUE +#define SPC5_FMPLL0_IDF_VALUE 5 +#define SPC5_FMPLL0_NDIV_VALUE 32 +#define SPC5_FMPLL0_ODF SPC5_FMPLL_ODF_DIV4 +#define SPC5_FMPLL1_IDF_VALUE 5 +#define SPC5_FMPLL1_NDIV_VALUE 60 +#define SPC5_FMPLL1_ODF SPC5_FMPLL_ODF_DIV4 +#define SPC5_AUX0CLK_SRC SPC5_CGM_SS_FMPLL1 +#define SPC5_MCONTROL_DIVIDER_VALUE 2 +#define SPC5_FMPLL1_CLK_DIVIDER_VALUE 2 +#define SPC5_AUX2CLK_SRC SPC5_CGM_SS_FMPLL1 +#define SPC5_SP_CLK_DIVIDER_VALUE 2 +#define SPC5_AUX3CLK_SRC SPC5_CGM_SS_FMPLL1 +#define SPC5_FR_CLK_DIVIDER_VALUE 2 +#define SPC5_ME_ME_BITS (SPC5_ME_ME_RUN1 | \ + SPC5_ME_ME_RUN2 | \ + SPC5_ME_ME_RUN3 | \ + SPC5_ME_ME_HALT0 | \ + SPC5_ME_ME_STOP0) +#define SPC5_ME_TEST_MC_BITS (SPC5_ME_MC_SYSCLK_IRC | \ + SPC5_ME_MC_IRCON | \ + SPC5_ME_MC_XOSC0ON | \ + SPC5_ME_MC_PLL0ON | \ + SPC5_ME_MC_PLL1ON | \ + SPC5_ME_MC_CFLAON_NORMAL | \ + SPC5_ME_MC_DFLAON_NORMAL | \ + SPC5_ME_MC_MVRON) +#define SPC5_ME_SAFE_MC_BITS (SPC5_ME_MC_PDO) +#define SPC5_ME_DRUN_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \ + SPC5_ME_MC_IRCON | \ + SPC5_ME_MC_XOSC0ON | \ + SPC5_ME_MC_PLL0ON | \ + SPC5_ME_MC_PLL1ON | \ + SPC5_ME_MC_CFLAON_NORMAL | \ + SPC5_ME_MC_DFLAON_NORMAL | \ + SPC5_ME_MC_MVRON) +#define SPC5_ME_RUN0_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \ + SPC5_ME_MC_IRCON | \ + SPC5_ME_MC_XOSC0ON | \ + SPC5_ME_MC_PLL0ON | \ + SPC5_ME_MC_PLL1ON | \ + SPC5_ME_MC_CFLAON_NORMAL | \ + SPC5_ME_MC_DFLAON_NORMAL | \ + SPC5_ME_MC_MVRON) +#define SPC5_ME_RUN1_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \ + SPC5_ME_MC_IRCON | \ + SPC5_ME_MC_XOSC0ON | \ + SPC5_ME_MC_PLL0ON | \ + SPC5_ME_MC_PLL1ON | \ + SPC5_ME_MC_CFLAON_NORMAL | \ + SPC5_ME_MC_DFLAON_NORMAL | \ + SPC5_ME_MC_MVRON) +#define SPC5_ME_RUN2_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \ + SPC5_ME_MC_IRCON | \ + SPC5_ME_MC_XOSC0ON | \ + SPC5_ME_MC_PLL0ON | \ + SPC5_ME_MC_PLL1ON | \ + SPC5_ME_MC_CFLAON_NORMAL | \ + SPC5_ME_MC_DFLAON_NORMAL | \ + SPC5_ME_MC_MVRON) +#define SPC5_ME_RUN3_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \ + SPC5_ME_MC_IRCON | \ + SPC5_ME_MC_XOSC0ON | \ + SPC5_ME_MC_PLL0ON | \ + SPC5_ME_MC_PLL1ON | \ + SPC5_ME_MC_CFLAON_NORMAL | \ + SPC5_ME_MC_DFLAON_NORMAL | \ + SPC5_ME_MC_MVRON) +#define SPC5_ME_HALT0_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \ + SPC5_ME_MC_IRCON | \ + SPC5_ME_MC_XOSC0ON | \ + SPC5_ME_MC_PLL0ON | \ + SPC5_ME_MC_PLL1ON | \ + SPC5_ME_MC_CFLAON_NORMAL | \ + SPC5_ME_MC_DFLAON_NORMAL | \ + SPC5_ME_MC_MVRON) +#define SPC5_ME_STOP0_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \ + SPC5_ME_MC_IRCON | \ + SPC5_ME_MC_XOSC0ON | \ + SPC5_ME_MC_PLL0ON | \ + SPC5_ME_MC_PLL1ON | \ + SPC5_ME_MC_CFLAON_NORMAL | \ + SPC5_ME_MC_DFLAON_NORMAL | \ + SPC5_ME_MC_MVRON) +#define SPC5_ME_RUN_PC3_BITS (SPC5_ME_RUN_PC_RUN0 | \ + SPC5_ME_RUN_PC_RUN1 | \ + SPC5_ME_RUN_PC_RUN2 | \ + SPC5_ME_RUN_PC_RUN3) +#define SPC5_ME_RUN_PC4_BITS (SPC5_ME_RUN_PC_RUN0 | \ + SPC5_ME_RUN_PC_RUN1 | \ + SPC5_ME_RUN_PC_RUN2 | \ + SPC5_ME_RUN_PC_RUN3) +#define SPC5_ME_RUN_PC5_BITS (SPC5_ME_RUN_PC_RUN0 | \ + SPC5_ME_RUN_PC_RUN1 | \ + SPC5_ME_RUN_PC_RUN2 | \ + SPC5_ME_RUN_PC_RUN3) +#define SPC5_ME_RUN_PC6_BITS (SPC5_ME_RUN_PC_RUN0 | \ + SPC5_ME_RUN_PC_RUN1 | \ + SPC5_ME_RUN_PC_RUN2 | \ + SPC5_ME_RUN_PC_RUN3) +#define SPC5_ME_RUN_PC7_BITS (SPC5_ME_RUN_PC_RUN0 | \ + SPC5_ME_RUN_PC_RUN1 | \ + SPC5_ME_RUN_PC_RUN2 | \ + SPC5_ME_RUN_PC_RUN3) +#define SPC5_ME_LP_PC4_BITS (SPC5_ME_LP_PC_HALT0 | \ + SPC5_ME_LP_PC_STOP0) +#define SPC5_ME_LP_PC5_BITS (SPC5_ME_LP_PC_HALT0 | \ + SPC5_ME_LP_PC_STOP0) +#define SPC5_ME_LP_PC6_BITS (SPC5_ME_LP_PC_HALT0 | \ + SPC5_ME_LP_PC_STOP0) +#define SPC5_ME_LP_PC7_BITS (SPC5_ME_LP_PC_HALT0 | \ + SPC5_ME_LP_PC_STOP0) +#define SPC5_PIT0_IRQ_PRIORITY 4 +#define SPC5_CLOCK_FAILURE_HOOK() chSysHalt() + +/* + * SERIAL driver system settings. + */ +#define SPC5_SERIAL_USE_LINFLEX0 TRUE +#define SPC5_SERIAL_USE_LINFLEX1 TRUE +#define SPC5_SERIAL_LINFLEX0_PRIORITY 8 +#define SPC5_SERIAL_LINFLEX1_PRIORITY 8 +#define SPC5_SERIAL_LINFLEX0_START_PCTL (SPC5_ME_PCTL_RUN(1) | \ + SPC5_ME_PCTL_LP(2)) +#define SPC5_SERIAL_LINFLEX0_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \ + SPC5_ME_PCTL_LP(0)) +#define SPC5_SERIAL_LINFLEX1_START_PCTL (SPC5_ME_PCTL_RUN(1) | \ + SPC5_ME_PCTL_LP(2)) +#define SPC5_SERIAL_LINFLEX1_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \ + SPC5_ME_PCTL_LP(0)) + +/* + * PWM driver system settings. + */ +#define SPC5_PWM_USE_SMOD0 TRUE +#define SPC5_PWM_USE_SMOD1 FALSE +#define SPC5_PWM_USE_SMOD2 FALSE +#define SPC5_PWM_USE_SMOD3 FALSE +#define SPC5_PWM_SMOD0_PRIORITY 7 +#define SPC5_PWM_SMOD1_PRIORITY 7 +#define SPC5_PWM_SMOD2_PRIORITY 7 +#define SPC5_PWM_SMOD3_PRIORITY 7 +#define SPC5_PWM_FLEXPWM0_START_PCTL (SPC5_ME_PCTL_RUN(1) | \ + SPC5_ME_PCTL_LP(2)) +#define SPC5_PWM_FLEXPWM0_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \ + SPC5_ME_PCTL_LP(0)) + +/* + * CAN driver system settings. + */ +#define SPC5_CAN_USE_FILTERS TRUE + +#define SPC5_CAN_USE_FLEXCAN0 TRUE +#define SPC5_CAN_FLEXCAN0_PRIORITY 11 +#define SPC5_CAN_FLEXCAN0_START_PCTL (SPC5_ME_PCTL_RUN(1) | \ + SPC5_ME_PCTL_LP(2)) +#define SPC5_CAN_FLEXCAN0_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \ + SPC5_ME_PCTL_LP(0)) diff --git a/testhal/SPC560Pxx/CAN/readme.txt b/testhal/SPC560Pxx/CAN/readme.txt new file mode 100644 index 000000000..b5587dd29 --- /dev/null +++ b/testhal/SPC560Pxx/CAN/readme.txt @@ -0,0 +1,27 @@ +***************************************************************************** +** ChibiOS/RT HAL - CAN drivers demo for SPC560Pxx. ** +***************************************************************************** + +** TARGET ** + +The demo runs on an STMicroelectronics SPC560Pxx microcontroller installed on +XPC56xx EVB Motherboard. + +** The Demo ** + +The application demonstrates the use of the SPC560Pxx CAN drivers. + +** Board Setup ** + +- Enable LED1 and LED2. + +** Build Procedure ** + +The demo has been tested using HighTec compiler. + +** Notes ** + +Some files used by the demo are not part of ChibiOS/RT but are copyright of +ST Microelectronics and are licensed under a different license. + + http://www.st.com diff --git a/testhal/SPC56ELxx/CAN/.cproject b/testhal/SPC56ELxx/CAN/.cproject new file mode 100644 index 000000000..dd958292f --- /dev/null +++ b/testhal/SPC56ELxx/CAN/.cproject @@ -0,0 +1,51 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/testhal/SPC56ELxx/CAN/.project b/testhal/SPC56ELxx/CAN/.project new file mode 100644 index 000000000..80fb08c6f --- /dev/null +++ b/testhal/SPC56ELxx/CAN/.project @@ -0,0 +1,38 @@ + + + SPC56ELxx-PWM-ICU + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + board + 2 + CHIBIOS/boards/ST_EVB_SPC56EL + + + os + 2 + CHIBIOS/os + + + diff --git a/testhal/SPC56ELxx/CAN/Makefile b/testhal/SPC56ELxx/CAN/Makefile new file mode 100644 index 000000000..79d8dd648 --- /dev/null +++ b/testhal/SPC56ELxx/CAN/Makefile @@ -0,0 +1,139 @@ +############################################################################## +# This file is automatically generated and can be overwritten, do no change +# this file manually. +############################################################################## +# Build global options +# NOTE: Can be overridden externally. +# + +# Compiler options here. +ifeq ($(USE_OPT),) + USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16 +endif + +# C specific options here (added to USE_OPT). +ifeq ($(USE_COPT),) + USE_COPT = +endif + +# C++ specific options here (added to USE_OPT). +ifeq ($(USE_CPPOPT),) + USE_CPPOPT = -fno-rtti -fno-exceptions +endif + +# Enable this if you want the linker to remove unused code and data. +ifeq ($(USE_LINK_GC),) + USE_LINK_GC = yes +endif + +# If enabled, this option allows to compile the application in VLE mode. +ifeq ($(USE_VLE),) + USE_VLE = yes +endif + +# Enable this if you want to see the full log while compiling. +ifeq ($(USE_VERBOSE_COMPILE),) + USE_VERBOSE_COMPILE = no +endif + +# +# Build global options +############################################################################## + +############################################################################## +# Project, sources and paths +# + +# Define project name here +PROJECT = out + +# Imported source files +include components/components.mak + +# Checks if there is a user mak file in the project directory. +ifneq ($(wildcard user.mak),) + include user.mak +endif + +# Define linker script file here +LDSCRIPT= application.ld + +# C sources here. +CSRC = $(LIB_C_SRC) \ + $(APP_C_SRC) \ + $(U_C_SRC) \ + ./components/components.c \ + ./main.c + +# C++ sources here. +CPPSRC = $(LIB_CPP_SRC) \ + $(APP_CPP_SRC) \ + $(U_CPP_SRC) + +# List ASM source files here +ASMSRC = $(LIB_ASM_SRC) \ + $(APP_ASM_SRC) \ + $(U_ASM_SRC) + +INCDIR = $(LIB_INCLUDES) \ + $(APP_INCLUDES) \ + ./components + +# +# Project, sources and paths +############################################################################## + +############################################################################## +# Compiler settings +# + +MCU = e200zx -meabi -msdata=none -mnew-mnemonics -mregnames + +TRGT = ppc-vle- +CC = $(TRGT)gcc +CPPC = $(TRGT)g++ +# Enable loading with g++ only if you need C++ runtime support. +# NOTE: You can use C++ even without C++ support if you are careful. C++ +# runtime support makes code size explode. +LD = $(TRGT)gcc +#LD = $(TRGT)g++ +CP = $(TRGT)objcopy +AS = $(TRGT)gcc -x assembler-with-cpp +OD = $(TRGT)objdump +HEX = $(CP) -O ihex +BIN = $(CP) -O binary + +# Define C warning options here +CWARN = -Wall -Wextra -Wstrict-prototypes + +# Define C++ warning options here +CPPWARN = -Wall -Wextra + +# +# Compiler settings +############################################################################## + +############################################################################## +# Start of default section +# + +# List all default C defines here, like -D_DEBUG=1 +DDEFS = -DSPC56EL60L3 + +# List all default ASM defines here, like -D_DEBUG=1 +DADEFS = + +# List all default directories to look for include files here +DINCDIR = + +# List the default directory to look for the libraries here +DLIBDIR = + +# List all default libraries here +DLIBS = + +# +# End of default section +############################################################################## + +include C:/SPC5Studio/eclipse/plugins/com.st.tools.spc5.components.platform.spc56elxx_1.0.0.201302201417/component/lib/rsc/rules.mk diff --git a/testhal/SPC56ELxx/CAN/chconf.h b/testhal/SPC56ELxx/CAN/chconf.h new file mode 100644 index 000000000..8800269d4 --- /dev/null +++ b/testhal/SPC56ELxx/CAN/chconf.h @@ -0,0 +1,529 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef _CHCONF_H_ +#define _CHCONF_H_ + +/*===========================================================================*/ +/** + * @name Kernel parameters and options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#if !defined(CH_FREQUENCY) || defined(__DOXYGEN__) +#define CH_FREQUENCY 1000 +#endif + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + */ +#if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__) +#define CH_TIME_QUANTUM 20 +#endif + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_USE_MEMCORE. + */ +#if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__) +#define CH_MEMCORE_SIZE 0 +#endif + +/** + * @brief Idle thread automatic spawn suppression. + * @details When this option is activated the function @p chSysInit() + * does not spawn the idle thread automatically. The application has + * then the responsibility to do one of the following: + * - Spawn a custom idle thread at priority @p IDLEPRIO. + * - Change the main() thread priority to @p IDLEPRIO then enter + * an endless loop. In this scenario the @p main() thread acts as + * the idle thread. + * . + * @note Unless an idle thread is spawned the @p main() thread must not + * enter a sleep state. + */ +#if !defined(CH_NO_IDLE_THREAD) || defined(__DOXYGEN__) +#define CH_NO_IDLE_THREAD FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Performance options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__) +#define CH_OPTIMIZE_SPEED TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Subsystem options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_REGISTRY) || defined(__DOXYGEN__) +#define CH_USE_REGISTRY TRUE +#endif + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__) +#define CH_USE_WAITEXIT TRUE +#endif + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES TRUE +#endif + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES_PRIORITY FALSE +#endif + +/** + * @brief Atomic semaphore API. + * @details If enabled then the semaphores the @p chSemSignalWait() API + * is included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__) +#define CH_USE_SEMSW TRUE +#endif + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__) +#define CH_USE_MUTEXES TRUE +#endif + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MUTEXES. + */ +#if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS TRUE +#endif + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_CONDVARS. + */ +#if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS_TIMEOUT TRUE +#endif + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__) +#define CH_USE_EVENTS TRUE +#endif + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_EVENTS. + */ +#if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_EVENTS_TIMEOUT TRUE +#endif + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES TRUE +#endif + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_MESSAGES. + */ +#if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES_PRIORITY FALSE +#endif + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__) +#define CH_USE_MAILBOXES TRUE +#endif + +/** + * @brief I/O Queues APIs. + * @details If enabled then the I/O queues APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__) +#define CH_USE_QUEUES TRUE +#endif + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__) +#define CH_USE_MEMCORE TRUE +#endif + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MEMCORE and either @p CH_USE_MUTEXES or + * @p CH_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) +#define CH_USE_HEAP TRUE +#endif + +/** + * @brief C-runtime allocator. + * @details If enabled the the heap allocator APIs just wrap the C-runtime + * @p malloc() and @p free() functions. + * + * @note The default is @p FALSE. + * @note Requires @p CH_USE_HEAP. + * @note The C-runtime may or may not require @p CH_USE_MEMCORE, see the + * appropriate documentation. + */ +#if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__) +#define CH_USE_MALLOC_HEAP FALSE +#endif + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__) +#define CH_USE_MEMPOOLS TRUE +#endif + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_WAITEXIT. + * @note Requires @p CH_USE_HEAP and/or @p CH_USE_MEMPOOLS. + */ +#if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__) +#define CH_USE_DYNAMIC TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Debug options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Debug option, system state check. + * @details If enabled the correct call protocol for system APIs is checked + * at runtime. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_SYSTEM_STATE_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_SYSTEM_STATE_CHECK FALSE +#endif + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_CHECKS FALSE +#endif + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_ASSERTS FALSE +#endif + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the context switch circular trace buffer is + * activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_TRACE FALSE +#endif + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_STACK_CHECK FALSE +#endif + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__) +#define CH_DBG_FILL_THREADS FALSE +#endif + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p Thread structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p TRUE. + * @note This debug option is defaulted to TRUE because it is required by + * some test cases into the test suite. + */ +#if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__) +#define CH_DBG_THREADS_PROFILING TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel hooks + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads descriptor structure extension. + * @details User fields added to the end of the @p Thread structure. + */ +#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) +#define THREAD_EXT_FIELDS \ + +#endif + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p chThdInit() API. + * + * @note It is invoked from within @p chThdInit() and implicitly from all + * the threads creation APIs. + */ +#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_INIT_HOOK(tp) { \ +} +#endif + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + * + * @note It is inserted into lock zone. + * @note It is also invoked when the threads simply return in order to + * terminate. + */ +#if !defined(THREAD_EXT_EXIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_EXIT_HOOK(tp) { \ +} +#endif + +/** + * @brief Context switch hook. + * @details This hook is invoked just before switching between threads. + */ +#if !defined(THREAD_CONTEXT_SWITCH_HOOK) || defined(__DOXYGEN__) +#define THREAD_CONTEXT_SWITCH_HOOK(ntp, otp) { \ +} +#endif + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) +#define IDLE_LOOP_HOOK() { \ +} +#endif + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#if !defined(SYSTEM_TICK_EVENT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_TICK_EVENT_HOOK() { \ +} +#endif + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#if !defined(SYSTEM_HALT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_HALT_HOOK() { \ +} +#endif + +/** @} */ + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + +#endif /* _CHCONF_H_ */ + +/** @} */ diff --git a/testhal/SPC56ELxx/CAN/halconf.h b/testhal/SPC56ELxx/CAN/halconf.h new file mode 100644 index 000000000..7c9fe78a8 --- /dev/null +++ b/testhal/SPC56ELxx/CAN/halconf.h @@ -0,0 +1,371 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * + * @addtogroup HAL_CONF + * @{ + */ + +#ifndef _HALCONF_H_ +#define _HALCONF_H_ + +#include "mcuconf.h" + +/** + * @name Drivers enable switches + */ +/** + * @brief Enables the TM subsystem. + */ +#if !defined(HAL_USE_TM) || defined(__DOXYGEN__) +#define HAL_USE_TM FALSE +#endif + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC FALSE +#endif + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN TRUE +#endif + +/** + * @brief Enables the EXT subsystem. + */ +#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__) +#define HAL_USE_EXT FALSE +#endif + +/** + * @brief Enables the GPT subsystem. + */ +#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) +#define HAL_USE_GPT FALSE +#endif + +/** + * @brief Enables the I2C subsystem. + */ +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C FALSE +#endif + +/** + * @brief Enables the ICU subsystem. + */ +#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) +#define HAL_USE_ICU TRUE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM TRUE +#endif + +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC FALSE +#endif + +/** + * @brief Enables the SDC subsystem. + */ +#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) +#define HAL_USE_SDC FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL TRUE +#endif + +/** + * @brief Enables the SERIAL over USB subsystem. + */ +#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL_USB FALSE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI FALSE +#endif + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART FALSE +#endif + +/** + * @brief Enables the USB subsystem. + */ +#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) +#define HAL_USE_USB FALSE +#endif +/** @} */ + +/*===========================================================================*/ +/** + * @name ADC driver related setting + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION FALSE +#endif +/** @} */ + +/*===========================================================================*/ +/** + * @name CAN driver related setting + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Sleep mode related APIs inclusion switch. + */ +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE FALSE +#endif +/** @} */ + +/*===========================================================================*/ +/** + * @name I2C driver related setting + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Enables the mutual exclusion APIs on the I2C bus. + */ +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION FALSE +#endif +/** @} */ + +/*===========================================================================*/ +/** + * @name MAC driver related setting + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) +#define MAC_USE_ZERO_COPY FALSE +#endif + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif +/** @} */ + +/*===========================================================================*/ +/** + * @name MMC_SPI driver related setting + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + * This option is recommended also if the SPI driver does not + * use a DMA channel and heavily loads the CPU. + */ +#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) +#define MMC_NICE_WAITING TRUE +#endif +/** @} */ + +/*===========================================================================*/ +/** + * @name SDC driver related setting + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Number of initialization attempts before rejecting the card. + * @note Attempts are performed at 10mS intervals. + */ +#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) +#define SDC_INIT_RETRY 1 +#endif + +/** + * @brief Include support for MMC cards. + * @note MMC support is not yet implemented so this option must be kept + * at @p FALSE. + */ +#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) +#define SDC_MMC_SUPPORT FALSE +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + */ +#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) +#define SDC_NICE_WAITING TRUE +#endif +/** @} */ + +/*===========================================================================*/ +/** + * @name SERIAL driver related setting + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 64 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif +/** @} */ + +/*===========================================================================*/ +/** + * @name SERIAL_USB driver related setting + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Serial over USB buffers size. + * @details Configuration parameter, the buffer size must be a multiple of + * the USB data endpoint maximum packet size. + * @note The default is 64 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_USB_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_USB_BUFFERS_SIZE 64 +#endif +/** @} */ + +/*===========================================================================*/ +/** + * @name SPI driver related setting + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION FALSE +#endif +/** @} */ + +#endif /* _HALCONF_H_ */ + +/** @} */ diff --git a/testhal/SPC56ELxx/CAN/main.c b/testhal/SPC56ELxx/CAN/main.c new file mode 100644 index 000000000..a56000ff9 --- /dev/null +++ b/testhal/SPC56ELxx/CAN/main.c @@ -0,0 +1,149 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include "ch.h" +#include "hal.h" + +struct can_instance { + CANDriver *canp; + uint32_t led; +}; + +static const struct can_instance can1 = {&CAND1, PD_LED1}; + +/* + * Internal loopback mode, 1MBaud. + * See chapter 25 on the SPC5 reference manual. + */ +static const CANConfig cancfg = { + CAN_MCR_WRN_EN, + CAN_CTRL_LPB | CAN_CTRL_PROPSEG(2) | CAN_CTRL_PSEG2(7) | + CAN_CTRL_PSEG1(3) | CAN_CTRL_PRESDIV(3) +#if SPC5_CAN_USE_FILTERS + , + { + {0, 0x00000001}, + {1, 0x01234567}, + {0, 0x00000000}, + {0, 0x00000003}, + {0, 0x00000004}, + {0, 0x00000005}, + {0, 0x00000006}, + {0, 0x00000007} + } +#endif +}; + +#if SPC5_CAN_USE_FILTERS +flagsmask_t rxFlag; +#endif + +/* + * Receiver thread. + */ +static WORKING_AREA(can_rx_wa, 256); +static msg_t can_rx(void *p) { + struct can_instance *cip = p; + EventListener el; + CANRxFrame rxmsg; + (void)p; + chRegSetThreadName("receiver"); + chEvtRegister(&cip->canp->rxfull_event, &el, 0); +#if SPC5_CAN_USE_FILTERS + rxFlag = chEvtGetAndClearFlagsI(&el); +#endif + while(!chThdShouldTerminate()) { + if (chEvtWaitAnyTimeout(ALL_EVENTS, MS2ST(100)) == 0) + continue; +#if !SPC5_CAN_USE_FILTERS + while (canReceive(cip->canp, CAN_ANY_MAILBOX, + &rxmsg, TIME_IMMEDIATE) == RDY_OK) { + /* Process message.*/ + palTogglePad(PORT_D, cip->led); + } +#else + while (canReceive(cip->canp, rxFlag, + &rxmsg, TIME_IMMEDIATE) == RDY_OK) { + /* Process message.*/ + palTogglePad(PORT_D, cip->led); + } +#endif + } + chEvtUnregister(&CAND1.rxfull_event, &el); + return 0; +} + +/* + * Transmitter thread. + */ +static WORKING_AREA(can_tx_wa, 256); +static msg_t can_tx(void * p) { + CANTxFrame txmsg; + + (void)p; + chRegSetThreadName("transmitter"); + txmsg.IDE = CAN_IDE_EXT; + txmsg.EID = 0x01234567; + txmsg.RTR = CAN_RTR_DATA; + txmsg.LENGTH = 8; + txmsg.data32[0] = 0x55AA55AA; + txmsg.data32[1] = 0x00FF00FF; + + while (!chThdShouldTerminate()) { + canTransmit(&CAND1, 1, &txmsg, MS2ST(100)); + palTogglePad(PORT_D, PD_LED2); + chThdSleepMilliseconds(500); + } + return 0; +} + +/* + * Application entry point. + */ +int main(void) { + + /* + * System initializations. + * - HAL initialization, this also initializes the configured device drivers + * and performs the board-specific initializations. + * - Kernel initialization, the main() function becomes a thread and the + * RTOS is active. + */ + halInit(); + chSysInit(); + + /* + * Activates the CAN driver 1. + */ + canStart(&CAND1, &cancfg); + + /* + * Starting the transmitter and receiver threads. + */ + chThdCreateStatic(can_rx_wa, sizeof(can_rx_wa), NORMALPRIO + 7, + can_rx, (void *)&can1); + chThdCreateStatic(can_tx_wa, sizeof(can_tx_wa), NORMALPRIO + 7, + can_tx, NULL); + + /* + * Normal main() thread activity, in this demo it does nothing. + */ + while (TRUE) { + chThdSleepMilliseconds(500); + } + return 0; +} + diff --git a/testhal/SPC56ELxx/CAN/mcuconf.h b/testhal/SPC56ELxx/CAN/mcuconf.h new file mode 100644 index 000000000..212082fc9 --- /dev/null +++ b/testhal/SPC56ELxx/CAN/mcuconf.h @@ -0,0 +1,236 @@ +/* + * Licensed under ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * SPC56ELxx drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the whole + * driver is enabled in halconf.h. + * + * IRQ priorities: + * 1...15 Lowest...Highest. + */ + +#define SPC56ELxx_MCUCONF + +/* + * HAL driver system settings. + */ +#define SPC5_NO_INIT FALSE +#define SPC5_ALLOW_OVERCLOCK FALSE +#define SPC5_DISABLE_WATCHDOG TRUE +#define SPC5_FMPLL0_CLK_SRC SPC5_FMPLL_SRC_XOSC +#define SPC5_FMPLL0_IDF_VALUE 5 +#define SPC5_FMPLL0_NDIV_VALUE 32 +#define SPC5_FMPLL0_ODF SPC5_FMPLL_ODF_DIV4 +#define SPC5_FMPLL1_CLK_SRC SPC5_FMPLL_SRC_XOSC +#define SPC5_FMPLL1_IDF_VALUE 5 +#define SPC5_FMPLL1_NDIV_VALUE 60 +#define SPC5_FMPLL1_ODF SPC5_FMPLL_ODF_DIV4 +#define SPC5_SYSCLK_DIVIDER_VALUE 2 +#define SPC5_AUX0CLK_SRC SPC5_CGM_SS_FMPLL0 +#define SPC5_MCONTROL_DIVIDER_VALUE 2 +#define SPC5_SWG_DIVIDER_VALUE 2 +#define SPC5_AUX1CLK_SRC SPC5_CGM_SS_FMPLL1 +#define SPC5_FLEXRAY_DIVIDER_VALUE 2 +#define SPC5_AUX2CLK_SRC SPC5_CGM_SS_FMPLL1 +#define SPC5_FLEXCAN_DIVIDER_VALUE 2 +#define SPC5_ME_ME_BITS (SPC5_ME_ME_RUN1 | \ + SPC5_ME_ME_RUN2 | \ + SPC5_ME_ME_RUN3 | \ + SPC5_ME_ME_HALT0 | \ + SPC5_ME_ME_STOP0) +#define SPC5_ME_SAFE_MC_BITS (SPC5_ME_MC_PDO) +#define SPC5_ME_DRUN_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \ + SPC5_ME_MC_IRCON | \ + SPC5_ME_MC_XOSC0ON | \ + SPC5_ME_MC_PLL0ON | \ + SPC5_ME_MC_PLL1ON | \ + SPC5_ME_MC_FLAON_NORMAL | \ + SPC5_ME_MC_MVRON) +#define SPC5_ME_RUN0_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \ + SPC5_ME_MC_IRCON | \ + SPC5_ME_MC_XOSC0ON | \ + SPC5_ME_MC_PLL0ON | \ + SPC5_ME_MC_PLL1ON | \ + SPC5_ME_MC_FLAON_NORMAL | \ + SPC5_ME_MC_MVRON) +#define SPC5_ME_RUN1_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \ + SPC5_ME_MC_IRCON | \ + SPC5_ME_MC_XOSC0ON | \ + SPC5_ME_MC_PLL0ON | \ + SPC5_ME_MC_PLL1ON | \ + SPC5_ME_MC_FLAON_NORMAL | \ + SPC5_ME_MC_MVRON) +#define SPC5_ME_RUN2_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \ + SPC5_ME_MC_IRCON | \ + SPC5_ME_MC_XOSC0ON | \ + SPC5_ME_MC_PLL0ON | \ + SPC5_ME_MC_PLL1ON | \ + SPC5_ME_MC_FLAON_NORMAL | \ + SPC5_ME_MC_MVRON) +#define SPC5_ME_RUN3_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \ + SPC5_ME_MC_IRCON | \ + SPC5_ME_MC_XOSC0ON | \ + SPC5_ME_MC_PLL0ON | \ + SPC5_ME_MC_PLL1ON | \ + SPC5_ME_MC_FLAON_NORMAL | \ + SPC5_ME_MC_MVRON) +#define SPC5_ME_HALT0_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \ + SPC5_ME_MC_IRCON | \ + SPC5_ME_MC_XOSC0ON | \ + SPC5_ME_MC_PLL0ON | \ + SPC5_ME_MC_PLL1ON | \ + SPC5_ME_MC_FLAON_NORMAL | \ + SPC5_ME_MC_MVRON) +#define SPC5_ME_STOP0_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \ + SPC5_ME_MC_IRCON | \ + SPC5_ME_MC_XOSC0ON | \ + SPC5_ME_MC_PLL0ON | \ + SPC5_ME_MC_PLL1ON | \ + SPC5_ME_MC_FLAON_NORMAL | \ + SPC5_ME_MC_MVRON) +#define SPC5_ME_RUN_PC3_BITS (SPC5_ME_RUN_PC_RUN0 | \ + SPC5_ME_RUN_PC_RUN1 | \ + SPC5_ME_RUN_PC_RUN2 | \ + SPC5_ME_RUN_PC_RUN3) +#define SPC5_ME_RUN_PC4_BITS (SPC5_ME_RUN_PC_RUN0 | \ + SPC5_ME_RUN_PC_RUN1 | \ + SPC5_ME_RUN_PC_RUN2 | \ + SPC5_ME_RUN_PC_RUN3) +#define SPC5_ME_RUN_PC5_BITS (SPC5_ME_RUN_PC_RUN0 | \ + SPC5_ME_RUN_PC_RUN1 | \ + SPC5_ME_RUN_PC_RUN2 | \ + SPC5_ME_RUN_PC_RUN3) +#define SPC5_ME_RUN_PC6_BITS (SPC5_ME_RUN_PC_RUN0 | \ + SPC5_ME_RUN_PC_RUN1 | \ + SPC5_ME_RUN_PC_RUN2 | \ + SPC5_ME_RUN_PC_RUN3) +#define SPC5_ME_RUN_PC7_BITS (SPC5_ME_RUN_PC_RUN0 | \ + SPC5_ME_RUN_PC_RUN1 | \ + SPC5_ME_RUN_PC_RUN2 | \ + SPC5_ME_RUN_PC_RUN3) +#define SPC5_ME_LP_PC4_BITS (SPC5_ME_LP_PC_HALT0 | \ + SPC5_ME_LP_PC_STOP0) +#define SPC5_ME_LP_PC5_BITS (SPC5_ME_LP_PC_HALT0 | \ + SPC5_ME_LP_PC_STOP0) +#define SPC5_ME_LP_PC6_BITS (SPC5_ME_LP_PC_HALT0 | \ + SPC5_ME_LP_PC_STOP0) +#define SPC5_ME_LP_PC7_BITS (SPC5_ME_LP_PC_HALT0 | \ + SPC5_ME_LP_PC_STOP0) +#define SPC5_CLOCK_FAILURE_HOOK() chSysHalt() + +/* + * SERIAL driver system settings. + */ +#define SPC5_SERIAL_USE_LINFLEX0 TRUE +#define SPC5_SERIAL_USE_LINFLEX1 TRUE +#define SPC5_SERIAL_LINFLEX0_PRIORITY 8 +#define SPC5_SERIAL_LINFLEX1_PRIORITY 8 +#define SPC5_SERIAL_LINFLEX0_START_PCTL (SPC5_ME_PCTL_RUN(1) | \ + SPC5_ME_PCTL_LP(2)) +#define SPC5_SERIAL_LINFLEX0_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \ + SPC5_ME_PCTL_LP(0)) +#define SPC5_SERIAL_LINFLEX1_START_PCTL (SPC5_ME_PCTL_RUN(1) | \ + SPC5_ME_PCTL_LP(2)) +#define SPC5_SERIAL_LINFLEX1_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \ + SPC5_ME_PCTL_LP(0)) + +/* + * PWM driver system settings. + */ +#define SPC5_PWM_USE_SMOD0 TRUE +#define SPC5_PWM_USE_SMOD1 FALSE +#define SPC5_PWM_USE_SMOD2 FALSE +#define SPC5_PWM_USE_SMOD3 FALSE +#define SPC5_PWM_SMOD0_PRIORITY 7 +#define SPC5_PWM_SMOD1_PRIORITY 7 +#define SPC5_PWM_SMOD2_PRIORITY 7 +#define SPC5_PWM_SMOD3_PRIORITY 7 +#define SPC5_PWM_FLEXPWM0_START_PCTL (SPC5_ME_PCTL_RUN(1) | \ + SPC5_ME_PCTL_LP(2)) +#define SPC5_PWM_FLEXPWM0_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \ + SPC5_ME_PCTL_LP(0)) + +#define SPC5_PWM_USE_SMOD4 FALSE +#define SPC5_PWM_USE_SMOD5 FALSE +#define SPC5_PWM_USE_SMOD6 FALSE +#define SPC5_PWM_USE_SMOD7 FALSE +#define SPC5_PWM_SMOD4_PRIORITY 7 +#define SPC5_PWM_SMOD5_PRIORITY 7 +#define SPC5_PWM_SMOD6_PRIORITY 7 +#define SPC5_PWM_SMOD7_PRIORITY 7 +#define SPC5_PWM_FLEXPWM1_START_PCTL (SPC5_ME_PCTL_RUN(1) | \ + SPC5_ME_PCTL_LP(2)) +#define SPC5_PWM_FLEXPWM1_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \ + SPC5_ME_PCTL_LP(0)) + +/* + * ICU driver system settings. + */ +#define SPC5_ICU_USE_SMOD0 TRUE +#define SPC5_ICU_USE_SMOD1 FALSE +#define SPC5_ICU_USE_SMOD2 FALSE +#define SPC5_ICU_USE_SMOD3 FALSE +#define SPC5_ICU_USE_SMOD4 FALSE +#define SPC5_ICU_USE_SMOD5 FALSE +#define SPC5_ICU_ETIMER0_PRIORITY 7 +#define SPC5_ICU_ETIMER0_START_PCTL (SPC5_ME_PCTL_RUN(1) | \ + SPC5_ME_PCTL_LP(2)) +#define SPC5_ICU_ETIMER0_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \ + SPC5_ME_PCTL_LP(0)) + +#define SPC5_ICU_USE_SMOD6 FALSE +#define SPC5_ICU_USE_SMOD7 FALSE +#define SPC5_ICU_USE_SMOD8 FALSE +#define SPC5_ICU_USE_SMOD9 FALSE +#define SPC5_ICU_USE_SMOD10 FALSE +#define SPC5_ICU_USE_SMOD11 FALSE +#define SPC5_ICU_ETIMER1_PRIORITY 7 +#define SPC5_ICU_ETIMER1_START_PCTL (SPC5_ME_PCTL_RUN(1) | \ + SPC5_ME_PCTL_LP(2)) +#define SPC5_ICU_ETIMER1_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \ + SPC5_ME_PCTL_LP(0)) + +#define SPC5_ICU_USE_SMOD12 FALSE +#define SPC5_ICU_USE_SMOD13 FALSE +#define SPC5_ICU_USE_SMOD14 FALSE +#define SPC5_ICU_USE_SMOD15 FALSE +#define SPC5_ICU_USE_SMOD16 FALSE +#define SPC5_ICU_USE_SMOD17 TRUE +#define SPC5_ICU_ETIMER2_PRIORITY 7 +#define SPC5_ICU_ETIMER2_START_PCTL (SPC5_ME_PCTL_RUN(1) | \ + SPC5_ME_PCTL_LP(2)) +#define SPC5_ICU_ETIMER2_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \ + SPC5_ME_PCTL_LP(0)) + +/* + * CAN driver system settings. + */ +#define SPC5_CAN_USE_FILTERS TRUE + +#define SPC5_CAN_USE_FLEXCAN0 TRUE +#define SPC5_CAN_FLEXCAN0_PRIORITY 11 +#define SPC5_CAN_FLEXCAN0_START_PCTL (SPC5_ME_PCTL_RUN(1) | \ + SPC5_ME_PCTL_LP(2)) +#define SPC5_CAN_FLEXCAN0_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \ + SPC5_ME_PCTL_LP(0)) + +#define SPC5_CAN_USE_FLEXCAN1 FALSE +#define SPC5_CAN_FLEXCAN1_PRIORITY 11 +#define SPC5_CAN_FLEXCAN1_START_PCTL (SPC5_ME_PCTL_RUN(1) | \ + SPC5_ME_PCTL_LP(2)) +#define SPC5_CAN_FLEXCAN1_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \ + SPC5_ME_PCTL_LP(0)) diff --git a/testhal/SPC56ELxx/CAN/readme.txt b/testhal/SPC56ELxx/CAN/readme.txt new file mode 100644 index 000000000..036a5502e --- /dev/null +++ b/testhal/SPC56ELxx/CAN/readme.txt @@ -0,0 +1,27 @@ +***************************************************************************** +** ChibiOS/RT HAL - CAN drivers demo for SPC56ELxx. ** +***************************************************************************** + +** TARGET ** + +The demo runs on an STMicroelectronics SPC56ELxx microcontroller installed on +XPC56xx EVB Motherboard. + +** The Demo ** + +The application demonstrates the use of the SPC56ELxx CAN drivers. + +** Board Setup ** + +- Enable LED1 and LED2. + +** Build Procedure ** + +The demo has been tested using HighTec compiler. + +** Notes ** + +Some files used by the demo are not part of ChibiOS/RT but are copyright of +ST Microelectronics and are licensed under a different license. + + http://www.st.com