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Added cache handling to DMAv2 driver. 

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@8209 35acf78f-673a-0410-8e92-d51de3d6d3f4
This commit is contained in:
gdisirio 2015-08-13 09:57:10 +00:00
parent 82ed9f3093
commit d8b4ba3e59
8 changed files with 286 additions and 65 deletions
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164
doc/rt/reports/STM32L053-32-GCC.txt Normal file
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@ -0,0 +1,164 @@
*** ChibiOS/RT test suite
***
*** Kernel: 3.0.0
*** Compiled: Jul 16 2015 - 14:39:45
*** Compiler: GCC 4.7.4 20140401 (release) [ARM/embedded-4_7-branch revision 209195]
*** Architecture: ARMv6-M
*** Core Variant: Cortex-M0+
*** Port Info: Preemption through NMI
*** Platform: STM32L053xx ultra-low-power MCU
*** Test Board: STMicroelectronics NUCLEO-L053R8
----------------------------------------------------------------------------
--- Test Case 1.1 (System, critical zones)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 1.2 (System, interrupts handling)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 1.3 (System, integrity)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 2.1 (Threads, enqueuing test #1)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 2.2 (Threads, enqueuing test #2)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 2.3 (Threads, priority change)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 2.4 (Threads, delays)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 3.1 (Semaphores, enqueuing)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 3.2 (Semaphores, timeout)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 3.3 (Semaphores, atomic signal-wait)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 3.4 (Binary Semaphores, functionality)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 4.1 (Mutexes, priority enqueuing test)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 4.2 (Mutexes, priority return)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 4.3 (Mutexes, status)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 4.4 (CondVar, signal test)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 4.5 (CondVar, broadcast test)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 4.6 (CondVar, boost test)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 5.1 (Messages, loop)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 6.1 (Mailboxes, queuing and timeouts)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 7.1 (Events, registration and dispatch)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 7.2 (Events, wait and broadcast)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 7.3 (Events, timeouts)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 8.1 (Heap, allocation and fragmentation test)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 9.1 (Memory Pools, queue/dequeue)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 10.1 (Dynamic APIs, threads creation from heap)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 10.2 (Dynamic APIs, threads creation from memory pool)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 10.3 (Dynamic APIs, registry and references)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.1 (Queues, input queues)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.2 (Queues, output queues)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 12.1 (Benchmark, messages #1)
--- Score : 113068 msgs/S, 226136 ctxswc/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 12.2 (Benchmark, messages #2)
--- Score : 90392 msgs/S, 180784 ctxswc/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 12.3 (Benchmark, messages #3)
--- Score : 90392 msgs/S, 180784 ctxswc/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 12.4 (Benchmark, context switch)
--- Score : 329040 ctxswc/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 12.5 (Benchmark, threads, full cycle)
--- Score : 70950 threads/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 12.6 (Benchmark, threads, create only)
--- Score : 102232 threads/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 12.7 (Benchmark, mass reschedule, 5 threads)
--- Score : 28907 reschedules/S, 173442 ctxswc/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 12.8 (Benchmark, round robin context switching)
--- Score : 240140 ctxswc/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 12.9 (Benchmark, I/O Queues throughput)
--- Score : 310484 bytes/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 12.10 (Benchmark, virtual timers set/reset)
--- Score : 196290 timers/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 12.11 (Benchmark, semaphores wait/signal)
--- Score : 630528 wait+signal/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 12.12 (Benchmark, mutexes lock/unlock)
--- Score : 314492 lock+unlock/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 12.13 (Benchmark, RAM footprint)
--- System: 328 bytes
--- Thread: 68 bytes
--- Timer : 20 bytes
--- Semaph: 12 bytes
--- EventS: 4 bytes
--- EventL: 20 bytes
--- Mutex : 16 bytes
--- CondV.: 8 bytes
--- Queue : 36 bytes
--- MailB.: 40 bytes
--- Result: SUCCESS
----------------------------------------------------------------------------
Final result: SUCCESS

19
os/hal/ports/STM32/LLD/DMAv2/stm32_dma.c
View File

@ -428,6 +428,25 @@ void dmaInit(void) {
DMA1->HIFCR = 0xFFFFFFFFU;
DMA2->LIFCR = 0xFFFFFFFFU;
DMA2->HIFCR = 0xFFFFFFFFU;
#if defined(STM32F7XX)
/* If the DMA is in use then the DMA-accessible RAM must be programmed as
Write Through using the MPU, region zero is used with a size of 512kB,
the sub-regions are programmed as follow:
- 0..4, enabled, it is the normal, DMA-accessible, RAM.
- 5..7, disabled, beyond RAM area.
The system memory layout is used as "background" for the MPU regions.*/
mpuConfigureRegion(MPU_REGION_0,
0x20000000U,
MPU_RASR_ATTR_AP_RW_RW |
MPU_RASR_ATTR_CACHEABLE_WT_NWA |
MPU_RNR_REGION(5) |
MPU_RNR_REGION(6) |
MPU_RNR_REGION(7) |
MPU_RASR_SIZE_512K |
MPU_RASR_ENABLE);
mpuEnable(MPU_CTRL_PRIVDEFENA);
#endif
}
/**

23
os/hal/ports/STM32/LLD/DMAv2/stm32_dma.h
View File

@ -235,6 +235,29 @@ typedef void (*stm32_dmaisr_t)(void *p, uint32_t flags);
/* Driver macros. */
/*===========================================================================*/
#if defined(STM32F7XX) || defined(__DOXYGEN__)
/**
* @brief Invalidates the data cache lines overlapping a DMA buffer.
* @note On devices without data cache this function does nothing.
* @note The function takes care of cache lines alignment.
*
* @param[in] addr address of the DMA buffer
* @param[in] size size of the DMA buffer
*
* @api
*/
#define dmaBufferInvalidate(addr, size) { \
uint32_t *aaddr = (uint32_t *)(((uint32_t)(addr)) & ~0x1FU); \
uint32_t asize = (uint32_t)((((size) - 1) | 0x1FU) + 1U); \
SCB_CleanInvalidateDCache_by_Addr(aaddr, asize); \
}
#else
#define dmaBufferInvalidate(addr, size) { \
(void)(addr); \
(void)(size); \
}
#endif
/**
* @name Macro Functions
* @{

1
os/hal/ports/STM32/STM32F7xx/hal_lld.h
View File

@ -1877,6 +1877,7 @@
/* Various helpers.*/
#include "nvic.h"
#include "mpu.h"
#include "stm32_dma.h"
#include "stm32_rcc.h"

51
os/hal/ports/common/ARMCMx/mpu.c
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@ -1,51 +0,0 @@
/*
ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
/**
* @file common/ARMCMx/mpu.c
* @brief Cortex-Mx MPU support code.
*
* @addtogroup COMMON_ARMCMx_MPU
* @{
*/
#include "hal.h"
/*===========================================================================*/
/* Driver local definitions. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver exported variables. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver local types. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver local variables. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver local functions. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver exported functions. */
/*===========================================================================*/
/** @} */

75
os/hal/ports/common/ARMCMx/mpu.h
View File

@ -33,6 +33,10 @@
* @name MPU registers definitions
* @{
*/
#define MPU_TYPE_SEPARATED (1U << 0U)
#define MPU_TYPE_DREGION(n) (((n) >> 8U) & 255U)
#define MPU_TYPE_IREGION(n) (((n) >> 16U) & 255U)
#define MPU_CTRL_ENABLE (1U << 0U)
#define MPU_CTRL_HFNMIENA (1U << 1U)
#define MPU_CTRL_PRIVDEFENA (1U << 2U)
@ -80,14 +84,14 @@
#define MPU_RASR_SRD_MASK (255U << 8U)
#define MPU_RASR_SRD(n) ((n) << 8U)
#define MPU_RASR_SRD_ALL (0U << 8U)
#define MPU_RASR_SRD_DISABLE_SUB1 (1U << 8U)
#define MPU_RASR_SRD_DISABLE_SUB2 (2U << 8U)
#define MPU_RASR_SRD_DISABLE_SUB3 (4U << 8U)
#define MPU_RASR_SRD_DISABLE_SUB4 (8U << 8U)
#define MPU_RASR_SRD_DISABLE_SUB5 (16U << 8U)
#define MPU_RASR_SRD_DISABLE_SUB6 (32U << 8U)
#define MPU_RASR_SRD_DISABLE_SUB7 (64U << 8U)
#define MPU_RASR_SRD_DISABLE_SUB8 (128U << 8U)
#define MPU_RASR_SRD_DISABLE_SUB0 (1U << 8U)
#define MPU_RASR_SRD_DISABLE_SUB1 (2U << 8U)
#define MPU_RASR_SRD_DISABLE_SUB2 (4U << 8U)
#define MPU_RASR_SRD_DISABLE_SUB3 (8U << 8U)
#define MPU_RASR_SRD_DISABLE_SUB4 (16U << 8U)
#define MPU_RASR_SRD_DISABLE_SUB5 (32U << 8U)
#define MPU_RASR_SRD_DISABLE_SUB6 (64U << 8U)
#define MPU_RASR_SRD_DISABLE_SUB7 (128U << 8U)
#define MPU_RASR_ATTR_B (1U << 16U)
#define MPU_RASR_ATTR_C (1U << 17U)
#define MPU_RASR_ATTR_S (1U << 18U)
@ -117,6 +121,20 @@
#define MPU_RASR_ATTR_NON_SHARED_DEVICE (MPU_RASR_ATTR_TEX(2))
/** @} */
/**
* @name Region identifiers
* @{
*/
#define MPU_REGION_0 0U
#define MPU_REGION_1 1U
#define MPU_REGION_2 2U
#define MPU_REGION_3 3U
#define MPU_REGION_4 4U
#define MPU_REGION_5 5U
#define MPU_REGION_6 6U
#define MPU_REGION_7 7U
/** @} */
/*===========================================================================*/
/* Driver pre-compile time settings. */
/*===========================================================================*/
@ -133,6 +151,47 @@
/* Driver macros. */
/*===========================================================================*/
/**
* @brief Enables the MPU.
* @note MEMFAULENA is enabled in SCB_SHCSR.
*
* @param[in] ctrl MPU control modes as defined in @p MPU_CTRL register,
* the enable bit is enforced
*
* @api
*/
#define mpuEnable(ctrl) { \
MPU->CTRL = ((uint32_t)ctrl) | MPU_CTRL_ENABLE; \
SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; \
}
/**
* @brief Disables the MPU.
* @note MEMFAULENA is disabled in SCB_SHCSR.
*
* @api
*/
#define mpuDisable() { \
SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; \
MPU->CTRL = 0; \
}
/**
* @brief Configures an MPU region.
*
* @param[in] region the region number
* @param[in] address start address of the region, note, there are alignment
* constraints
* @param[in] attribs attributes mask as defined in @p MPU_RASR register
*
* @api
*/
#define mpuConfigureRegion(region, addr, attribs) { \
MPU->RNR = ((uint32_t)region); \
MPU->RBAR = ((uint32_t)addr); \
MPU->RASR = ((uint32_t)attribs); \
}
/*===========================================================================*/
/* External declarations. */
/*===========================================================================*/

3
readme.txt
View File

@ -85,7 +85,8 @@
driver.
- HAL: Introduced preliminary support for STM32F7xx devices.
- HAL: Introduced preliminary support for STM32L0xx devices.
- HAL: New STM32 shared DMAv2 driver supporting channel selection (F2, F4, F7).
- HAL: New STM32 shared DMAv2 driver supporting channel selection and
data cache invalidation (F2, F4, F7).
- HAL: New STM32 shared DMAv1 driver supporting channel selection and fixing
the behavior with shared IRQs (F0, L0).
- HAL: New STM32 ADCv2 driver supporting large STM32 devices (F2, F4, F7).

15
testhal/STM32/STM32F7xx/GPT-ADC-SPI-PWM-ICU/main.c
View File

@ -47,6 +47,11 @@ size_t nx = 0, ny = 0;
static void adccallback(ADCDriver *adcp, adcsample_t *buffer, size_t n) {
(void)adcp;
/* DMA buffer invalidation because data cache.*/
dmaBufferInvalidate(buffer, n * ADC_GRP1_NUM_CHANNELS);
/* Updating counters.*/
if (samples1 == buffer) {
nx += n;
}
@ -111,11 +116,6 @@ static THD_FUNCTION(Thread1, arg) {
*/
int main(void) {
SCB_InvalidateICache();
SCB_EnableICache();
SCB_InvalidateDCache();
SCB_EnableDCache();
/*
* System initializations.
* - HAL initialization, this also initializes the configured device drivers
@ -126,6 +126,11 @@ int main(void) {
halInit();
chSysInit();
SCB_InvalidateICache();
SCB_EnableICache();
SCB_InvalidateDCache();
SCB_EnableDCache();
/*
* Activates the serial driver 1 using the driver default configuration.
*/