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ChibiOS
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git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@2460 35acf78f-673a-0410-8e92-d51de3d6d3f4

This commit is contained in:
gdisirio 2010-12-05 12:18:15 +00:00
parent f650ce36c1
commit d8edc8d012
4 changed files with 21 additions and 9 deletions
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14
demos/ARMCM3-LPC1343-GCC/mcuconf.h
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@ -31,6 +31,11 @@
/* /*
* HAL driver system settings. * HAL driver system settings.
*/ */
#define LPC13xx_PLLCLK_SOURCE SYSPLLCLKSEL_SYSOSC
#define LPC13xx_SYSPLL_MUL 6
#define LPC13xx_SYSPLL_DIV 4
#define LPC13xx_MAINCLK_SOURCE SYSMAINCLKSEL_PLLOUT
#define LPC13xx_SYSABHCLK_DIV 1
/* /*
* ADC driver system settings. * ADC driver system settings.
@ -47,7 +52,16 @@
/* /*
* SERIAL driver system settings. * SERIAL driver system settings.
*/ */
#define LPC13xx_SERIAL_USE_UART0 TRUE
#define LPC13xx_SERIAL_FIFO_PRELOAD 16
#define LPC13xx_SERIAL_UART0CLKDIV 1
#define LPC13xx_SERIAL_UART0_IRQ_PRIORITY 3
/* /*
* SPI driver system settings. * SPI driver system settings.
*/ */
#define LPC13xx_SPI_USE_SSP0 TRUE
#define LPC13xx_SPI_SSP0CLKDIV 1
#define LPC13xx_SPI_SSP0_IRQ_PRIORITY 5
#define LPC13xx_SPI_SSP_ERROR_HOOK(spip) chSysHalt()
#define LPC13xx_SPI_SCK0_SELECTOR SCK0_IS_PIO2_11

3
os/hal/platforms/LPC11xx/spi_lld.h
View File

@ -37,7 +37,7 @@
/** /**
* @brief Hardware FIFO depth. * @brief Hardware FIFO depth.
*/ */
#define LPC11xx_SSP_FIFO_DEPTH 8 #define LPC11xx_SSP_FIFO_DEPTH 8
#define CR0_DSSMASK 0x0F #define CR0_DSSMASK 0x0F
#define CR0_DSS4BIT 3 #define CR0_DSS4BIT 3
@ -89,7 +89,6 @@
#define ICR_ROR 1 #define ICR_ROR 1
#define ICR_RT 2 #define ICR_RT 2
/** /**
* @brief SCK0 signal assigned to pin PIO0_10. * @brief SCK0 signal assigned to pin PIO0_10.
*/ */

10
os/hal/platforms/LPC13xx/hal_lld.h
View File

@ -61,7 +61,7 @@
* @brief System PLL clock source. * @brief System PLL clock source.
*/ */
#if !defined(LPC13xx_PLLCLK_SOURCE) || defined(__DOXYGEN__) #if !defined(LPC13xx_PLLCLK_SOURCE) || defined(__DOXYGEN__)
#define LPC13xx_PLLCLK_SOURCE SYSPLLCLKSEL_SYSOSC #define LPC13xx_PLLCLK_SOURCE SYSPLLCLKSEL_SYSOSC
#endif #endif
/** /**
@ -70,7 +70,7 @@
* must not exceed the CCO ratings. * must not exceed the CCO ratings.
*/ */
#if !defined(LPC13xx_SYSPLL_MUL) || defined(__DOXYGEN__) #if !defined(LPC13xx_SYSPLL_MUL) || defined(__DOXYGEN__)
#define LPC13xx_SYSPLL_MUL 6 #define LPC13xx_SYSPLL_MUL 6
#endif #endif
/** /**
@ -78,14 +78,14 @@
* @note The value must be chosen between (2, 4, 8, 16). * @note The value must be chosen between (2, 4, 8, 16).
*/ */
#if !defined(LPC13xx_SYSPLL_DIV) || defined(__DOXYGEN__) #if !defined(LPC13xx_SYSPLL_DIV) || defined(__DOXYGEN__)
#define LPC13xx_SYSPLL_DIV 4 #define LPC13xx_SYSPLL_DIV 4
#endif #endif
/** /**
* @brief System main clock source. * @brief System main clock source.
*/ */
#if !defined(LPC13xx_MAINCLK_SOURCE) || defined(__DOXYGEN__) #if !defined(LPC13xx_MAINCLK_SOURCE) || defined(__DOXYGEN__)
#define LPC13xx_MAINCLK_SOURCE SYSMAINCLKSEL_PLLOUT #define LPC13xx_MAINCLK_SOURCE SYSMAINCLKSEL_PLLOUT
#endif #endif
/** /**
@ -93,7 +93,7 @@
* @note The value must be chosen between (1...255). * @note The value must be chosen between (1...255).
*/ */
#if !defined(LPC13xx_SYSCLK_DIV) || defined(__DOXYGEN__) #if !defined(LPC13xx_SYSCLK_DIV) || defined(__DOXYGEN__)
#define LPC13xx_SYSABHCLK_DIV 1 #define LPC13xx_SYSABHCLK_DIV 1
#endif #endif
/*===========================================================================*/ /*===========================================================================*/

3
os/hal/platforms/LPC13xx/spi_lld.h
View File

@ -37,7 +37,7 @@
/** /**
* @brief Hardware FIFO depth. * @brief Hardware FIFO depth.
*/ */
#define LPC13xx_SSP_FIFO_DEPTH 8 #define LPC13xx_SSP_FIFO_DEPTH 8
#define CR0_DSSMASK 0x0F #define CR0_DSSMASK 0x0F
#define CR0_DSS4BIT 3 #define CR0_DSS4BIT 3
@ -89,7 +89,6 @@
#define ICR_ROR 1 #define ICR_ROR 1
#define ICR_RT 2 #define ICR_RT 2
/** /**
* @brief SCK0 signal assigned to pin PIO0_10. * @brief SCK0 signal assigned to pin PIO0_10.
*/ */