Fixed bug #951.
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@12054 110e8d01-0319-4d1e-a829-52ad28d1bb01
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@ -99,6 +99,7 @@ static const SerialConfig default_config =
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* @param[in] config the architecture-dependent serial driver configuration
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*/
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static void usart_init(SerialDriver *sdp, const SerialConfig *config) {
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uint32_t fck;
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USART_TypeDef *u = sdp->usart;
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/* Baud rate setting.*/
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@ -107,9 +108,16 @@ static void usart_init(SerialDriver *sdp, const SerialConfig *config) {
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#else
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if (sdp->usart == USART1)
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#endif
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u->BRR = STM32_PCLK2 / config->speed;
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fck = STM32_PCLK2 / config->speed;
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else
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u->BRR = STM32_PCLK1 / config->speed;
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fck = STM32_PCLK1 / config->speed;
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/* Correcting USARTDIV when oversampling by 8 instead of 16.
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Fraction is still 4 bits wide, but only lower 3 bits used.
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Mantissa is doubled, but Fraction is left the same.*/
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if (config->cr1 & USART_CR1_OVER8)
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fck = ((fck & ~7) * 2) | (fck & 7);
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u->BRR = fck;
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/* Note that some bits are enforced.*/
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u->CR2 = config->cr2 | USART_CR2_LBDIE;
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@ -196,6 +196,7 @@ static void usart_stop(UARTDriver *uartp) {
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* @param[in] uartp pointer to the @p UARTDriver object
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*/
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static void usart_start(UARTDriver *uartp) {
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uint32_t fck;
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uint16_t cr1;
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USART_TypeDef *u = uartp->usart;
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@ -208,9 +209,16 @@ static void usart_start(UARTDriver *uartp) {
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#else
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if (uartp->usart == USART1)
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#endif
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u->BRR = STM32_PCLK2 / uartp->config->speed;
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fck = STM32_PCLK2 / uartp->config->speed;
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else
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u->BRR = STM32_PCLK1 / uartp->config->speed;
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fck = STM32_PCLK1 / uartp->config->speed;
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/* Correcting USARTDIV when oversampling by 8 instead of 16.
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Fraction is still 4 bits wide, but only lower 3 bits used.
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Mantissa is doubled, but Fraction is left the same.*/
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if (uartp->config->cr1 & USART_CR1_OVER8)
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fck = ((fck & ~7) * 2) | (fck & 7);
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u->BRR = fck;
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/* Resetting eventual pending status flags.*/
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(void)u->SR; /* SR reset step 1.*/
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@ -213,17 +213,26 @@ static uint8_t sd_out_buflp1[STM32_SERIAL_LPUART1_OUT_BUF_SIZE];
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* @param[in] config the architecture-dependent serial driver configuration
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*/
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static void usart_init(SerialDriver *sdp, const SerialConfig *config) {
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uint32_t fck;
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USART_TypeDef *u = sdp->usart;
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/* Baud rate setting.*/
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#if STM32_SERIAL_USE_LPUART1
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if ( sdp == &LPSD1 )
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{
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u->BRR = (uint32_t)( ( (uint64_t)sdp->clock * 256 ) / config->speed);
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if ( sdp == &LPSD1 ) {
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fck = (uint32_t)(((uint64_t)sdp->clock * 256 ) / config->speed);
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}
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else
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#endif
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u->BRR = (uint32_t)(sdp->clock / config->speed);
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{
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fck = (uint32_t)(sdp->clock / config->speed);
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}
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/* Correcting USARTDIV when oversampling by 8 instead of 16.
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Fraction is still 4 bits wide, but only lower 3 bits used.
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Mantissa is doubled, but Fraction is left the same.*/
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if (config->cr1 & USART_CR1_OVER8)
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fck = ((fck & ~7) * 2) | (fck & 7);
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u->BRR = fck;
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/* Note that some bits are enforced.*/
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u->CR2 = config->cr2 | USART_CR2_LBDIE;
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@ -252,6 +252,7 @@ static void usart_stop(UARTDriver *uartp) {
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* @param[in] uartp pointer to the @p UARTDriver object
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*/
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static void usart_start(UARTDriver *uartp) {
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uint32_t fck;
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uint32_t cr1;
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const uint32_t tmo = uartp->config->timeout;
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USART_TypeDef *u = uartp->usart;
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@ -260,7 +261,14 @@ static void usart_start(UARTDriver *uartp) {
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usart_stop(uartp);
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/* Baud rate setting.*/
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u->BRR = (uint32_t)(uartp->clock / uartp->config->speed);
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fck = (uint32_t)(uartp->clock / uartp->config->speed);
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/* Correcting USARTDIV when oversampling by 8 instead of 16.
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Fraction is still 4 bits wide, but only lower 3 bits used.
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Mantissa is doubled, but Fraction is left the same.*/
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if (uartp->config->cr1 & USART_CR1_OVER8)
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fck = ((fck & ~7) * 2) | (fck & 7);
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u->BRR = fck;
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/* Resetting eventual pending status flags.*/
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u->ICR = 0xFFFFFFFFU;
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@ -126,6 +126,9 @@
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- EX: Updated LIS302DL to 1.1.0 (backported to 18.2.1).
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- EX: Updated LPS25H to 1.1.0 (backported to 18.2.1).
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- EX: Updated LSM303DLHC to 1.1.0 (backported to 18.2.1).
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- HAL: Fixed Invalid divider settings in Serial and UART STM32 drivers
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when USART_CR1_OVER8 is specified (bug #951)(backported to 18.2.2
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and 17.6.5).
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- NIL: Fixed missing extern declaration in IAR Cortex-M port (bug #950)
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(backported to 18.2.2 and 17.6.5).
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- HAL: Fixed ASCR register invalid handling in STM32 GPIOv3 driver (bug #949)
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