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Fixed bug 3436124. 

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/branches/stable_2.2.x@3687 35acf78f-673a-0410-8e92-d51de3d6d3f4
This commit is contained in:
gdisirio 2011-12-30 10:11:40 +00:00
parent a4d2ece8ab
commit d9911f12c0
4 changed files with 10 additions and 32 deletions
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8
docs/reports/STM32F103-72-GCC.txt
View File

@ -5,8 +5,8 @@ Settings: SYSCLK=72, ACR=0x12 (2 wait states)
*** ChibiOS/RT test suite
***
*** Kernel: 2.2.7
*** GCC Version: 4.6.0
*** Kernel: 2.2.8
*** GCC Version: 4.6.2
*** Architecture: ARMv7-M
*** Core Variant: Cortex-M3
*** Platform: STM32 Performance Line Medium Density
@ -114,11 +114,11 @@ Settings: SYSCLK=72, ACR=0x12 (2 wait states)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.5 (Benchmark, threads, full cycle)
--- Score : 161399 threads/S
--- Score : 159606 threads/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.6 (Benchmark, threads, create only)
--- Score : 240209 threads/S
--- Score : 236259 threads/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.7 (Benchmark, mass reschedule, 5 threads)

4
os/hal/platforms/STM32/spi_lld.c
View File

@ -304,10 +304,10 @@ void spi_lld_start(SPIDriver *spip) {
/* More DMA setup.*/
if ((spip->spd_config->spc_cr1 & SPI_CR1_DFF) == 0)
spip->spd_dmaccr = (STM32_SPI_SPI2_DMA_PRIORITY << 12) |
spip->spd_dmaccr = (STM32_SPI_SPI_DMA_PRIORITY << 12) |
DMA_CCR1_TEIE; /* 8 bits transfers. */
else
spip->spd_dmaccr = (STM32_SPI_SPI2_DMA_PRIORITY << 12) |
spip->spd_dmaccr = (STM32_SPI_SPI_DMA_PRIORITY << 12) |
DMA_CCR1_TEIE | DMA_CCR1_MSIZE_0 |
DMA_CCR1_PSIZE_0; /* 16 bits transfers. */

29
os/hal/platforms/STM32/spi_lld.h
View File

@ -73,33 +73,10 @@
#endif
/**
* @brief SPI1 DMA priority (0..3|lowest..highest).
* @note The priority level is used for both the TX and RX DMA channels but
* because of the channels ordering the RX channel has always priority
* over the TX channel.
* @brief Shared SPIs DMA priority (0..3|lowest..highest).
*/
#if !defined(STM32_SPI_SPI1_DMA_PRIORITY) || defined(__DOXYGEN__)
#define STM32_SPI_SPI1_DMA_PRIORITY 2
#endif
/**
* @brief SPI2 DMA priority (0..3|lowest..highest).
* @note The priority level is used for both the TX and RX DMA channels but
* because of the channels ordering the RX channel has always priority
* over the TX channel.
*/
#if !defined(STM32_SPI_SPI2_DMA_PRIORITY) || defined(__DOXYGEN__)
#define STM32_SPI_SPI2_DMA_PRIORITY 2
#endif
/**
* @brief SPI3 DMA priority (0..3|lowest..highest).
* @note The priority level is used for both the TX and RX DMA channels but
* because of the channels ordering the RX channel has always priority
* over the TX channel.
*/
#if !defined(STM32_SPI_SPI3_DMA_PRIORITY) || defined(__DOXYGEN__)
#define STM32_SPI_SPI3_DMA_PRIORITY 2
#if !defined(STM32_SPI_SPI_DMA_PRIORITY) || defined(__DOXYGEN__)
#define STM32_SPI_SPI_DMA_PRIORITY 2
#endif
/**

1
readme.txt
View File

@ -71,6 +71,7 @@
*** 2.2.8 ***
- NEW: Added new API chThdExitS() in order to allow atomic operations on
thead exit.
- FIX: Fixed DMA priority setting error in STM32 SPI driver (bug 3436124).
- FIX: Fixed broken support for UART5 in STM32 serial driver (bug 3434094).
- FIX: Fixed misplaced chRegSetThreadName() in ARM7-AT91SAM7S-FATFS-GCC demo
(bug 3411780).