diff --git a/demos/STM32/RT-STM32L552ZE-NUCLEO144-TEST/cfg/mcuconf.h b/demos/STM32/RT-STM32L552ZE-NUCLEO144-TEST/cfg/mcuconf.h
index 26d38d862..579621eaa 100644
--- a/demos/STM32/RT-STM32L552ZE-NUCLEO144-TEST/cfg/mcuconf.h
+++ b/demos/STM32/RT-STM32L552ZE-NUCLEO144-TEST/cfg/mcuconf.h
@@ -36,6 +36,11 @@
#define STM32L552_MCUCONF
#define STM32L562_MCUCONF
+/*
+ * Secure mode HAL settings.
+ */
+#define STM32_SECURE_MODE TRUE
+
/*
* HAL driver global settings.
*/
diff --git a/demos/STM32/RT-STM32L552ZE-NUCLEO144-TEST/cfg/secconf.h b/demos/STM32/RT-STM32L552ZE-NUCLEO144-TEST/cfg/secconf.h
new file mode 100644
index 000000000..ae5ea1cdc
--- /dev/null
+++ b/demos/STM32/RT-STM32L552ZE-NUCLEO144-TEST/cfg/secconf.h
@@ -0,0 +1,86 @@
+/*
+ ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/*
+ * STM32L5xx security configuration.
+ */
+
+#ifndef SECCONF_H
+#define SECCONF_H
+
+#define STM32L5xx_SECCONF
+#define STM32L552_SECCONF
+#define STM32L562_SECCONF
+
+/*
+ * Security flash settings.
+ */
+#define STM32_FLASH_OVERRIDE_SETTINGS TRUE
+#define STM32_FLASH_SECWM1R1 (STM32_FLASH_SECWM_START(0x00) | STM32_FLASH_SECWM_END(0x1F))
+#define STM32_FLASH_SECWM2R1 (STM32_FLASH_SECWM_START(0x00) | STM32_FLASH_SECWM_END(0x1F))
+#define STM32_FLASH_SECBB1R1 0x00000000
+#define STM32_FLASH_SECBB1R2 0x00000000
+#define STM32_FLASH_SECBB1R3 0x00000000
+#define STM32_FLASH_SECBB1R4 0x00000000
+#define STM32_FLASH_SECBB2R1 0x00000000
+#define STM32_FLASH_SECBB2R2 0x00000000
+#define STM32_FLASH_SECBB2R3 0x00000000
+#define STM32_FLASH_SECBB2R4 0x00000000
+
+/*
+ * Security RAM settings.
+ * VCTR: 256b per bit.
+ * LCKVTR: 8kB per bit.
+ */
+#define STM32_MPCBB1_CR (GTZC_MPCBB_CR_SRWILADIS_Msk | GTZC_MPCBB_CR_LCK_Msk)
+#define STM32_MPCBB1_LCKVTR1 0x00000000
+#define STM32_MPCBB1_VCTR0 0xFFFFFFFF
+#define STM32_MPCBB1_VCTR1 0xFFFFFFFF
+#define STM32_MPCBB1_VCTR2 0xFFFFFFFF
+#define STM32_MPCBB1_VCTR3 0xFFFFFFFF
+#define STM32_MPCBB1_VCTR4 0x00000000
+#define STM32_MPCBB1_VCTR5 0x00000000
+#define STM32_MPCBB1_VCTR6 0x00000000
+#define STM32_MPCBB1_VCTR7 0x00000000
+#define STM32_MPCBB1_VCTR8 0x00000000
+#define STM32_MPCBB1_VCTR9 0x00000000
+#define STM32_MPCBB1_VCTR10 0x00000000
+#define STM32_MPCBB1_VCTR11 0x00000000
+#define STM32_MPCBB1_VCTR12 0x00000000
+#define STM32_MPCBB1_VCTR13 0x00000000
+#define STM32_MPCBB1_VCTR14 0x00000000
+#define STM32_MPCBB1_VCTR15 0x00000000
+#define STM32_MPCBB1_VCTR16 0x00000000
+#define STM32_MPCBB1_VCTR17 0x00000000
+#define STM32_MPCBB1_VCTR18 0x00000000
+#define STM32_MPCBB1_VCTR19 0x00000000
+#define STM32_MPCBB1_VCTR20 0x00000000
+#define STM32_MPCBB1_VCTR21 0x00000000
+#define STM32_MPCBB1_VCTR22 0x00000000
+#define STM32_MPCBB1_VCTR23 0x00000000
+
+#define STM32_MPCBB2_CR (GTZC_MPCBB_CR_SRWILADIS_Msk | GTZC_MPCBB_CR_LCK_Msk)
+#define STM32_MPCBB2_LCKVTR1 0x00000000
+#define STM32_MPCBB2_VCTR0 0x00000000
+#define STM32_MPCBB2_VCTR1 0x00000000
+#define STM32_MPCBB2_VCTR2 0x00000000
+#define STM32_MPCBB2_VCTR3 0x00000000
+#define STM32_MPCBB2_VCTR4 0x00000000
+#define STM32_MPCBB2_VCTR5 0x00000000
+#define STM32_MPCBB2_VCTR6 0x00000000
+#define STM32_MPCBB2_VCTR7 0x00000000
+
+#endif /* SECCONF_H */
diff --git a/demos/STM32/RT-STM32L552ZE-NUCLEO144-TEST/debug/RT-STM32L552ZE-NUCLEO144-TEST (ST-Link GDB Server, Flash and Run).launch b/demos/STM32/RT-STM32L552ZE-NUCLEO144-TEST/debug/RT-STM32L552ZE-NUCLEO144-TEST (ST-Link GDB Server, Flash and Run).launch
index 781c15460..abcab07d8 100644
--- a/demos/STM32/RT-STM32L552ZE-NUCLEO144-TEST/debug/RT-STM32L552ZE-NUCLEO144-TEST (ST-Link GDB Server, Flash and Run).launch
+++ b/demos/STM32/RT-STM32L552ZE-NUCLEO144-TEST/debug/RT-STM32L552ZE-NUCLEO144-TEST (ST-Link GDB Server, Flash and Run).launch
@@ -33,9 +33,9 @@
-
+
-
+
diff --git a/os/common/ports/ARMv8-M-ML/chcore.h b/os/common/ports/ARMv8-M-ML/chcore.h
index 467d1dbb0..354bf3a1d 100644
--- a/os/common/ports/ARMv8-M-ML/chcore.h
+++ b/os/common/ports/ARMv8-M-ML/chcore.h
@@ -253,23 +253,6 @@
#error "invalid CORTEX_FAST_PRIORITIES value specified"
#endif
-/**
- * @brief SVCALL handler priority.
- */
-#define CORTEX_PRIORITY_SVCALL (CORTEX_MAXIMUM_PRIORITY + \
- CORTEX_FAST_PRIORITIES)
-
-/**
- * @brief Maximum usable priority for normal ISRs.
- * @note Must be lower than @p CORTEX_PRIORITY_SVCALL.
- */
-#define CORTEX_MAX_KERNEL_PRIORITY (CORTEX_PRIORITY_SVCALL + 1)
-
-/**
- * @brief BASEPRI level within kernel lock.
- */
-#define CORTEX_BASEPRI_KERNEL CORTEX_PRIO_MASK(CORTEX_MAX_KERNEL_PRIORITY)
-
#if PORT_KERNEL_MODE == PORT_KERNEL_MODE_NORMAL
/**
* @brief EXC_RETURN to be used when starting a thread.
@@ -291,6 +274,12 @@
*/
#define CORTEX_BASEPRI_DISABLED CORTEX_PRIO_MASK(0)
+/**
+ * @brief SVCALL handler priority.
+ */
+#define CORTEX_PRIORITY_SVCALL (CORTEX_MAXIMUM_PRIORITY + \
+ CORTEX_FAST_PRIORITIES)
+
/**
* @brief PENDSV handler priority.
*/
@@ -307,17 +296,33 @@
#endif
#define PORT_INFO "Secure host mode"
#define CORTEX_BASEPRI_DISABLED CORTEX_PRIO_MASK(CORTEX_MINIMUM_PRIORITY)
+#define CORTEX_PRIORITY_SVCALL (CORTEX_MAXIMUM_PRIORITY + \
+ CORTEX_FAST_PRIORITIES)
#define CORTEX_PRIORITY_PENDSV (CORTEX_MINIMUM_PRIORITY / 2)
#elif PORT_KERNEL_MODE == PORT_KERNEL_MODE_GUEST
#define PORT_EXC_RETURN 0xFFFFFFBC
#define PORT_CONTEXT_RESERVED_SIZE (sizeof (struct port_intctx))
#define PORT_INFO "Non-secure guest mode"
+#define CORTEX_BASEPRI_DISABLED CORTEX_PRIO_MASK(0)
+#define CORTEX_PRIORITY_SVCALL ((CORTEX_MAXIMUM_PRIORITY + \
+#define CORTEX_PRIORITY_PENDSV (CORTEX_MINIMUM_PRIORITY & 0xFFFFFFFE)
#else
#error "invalid kernel security mode"
#endif
+/**
+ * @brief Maximum usable priority for normal ISRs.
+ * @note Must be lower than @p CORTEX_PRIORITY_SVCALL.
+ */
+#define CORTEX_MAX_KERNEL_PRIORITY (CORTEX_PRIORITY_SVCALL + 1)
+
+/**
+ * @brief BASEPRI level within kernel lock.
+ */
+#define CORTEX_BASEPRI_KERNEL CORTEX_PRIO_MASK(CORTEX_MAX_KERNEL_PRIORITY)
+
/**
* @name Port information
* @{
diff --git a/os/hal/ports/STM32/LLD/ICACHEv1/stm32_icache.inc b/os/hal/ports/STM32/LLD/ICACHEv1/stm32_icache.inc
index 522da376f..c24aacdcb 100644
--- a/os/hal/ports/STM32/LLD/ICACHEv1/stm32_icache.inc
+++ b/os/hal/ports/STM32/LLD/ICACHEv1/stm32_icache.inc
@@ -35,7 +35,7 @@
#define STM32_HAS_ICACHE FALSE
#endif
-#if STM32_HAS_PLL
+#if STM32_HAS_ICACHE
/* Checks on configurations.*/
#if !defined(STM32_ICACHE_CR)
@@ -108,6 +108,6 @@ static inline void icache_deinit(void) {
/* Driver exported functions. */
/*===========================================================================*/
-#endif /* STM32_HAS_PLL */
+#endif /* STM32_HAS_ICACHE */
/** @} */
diff --git a/os/hal/ports/STM32/STM32L5xx/hal_lld.h b/os/hal/ports/STM32/STM32L5xx/hal_lld.h
index 70344e0fc..fa29306c1 100644
--- a/os/hal/ports/STM32/STM32L5xx/hal_lld.h
+++ b/os/hal/ports/STM32/STM32L5xx/hal_lld.h
@@ -806,6 +806,9 @@
#include "stm32_hsi48.inc"
#include "stm32_hse.inc"
+/* Secure mode handler.*/
+#include "stm32_secure.inc"
+
/*
* Platform HSI16-related checks.
*/
diff --git a/os/hal/ports/STM32/STM32L5xx/stm32_secure.inc b/os/hal/ports/STM32/STM32L5xx/stm32_secure.inc
new file mode 100644
index 000000000..45a15af56
--- /dev/null
+++ b/os/hal/ports/STM32/STM32L5xx/stm32_secure.inc
@@ -0,0 +1,320 @@
+/*
+ ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file STM32L5xx/stm32_secure.inc
+ * @brief Secure mode handler.
+ *
+ * @addtogroup STM32_SECURE_HANDLER
+ * @{
+ */
+
+/*===========================================================================*/
+/* Driver local definitions. */
+/*===========================================================================*/
+
+/**
+ * @name FLASH_SECWMn registers bits definitions
+ * @{
+ */
+#define STM32_FLASH_SECWM_START(n) ((n) << 0)
+#define STM32_FLASH_SECWM_END(n) ((n) << 16)
+/** @} */
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+/* Registry checks for robustness.*/
+#if !defined(STM32_SECURE_MODE)
+#define STM32_SECURE_MODE FALSE
+#endif
+
+#if STM32_SECURE_MODE
+
+/* Configuration data inclusion.*/
+#include "secconf.h"
+
+/* Checks on configurations.*/
+#if !defined(STM32_FLASH_OVERRIDE_SETTINGS)
+#error "STM32_FLASH_OVERRIDE_SETTINGS not defined in secconf.h"
+#endif
+
+#if !defined(STM32_FLASH_SECWM1R1)
+#error "STM32_FLASH_SECWM1R1 not defined in secconf.h"
+#endif
+
+#if !defined(STM32_FLASH_SECWM2R1)
+#error "STM32_FLASH_SECWM2R1 not defined in secconf.h"
+#endif
+
+#if !defined(STM32_FLASH_SECBB1R1)
+#error "STM32_FLASH_SECBB1R1 not defined in secconf.h"
+#endif
+
+#if !defined(STM32_FLASH_SECBB1R2)
+#error "STM32_FLASH_SECBB1R2 not defined in secconf.h"
+#endif
+
+#if !defined(STM32_FLASH_SECBB1R3)
+#error "STM32_FLASH_SECBB1R3 not defined in secconf.h"
+#endif
+
+#if !defined(STM32_FLASH_SECBB1R4)
+#error "STM32_FLASH_SECBB1R4 not defined in secconf.h"
+#endif
+
+#if !defined(STM32_FLASH_SECBB2R1)
+#error "STM32_FLASH_SECBB2R1 not defined in secconf.h"
+#endif
+
+#if !defined(STM32_FLASH_SECBB2R2)
+#error "STM32_FLASH_SECBB2R2 not defined in secconf.h"
+#endif
+
+#if !defined(STM32_FLASH_SECBB2R3)
+#error "STM32_FLASH_SECBB2R3 not defined in secconf.h"
+#endif
+
+#if !defined(STM32_FLASH_SECBB2R4)
+#error "STM32_FLASH_SECBB2R4 not defined in secconf.h"
+#endif
+
+#if !defined(STM32_MPCBB1_CR)
+#error "STM32_MPCBB1_CR not defined in secconf.h"
+#endif
+
+#if !defined(STM32_MPCBB1_LCKVTR1)
+#error "STM32_MPCBB1_LCKVTR1 not defined in secconf.h"
+#endif
+
+#if !defined(STM32_MPCBB1_VCTR0)
+#error "STM32_MPCBB1_VCTR0 not defined in secconf.h"
+#endif
+
+#if !defined(STM32_MPCBB1_VCTR1)
+#error "STM32_MPCBB1_VCTR1 not defined in secconf.h"
+#endif
+
+#if !defined(STM32_MPCBB1_VCTR2)
+#error "STM32_MPCBB1_VCTR2 not defined in secconf.h"
+#endif
+
+#if !defined(STM32_MPCBB1_VCTR3)
+#error "STM32_MPCBB1_VCTR3 not defined in secconf.h"
+#endif
+
+#if !defined(STM32_MPCBB1_VCTR4)
+#error "STM32_MPCBB1_VCTR4 not defined in secconf.h"
+#endif
+
+#if !defined(STM32_MPCBB1_VCTR5)
+#error "STM32_MPCBB1_VCTR5 not defined in secconf.h"
+#endif
+
+#if !defined(STM32_MPCBB1_VCTR6)
+#error "STM32_MPCBB1_VCTR6 not defined in secconf.h"
+#endif
+
+#if !defined(STM32_MPCBB1_VCTR7)
+#error "STM32_MPCBB1_VCTR7 not defined in secconf.h"
+#endif
+
+#if !defined(STM32_MPCBB1_VCTR8)
+#error "STM32_MPCBB1_VCTR8 not defined in secconf.h"
+#endif
+
+#if !defined(STM32_MPCBB1_VCTR9)
+#error "STM32_MPCBB1_VCTR9 not defined in secconf.h"
+#endif
+
+#if !defined(STM32_MPCBB1_VCTR10)
+#error "STM32_MPCBB1_VCTR10 not defined in secconf.h"
+#endif
+
+#if !defined(STM32_MPCBB1_VCTR11)
+#error "STM32_MPCBB1_VCTR11 not defined in secconf.h"
+#endif
+
+#if !defined(STM32_MPCBB1_VCTR12)
+#error "STM32_MPCBB1_VCTR12 not defined in secconf.h"
+#endif
+
+#if !defined(STM32_MPCBB1_VCTR13)
+#error "STM32_MPCBB1_VCTR13 not defined in secconf.h"
+#endif
+
+#if !defined(STM32_MPCBB1_VCTR14)
+#error "STM32_MPCBB1_VCTR14 not defined in secconf.h"
+#endif
+
+#if !defined(STM32_MPCBB1_VCTR15)
+#error "STM32_MPCBB1_VCTR15 not defined in secconf.h"
+#endif
+
+#if !defined(STM32_MPCBB1_VCTR16)
+#error "STM32_MPCBB1_VCTR16 not defined in secconf.h"
+#endif
+
+#if !defined(STM32_MPCBB1_VCTR17)
+#error "STM32_MPCBB1_VCTR17 not defined in secconf.h"
+#endif
+
+#if !defined(STM32_MPCBB1_VCTR18)
+#error "STM32_MPCBB1_VCTR18 not defined in secconf.h"
+#endif
+
+#if !defined(STM32_MPCBB1_VCTR19)
+#error "STM32_MPCBB1_VCTR19 not defined in secconf.h"
+#endif
+
+#if !defined(STM32_MPCBB1_VCTR20)
+#error "STM32_MPCBB1_VCTR20 not defined in secconf.h"
+#endif
+
+#if !defined(STM32_MPCBB1_VCTR21)
+#error "STM32_MPCBB1_VCTR21 not defined in secconf.h"
+#endif
+
+#if !defined(STM32_MPCBB1_VCTR22)
+#error "STM32_MPCBB1_VCTR22 not defined in secconf.h"
+#endif
+
+#if !defined(STM32_MPCBB1_VCTR23)
+#error "STM32_MPCBB1_VCTR23 not defined in secconf.h"
+#endif
+
+#if !defined(STM32_MPCBB2_CR)
+#error "STM32_MPCBB2_CR not defined in secconf.h"
+#endif
+
+#if !defined(STM32_MPCBB2_LCKVTR1)
+#error "STM32_MPCBB2_LCKVTR1 not defined in secconf.h"
+#endif
+
+#if !defined(STM32_MPCBB2_VCTR0)
+#error "STM32_MPCBB2_VCTR0 not defined in secconf.h"
+#endif
+
+#if !defined(STM32_MPCBB2_VCTR1)
+#error "STM32_MPCBB2_VCTR1 not defined in secconf.h"
+#endif
+
+#if !defined(STM32_MPCBB2_VCTR2)
+#error "STM32_MPCBB2_VCTR2 not defined in secconf.h"
+#endif
+
+#if !defined(STM32_MPCBB2_VCTR3)
+#error "STM32_MPCBB2_VCTR3 not defined in secconf.h"
+#endif
+
+#if !defined(STM32_MPCBB2_VCTR4)
+#error "STM32_MPCBB2_VCTR4 not defined in secconf.h"
+#endif
+
+#if !defined(STM32_MPCBB2_VCTR5)
+#error "STM32_MPCBB2_VCTR5 not defined in secconf.h"
+#endif
+
+#if !defined(STM32_MPCBB2_VCTR6)
+#error "STM32_MPCBB2_VCTR6 not defined in secconf.h"
+#endif
+
+#if !defined(STM32_MPCBB2_VCTR7)
+#error "STM32_MPCBB2_VCTR7 not defined in secconf.h"
+#endif
+
+/* Check on limits.*/
+
+#endif /* STM32_SECURE_MODE */
+
+/*===========================================================================*/
+/* Driver exported variables. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local variables. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local functions. */
+/*===========================================================================*/
+
+static inline void secure_init(void) {
+
+#if STM32_SECURE_MODE
+#if STM32_FLASH_OVERRIDE_SETTINGS
+ FLASH->SECWM1R1 = STM32_FLASH_SECWM1R1;
+ FLASH->SECWM2R1 = STM32_FLASH_SECWM2R1;
+ FLASH->SECBB1R1 = STM32_FLASH_SECBB1R1;
+ FLASH->SECBB1R2 = STM32_FLASH_SECBB1R2;
+ FLASH->SECBB1R3 = STM32_FLASH_SECBB1R3;
+ FLASH->SECBB1R4 = STM32_FLASH_SECBB1R4;
+ FLASH->SECBB2R1 = STM32_FLASH_SECBB2R1;
+ FLASH->SECBB2R2 = STM32_FLASH_SECBB2R2;
+ FLASH->SECBB2R3 = STM32_FLASH_SECBB2R3;
+ FLASH->SECBB2R4 = STM32_FLASH_SECBB2R4;
+#endif
+
+ GTZC_MPCBB1->VCTR[0] = STM32_MPCBB1_VCTR0;
+ GTZC_MPCBB1->VCTR[1] = STM32_MPCBB1_VCTR1;
+ GTZC_MPCBB1->VCTR[2] = STM32_MPCBB1_VCTR2;
+ GTZC_MPCBB1->VCTR[3] = STM32_MPCBB1_VCTR3;
+ GTZC_MPCBB1->VCTR[4] = STM32_MPCBB1_VCTR4;
+ GTZC_MPCBB1->VCTR[5] = STM32_MPCBB1_VCTR5;
+ GTZC_MPCBB1->VCTR[6] = STM32_MPCBB1_VCTR6;
+ GTZC_MPCBB1->VCTR[7] = STM32_MPCBB1_VCTR7;
+ GTZC_MPCBB1->VCTR[8] = STM32_MPCBB1_VCTR8;
+ GTZC_MPCBB1->VCTR[9] = STM32_MPCBB1_VCTR9;
+ GTZC_MPCBB1->VCTR[10] = STM32_MPCBB1_VCTR10;
+ GTZC_MPCBB1->VCTR[11] = STM32_MPCBB1_VCTR11;
+ GTZC_MPCBB1->VCTR[12] = STM32_MPCBB1_VCTR12;
+ GTZC_MPCBB1->VCTR[13] = STM32_MPCBB1_VCTR13;
+ GTZC_MPCBB1->VCTR[14] = STM32_MPCBB1_VCTR14;
+ GTZC_MPCBB1->VCTR[15] = STM32_MPCBB1_VCTR15;
+ GTZC_MPCBB1->VCTR[16] = STM32_MPCBB1_VCTR16;
+ GTZC_MPCBB1->VCTR[17] = STM32_MPCBB1_VCTR17;
+ GTZC_MPCBB1->VCTR[18] = STM32_MPCBB1_VCTR18;
+ GTZC_MPCBB1->VCTR[19] = STM32_MPCBB1_VCTR19;
+ GTZC_MPCBB1->VCTR[20] = STM32_MPCBB1_VCTR20;
+ GTZC_MPCBB1->VCTR[21] = STM32_MPCBB1_VCTR21;
+ GTZC_MPCBB1->VCTR[22] = STM32_MPCBB1_VCTR22;
+ GTZC_MPCBB1->VCTR[23] = STM32_MPCBB1_VCTR23;
+ GTZC_MPCBB1->LCKVTR1 = STM32_MPCBB1_LCKVTR1;
+ GTZC_MPCBB1->CR = STM32_MPCBB1_CR;
+
+ GTZC_MPCBB2->VCTR[0] = STM32_MPCBB2_VCTR0;
+ GTZC_MPCBB2->VCTR[1] = STM32_MPCBB2_VCTR1;
+ GTZC_MPCBB2->VCTR[2] = STM32_MPCBB2_VCTR2;
+ GTZC_MPCBB2->VCTR[3] = STM32_MPCBB2_VCTR3;
+ GTZC_MPCBB2->VCTR[4] = STM32_MPCBB2_VCTR4;
+ GTZC_MPCBB2->VCTR[5] = STM32_MPCBB2_VCTR5;
+ GTZC_MPCBB2->VCTR[6] = STM32_MPCBB2_VCTR6;
+ GTZC_MPCBB2->VCTR[7] = STM32_MPCBB2_VCTR7;
+ GTZC_MPCBB2->LCKVTR1 = STM32_MPCBB2_LCKVTR1;
+ GTZC_MPCBB2->CR = STM32_MPCBB2_CR;
+#endif
+}
+
+/*===========================================================================*/
+/* Driver interrupt handlers. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported functions. */
+/*===========================================================================*/
+
+/** @} */