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ChibiOS
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L4 and L4+ clock tree improvements. 

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@13241 27425a3e-05d8-49a3-a47f-9c15f0e5edd8
This commit is contained in:
Giovanni Di Sirio 2019-12-31 08:40:16 +00:00
parent e28cb50773
commit d9deb746f3
16 changed files with 315 additions and 23 deletions
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4
demos/STM32/RT-STM32L4R5ZI-NUCLEO144/cfg/mcuconf.h
View File

@ -81,6 +81,7 @@
#define STM32_PLLSAI2P_VALUE 7
#define STM32_PLLSAI2Q_VALUE 6
#define STM32_PLLSAI2R_VALUE 6
#define STM32_PLLSAI2DIVR STM32_PLLSAI2DIVR_DIV16
/*
* Peripherals clock sources.
@ -94,6 +95,7 @@
#define STM32_I2C1SEL STM32_I2C1SEL_SYSCLK
#define STM32_I2C2SEL STM32_I2C2SEL_SYSCLK
#define STM32_I2C3SEL STM32_I2C3SEL_SYSCLK
#define STM32_I2C4SEL STM32_I2C4SEL_SYSCLK
#define STM32_LPTIM1SEL STM32_LPTIM1SEL_PCLK1
#define STM32_LPTIM2SEL STM32_LPTIM2SEL_PCLK1
#define STM32_CLK48SEL STM32_CLK48SEL_PLLSAI1
@ -103,7 +105,7 @@
#define STM32_SAI1SEL STM32_SAI1SEL_OFF
#define STM32_SAI2SEL STM32_SAI2SEL_OFF
#define STM32_DSISEL STM32_DSISEL_DSIPHY
#define STM32_SDMMC STM32_SDMMCSEL_48CLK
#define STM32_SDMMCSEL STM32_SDMMCSEL_48CLK
#define STM32_OSPISEL STM32_OSPISEL_SYSCLK
#define STM32_RTCSEL STM32_RTCSEL_LSI

4
demos/STM32/RT-STM32L4R9-DISCOVERY/cfg/mcuconf.h
View File

@ -81,6 +81,7 @@
#define STM32_PLLSAI2P_VALUE 7
#define STM32_PLLSAI2Q_VALUE 6
#define STM32_PLLSAI2R_VALUE 6
#define STM32_PLLSAI2DIVR STM32_PLLSAI2DIVR_DIV16
/*
* Peripherals clock sources.
@ -94,6 +95,7 @@
#define STM32_I2C1SEL STM32_I2C1SEL_SYSCLK
#define STM32_I2C2SEL STM32_I2C2SEL_SYSCLK
#define STM32_I2C3SEL STM32_I2C3SEL_SYSCLK
#define STM32_I2C4SEL STM32_I2C4SEL_SYSCLK
#define STM32_LPTIM1SEL STM32_LPTIM1SEL_PCLK1
#define STM32_LPTIM2SEL STM32_LPTIM2SEL_PCLK1
#define STM32_CLK48SEL STM32_CLK48SEL_PLLSAI1
@ -103,7 +105,7 @@
#define STM32_SAI1SEL STM32_SAI1SEL_OFF
#define STM32_SAI2SEL STM32_SAI2SEL_OFF
#define STM32_DSISEL STM32_DSISEL_DSIPHY
#define STM32_SDMMC STM32_SDMMCSEL_48CLK
#define STM32_SDMMCSEL STM32_SDMMCSEL_48CLK
#define STM32_OSPISEL STM32_OSPISEL_SYSCLK
#define STM32_RTCSEL STM32_RTCSEL_LSI

22
os/hal/ports/STM32/STM32L4xx+/hal_lld.c
View File

@ -315,21 +315,29 @@ void stm32_clock_init(void) {
RCC->CFGR = STM32_MCOPRE | STM32_MCOSEL | STM32_STOPWUCK |
STM32_PPRE2 | STM32_PPRE1 | STM32_HPRE;
/* CCIPR register initialization, note, must take care of the _OFF
/* CCIPR register initialization.*/
{
uint32_t ccipr = STM32_ADCSEL |
STM32_CLK48SEL | STM32_LPTIM2SEL | STM32_LPTIM1SEL |
STM32_I2C3SEL | STM32_I2C2SEL | STM32_I2C1SEL |
STM32_LPUART1SEL | STM32_UART5SEL | STM32_UART4SEL |
STM32_USART3SEL | STM32_USART2SEL | STM32_USART1SEL;
RCC->CCIPR = ccipr;
}
/* CCIPR2 register initialization, note, must take care of the _OFF
pseudo settings.*/
{
uint32_t ccipr = STM32_DFSDMSEL | STM32_ADCSEL |
STM32_CLK48SEL | STM32_LPTIM2SEL | STM32_LPTIM1SEL |
STM32_I2C3SEL | STM32_I2C2SEL | STM32_I2C1SEL |
STM32_UART5SEL | STM32_UART4SEL | STM32_USART3SEL |
STM32_USART2SEL | STM32_USART1SEL | STM32_LPUART1SEL;
uint32_t ccipr = STM32_OSPISEL | STM32_PLLSAI2DIVR |
STM32_SDMMCSEL | STM32_DSISEL | STM32_ADFSDMSEL |
STM32_DFSDMSEL | STM32_I2C4SEL;
#if STM32_SAI2SEL != STM32_SAI2SEL_OFF
ccipr |= STM32_SAI2SEL;
#endif
#if STM32_SAI1SEL != STM32_SAI1SEL_OFF
ccipr |= STM32_SAI1SEL;
#endif
RCC->CCIPR = ccipr;
RCC->CCIPR2 = ccipr;
}
/* Set flash WS's for SYSCLK source */

191
os/hal/ports/STM32/STM32L4xx+/hal_lld.h
View File

@ -671,6 +671,13 @@
#define STM32_PLLSAI2R_VALUE 6
#endif
/**
* @brief PLLSAI2DIVR value.
*/
#if !defined(STM32_PLLSAI2DIVR) || defined(__DOXYGEN__)
#define STM32_PLLSAI2DIVR STM32_PLLSAI2DIVR_DIV16
#endif
/**
* @brief USART1 clock source.
*/
@ -807,8 +814,8 @@
/**
* @brief SDMMC value (SDMMC clock source).
*/
#if !defined(STM32_SDMMC) || defined(__DOXYGEN__)
#define STM32_SDMMC STM32_SDMMCSEL_48CLK
#if !defined(STM32_SDMMCSEL) || defined(__DOXYGEN__)
#define STM32_SDMMCSEL STM32_SDMMCSEL_48CLK
#endif
/**
@ -1151,6 +1158,9 @@
#if (STM32_I2C3SEL == STM32_I2C3SEL_HSI16)
#error "HSI16 not enabled, required by I2C3SEL"
#endif
#if (STM32_I2C4SEL == STM32_I2C4SEL_HSI16)
#error "HSI16 not enabled, required by I2C4SEL"
#endif
#if (STM32_LPTIM1SEL == STM32_LPTIM1SEL_HSI16)
#error "HSI16 not enabled, required by LPTIM1SEL"
@ -2100,12 +2110,16 @@
*/
#if (STM32_USART1SEL == STM32_USART1SEL_PCLK2) || defined(__DOXYGEN__)
#define STM32_USART1CLK STM32_PCLK2
#elif STM32_USART1SEL == STM32_USART1SEL_SYSCLK
#define STM32_USART1CLK STM32_SYSCLK
#elif STM32_USART1SEL == STM32_USART1SEL_HSI16
#define STM32_USART1CLK STM32_HSI16CLK
#elif STM32_USART1SEL == STM32_USART1SEL_LSE
#define STM32_USART1CLK STM32_LSECLK
#else
#error "invalid source selected for USART1 clock"
#endif
@ -2115,12 +2129,16 @@
*/
#if (STM32_USART2SEL == STM32_USART2SEL_PCLK1) || defined(__DOXYGEN__)
#define STM32_USART2CLK STM32_PCLK1
#elif STM32_USART2SEL == STM32_USART2SEL_SYSCLK
#define STM32_USART2CLK STM32_SYSCLK
#elif STM32_USART2SEL == STM32_USART2SEL_HSI16
#define STM32_USART2CLK STM32_HSI16CLK
#elif STM32_USART2SEL == STM32_USART2SEL_LSE
#define STM32_USART2CLK STM32_LSECLK
#else
#error "invalid source selected for USART2 clock"
#endif
@ -2130,12 +2148,16 @@
*/
#if (STM32_USART3SEL == STM32_USART3SEL_PCLK1) || defined(__DOXYGEN__)
#define STM32_USART3CLK STM32_PCLK1
#elif STM32_USART3SEL == STM32_USART3SEL_SYSCLK
#define STM32_USART3CLK STM32_SYSCLK
#elif STM32_USART3SEL == STM32_USART3SEL_HSI16
#define STM32_USART3CLK STM32_HSI16CLK
#elif STM32_USART3SEL == STM32_USART3SEL_LSE
#define STM32_USART3CLK STM32_LSECLK
#else
#error "invalid source selected for USART3 clock"
#endif
@ -2145,12 +2167,16 @@
*/
#if (STM32_UART4SEL == STM32_UART4SEL_PCLK1) || defined(__DOXYGEN__)
#define STM32_UART4CLK STM32_PCLK1
#elif STM32_UART4SEL == STM32_UART4SEL_SYSCLK
#define STM32_UART4CLK STM32_SYSCLK
#elif STM32_UART4SEL == STM32_UART4SEL_HSI16
#define STM32_UART4CLK STM32_HSI16CLK
#elif STM32_UART4SEL == STM32_UART4SEL_LSE
#define STM32_UART4CLK STM32_LSECLK
#else
#error "invalid source selected for UART4 clock"
#endif
@ -2160,12 +2186,16 @@
*/
#if (STM32_UART5SEL == STM32_UART5SEL_PCLK1) || defined(__DOXYGEN__)
#define STM32_UART5CLK STM32_PCLK1
#elif STM32_UART5SEL == STM32_UART5SEL_SYSCLK
#define STM32_UART5CLK STM32_SYSCLK
#elif STM32_UART5SEL == STM32_UART5SEL_HSI16
#define STM32_UART5CLK STM32_HSI16CLK
#elif STM32_UART5SEL == STM32_UART5SEL_LSE
#define STM32_UART5CLK STM32_LSECLK
#else
#error "invalid source selected for UART5 clock"
#endif
@ -2175,12 +2205,16 @@
*/
#if (STM32_LPUART1SEL == STM32_LPUART1SEL_PCLK1) || defined(__DOXYGEN__)
#define STM32_LPUART1CLK STM32_PCLK1
#elif STM32_LPUART1SEL == STM32_LPUART1SEL_SYSCLK
#define STM32_LPUART1CLK STM32_SYSCLK
#elif STM32_LPUART1SEL == STM32_LPUART1SEL_HSI16
#define STM32_LPUART1CLK STM32_HSI16CLK
#elif STM32_LPUART1SEL == STM32_LPUART1SEL_LSE
#define STM32_LPUART1CLK STM32_LSECLK
#else
#error "invalid source selected for LPUART1 clock"
#endif
@ -2190,10 +2224,13 @@
*/
#if (STM32_I2C1SEL == STM32_I2C1SEL_PCLK1) || defined(__DOXYGEN__)
#define STM32_I2C1CLK STM32_PCLK1
#elif STM32_I2C1SEL == STM32_I2C1SEL_SYSCLK
#define STM32_I2C1CLK STM32_SYSCLK
#elif STM32_I2C1SEL == STM32_I2C1SEL_HSI16
#define STM32_I2C1CLK STM32_HSI16CLK
#else
#error "invalid source selected for I2C1 clock"
#endif
@ -2203,10 +2240,13 @@
*/
#if (STM32_I2C2SEL == STM32_I2C2SEL_PCLK1) || defined(__DOXYGEN__)
#define STM32_I2C2CLK STM32_PCLK1
#elif STM32_I2C2SEL == STM32_I2C2SEL_SYSCLK
#define STM32_I2C2CLK STM32_SYSCLK
#elif STM32_I2C2SEL == STM32_I2C2SEL_HSI16
#define STM32_I2C2CLK STM32_HSI16CLK
#else
#error "invalid source selected for I2C2 clock"
#endif
@ -2216,25 +2256,48 @@
*/
#if (STM32_I2C3SEL == STM32_I2C3SEL_PCLK1) || defined(__DOXYGEN__)
#define STM32_I2C3CLK STM32_PCLK1
#elif STM32_I2C3SEL == STM32_I2C3SEL_SYSCLK
#define STM32_I2C3CLK STM32_SYSCLK
#elif STM32_I2C3SEL == STM32_I2C3SEL_HSI16
#define STM32_I2C3CLK STM32_HSI16CLK
#else
#error "invalid source selected for I2C3 clock"
#endif
/**
* @brief I2C4 clock frequency.
*/
#if (STM32_I2C4SEL == STM32_I2C4SEL_PCLK1) || defined(__DOXYGEN__)
#define STM32_I2C4CLK STM32_PCLK1
#elif STM32_I2C4SEL == STM32_I2C4SEL_SYSCLK
#define STM32_I2C4CLK STM32_SYSCLK
#elif STM32_I2C4SEL == STM32_I2C4SEL_HSI16
#define STM32_I2C4CLK STM32_HSI16CLK
#else
#error "invalid source selected for I2C4 clock"
#endif
/**
* @brief LPTIM1 clock frequency.
*/
#if (STM32_LPTIM1SEL == STM32_LPTIM1SEL_PCLK1) || defined(__DOXYGEN__)
#define STM32_LPTIM1CLK STM32_PCLK1
#elif STM32_LPTIM1SEL == STM32_LPTIM1SEL_LSI
#define STM32_LPTIM1CLK STM32_LSICLK
#elif STM32_LPTIM1SEL == STM32_LPTIM1SEL_HSI16
#define STM32_LPTIM1CLK STM32_HSI16CLK
#elif STM32_LPTIM1SEL == STM32_LPTIM1SEL_LSE
#define STM32_LPTIM1CLK STM32_LSECLK
#else
#error "invalid source selected for LPTIM1 clock"
#endif
@ -2244,12 +2307,16 @@
*/
#if (STM32_LPTIM2SEL == STM32_LPTIM2SEL_PCLK1) || defined(__DOXYGEN__)
#define STM32_LPTIM2CLK STM32_PCLK1
#elif STM32_LPTIM2SEL == STM32_LPTIM2SEL_LSI
#define STM32_LPTIM2CLK STM32_LSICLK
#elif STM32_LPTIM2SEL == STM32_LPTIM2SEL_HSI16
#define STM32_LPTIM2CLK STM32_HSI16CLK
#elif STM32_LPTIM2SEL == STM32_LPTIM2SEL_LSE
#define STM32_LPTIM2CLK STM32_LSECLK
#else
#error "invalid source selected for LPTIM2 clock"
#endif
@ -2259,16 +2326,96 @@
*/
#if (STM32_CLK48SEL == STM32_CLK48SEL_HSI48) || defined(__DOXYGEN__)
#define STM32_48CLK STM32_HSI48CLK
#elif STM32_CLK48SEL == STM32_CLK48SEL_PLLSAI1
#define STM32_48CLK (STM32_PLLSAI1VCO / STM32_PLLSAI1Q_VALUE)
#elif STM32_CLK48SEL == STM32_CLK48SEL_PLL
#define STM32_48CLK (STM32_PLLVCO / STM32_PLLQ_VALUE)
#elif STM32_CLK48SEL == STM32_CLK48SEL_MSI
#define STM32_48CLK STM32_MSICLK
#else
#error "invalid source selected for 48CLK clock"
#endif
/**
* @brief SAI1 clock frequency.
*/
#if (STM32_SAI1SEL == STM32_SAI1SEL_PLLSAI1) || defined(__DOXYGEN__)
#define STM32_SAI1CLK STM32_PLLSAI1_P_CLKOUT
#elif STM32_SAI1SEL == STM32_SAI1SEL_PLLSAI2
#define STM32_SAI1CLK STM32_PLLSAI2_P_CLKOUT
#elif STM32_SAI1SEL == STM32_SAI1SEL_PLL
#define STM32_SAI1CLK STM32_PLL_P_CLKOUT
#elif STM32_SAI1SEL == STM32_SAI1SEL_EXTCLK
#define STM32_SAI1CLK 0 /* Unknown, would require a board value */
#elif STM32_SAI1SEL == STM32_SAI1SEL_HSI16
#define STM32_SAI1CLK STM32_HSI16CLK
#elif STM32_SAI1SEL == STM32_SAI1SEL_OFF
#define STM32_SAI1CLK 0
#else
#error "invalid source selected for SAI1 clock"
#endif
/**
* @brief SAI2 clock frequency.
*/
#if (STM32_SAI2SEL == STM32_SAI2SEL_PLLSAI1) || defined(__DOXYGEN__)
#define STM32_SAI2CLK STM32_PLLSAI1_P_CLKOUT
#elif STM32_SAI2SEL == STM32_SAI2SEL_PLLSAI2
#define STM32_SAI2CLK STM32_PLLSAI2_P_CLKOUT
#elif STM32_SAI2SEL == STM32_SAI2SEL_PLL
#define STM32_SAI2CLK STM32_PLL_P_CLKOUT
#elif STM32_SAI2SEL == STM32_SAI2SEL_EXTCLK
#define STM32_SAI2CLK 0 /* Unknown, would require a board value */
#elif STM32_SAI2SEL == STM32_SAI2SEL_HSI16
#define STM32_SAI2CLK STM32_HSI16CLK
#elif STM32_SAI2SEL == STM32_SAI2SEL_OFF
#define STM32_SAI2CLK 0
#else
#error "invalid source selected for SAI2 clock"
#endif
/**
* @brief DSI clock frequency.
*/
#if (STM32_DSISEL == STM32_DSISEL_DSIPHY) || defined(__DOXYGEN__)
#define STM32_DSICLK 0
#elif STM32_DSISEL == STM32_DSISEL_PLLDSICLK
#define STM32_DSICLK STM32_PLLSAI2_Q_CLKOUT
#else
#error "invalid source selected for DSI clock"
#endif
/**
* @brief SDMMC clock frequency.
*/
#if (STM32_SDMMCSEL == STM32_SDMMCSEL_48CLK) || defined(__DOXYGEN__)
#define STM32_SDMMCCLK STM32_48CLK
#elif STM32_SDMMCSEL == STM32_SDMMCSEL_PLLSAI3CLK
#define STM32_SDMMCCLK STM32_PLL_P_CLKOUT
#else
#error "invalid source selected for SDMMC clock"
#endif
/**
* @brief USB clock point.
*/
@ -2284,10 +2431,13 @@
*/
#if (STM32_ADCSEL == STM32_ADCSEL_NOCLK) || defined(__DOXYGEN__)
#define STM32_ADCCLK 0
#elif STM32_ADCSEL == STM32_ADCSEL_PLLSAI1
#define STM32_ADCCLK STM32_PLLSAI1_R_CLKOUT
#elif STM32_ADCSEL == STM32_ADCSEL_SYSCLK
#define STM32_ADCCLK STM32_SYSCLK
#else
#error "invalid source selected for ADC clock"
#endif
@ -2297,8 +2447,10 @@
*/
#if (STM32_DFSDMSEL == STM32_DFSDMSEL_PCLK2) || defined(__DOXYGEN__)
#define STM32_DFSDMCLK STM32_PCLK2
#elif STM32_DFSDMSEL == STM32_DFSDMSEL_SYSCLK
#define STM32_DFSDMCLK STM32_SYSCLK
#else
#error "invalid source selected for DFSDM clock"
#endif
@ -2308,6 +2460,41 @@
*/
#define STM32_SDMMC1CLK STM32_48CLK
/**
* @brief LTDC frequency.
*/
#if (STM32_PLLSAI2DIVR == STM32_PLLSAI2DIVR_DIV2) || defined(__DOXYGEN__)
#define STM32_LTDCCLK (STM32_PLLSAI2_R_CLKOUT / 2)
#elif STM32_PLLSAI2DIVR == STM32_PLLSAI2DIVR_DIV4
#define STM32_LTDCCLK (STM32_PLLSAI2_R_CLKOUT / 4)
#elif STM32_PLLSAI2DIVR == STM32_PLLSAI2DIVR_DIV8
#define STM32_LTDCCLK (STM32_PLLSAI2_R_CLKOUT / 8)
#elif STM32_PLLSAI2DIVR == STM32_PLLSAI2DIVR_DIV16
#define STM32_LTDCCLK (STM32_PLLSAI2_R_CLKOUT / 16)
#else
#error "invalid STM32_PLLSAI2DIVR value specified"
#endif
/**
* @brief OSPI clock frequency.
*/
#if (STM32_OSPISEL == STM32_OSPISEL_SYSCLK) || defined(__DOXYGEN__)
#define STM32_OSPICLK STM32_SYSCLK
#elif STM32_OSPISEL == STM32_OSPISEL_MSI
#define STM32_OSPICLK STM32_MSICLK
#elif STM32_OSPISEL == STM32_OSPISEL_48CLK
#define STM32_OSPICLK STM32_PLLSAI1_Q_CLKOUT
#else
#error "invalid source selected for OSPI clock"
#endif
/**
* @brief Clock of timers connected to APB1
*/

8
os/hal/ports/STM32/STM32L4xx/hal_lld.c
View File

@ -350,6 +350,14 @@ void stm32_clock_init(void) {
RCC->CCIPR = ccipr;
}
#if STM32_HAS_I2C4
/* CCIPR2 register initialization.*/
{
uint32_t ccipr2 = STM32_I2C4SEL;
RCC->CCIPR2 = ccipr2;
}
#endif
/* Set flash WS's for SYSCLK source */
if (STM32_FLASHBITS > STM32_MSI_FLASHBITS) {
FLASH->ACR = (FLASH->ACR & ~FLASH_ACR_LATENCY_Msk) | STM32_FLASHBITS;

67
os/hal/ports/STM32/STM32L4xx/hal_lld.h
View File

@ -295,6 +295,16 @@
#define STM32_DFSDMSEL_SYSCLK (1 << 31) /**< DFSDM source is SYSCLK. */
/** @} */
/**
* @name RCC_CCIPR2 register bits definitions
* @{
*/
#define STM32_I2C4SEL_MASK (3 << 0) /**< I2C1SEL mask. */
#define STM32_I2C4SEL_PCLK1 (0 << 0) /**< I2C1 source is PCLK1. */
#define STM32_I2C4SEL_SYSCLK (1 << 0) /**< I2C1 source is SYSCLK. */
#define STM32_I2C4SEL_HSI16 (2 << 0) /**< I2C1 source is HSI16. */
/** @} */
/**
* @name RCC_BDCR register bits definitions
* @{
@ -683,6 +693,13 @@
#define STM32_I2C3SEL STM32_I2C3SEL_SYSCLK
#endif
/**
* @brief I2C4 clock source.
*/
#if !defined(STM32_I2C4SEL) || defined(__DOXYGEN__)
#define STM32_I2C4SEL STM32_I2C4SEL_SYSCLK
#endif
/**
* @brief LPTIM1 clock source.
*/
@ -1065,6 +1082,9 @@
#if (STM32_I2C3SEL == STM32_I2C3SEL_HSI16)
#error "HSI16 not enabled, required by I2C3SEL"
#endif
#if (STM32_I2C4SEL == STM32_I2C4SEL_HSI16)
#error "HSI16 not enabled, required by I2C4SEL"
#endif
#if (STM32_LPTIM1SEL == STM32_LPTIM1SEL_HSI16)
#error "HSI16 not enabled, required by LPTIM1SEL"
@ -2075,6 +2095,19 @@
#error "invalid source selected for I2C3 clock"
#endif
/**
* @brief I2C4 clock frequency.
*/
#if (STM32_I2C4SEL == STM32_I2C4SEL_PCLK1) || defined(__DOXYGEN__)
#define STM32_I2C4CLK STM32_PCLK1
#elif STM32_I2C4SEL == STM32_I2C4SEL_SYSCLK
#define STM32_I2C4CLK STM32_SYSCLK
#elif STM32_I2C4SEL == STM32_I2C4SEL_HSI16
#define STM32_I2C4CLK STM32_HSI16CLK
#else
#error "invalid source selected for I2C4 clock"
#endif
/**
* @brief LPTIM1 clock frequency.
*/
@ -2138,6 +2171,40 @@
#endif /* STM32_CLOCK_HAS_HSI48 */
/**
* @brief SAI1 clock frequency.
*/
#if (STM32_SAI1SEL == STM32_SAI1SEL_PLLSAI1) || defined(__DOXYGEN__)
#define STM32_SAI1CLK STM32_PLLSAI1_P_CLKOUT
#elif STM32_SAI1SEL == STM32_SAI1SEL_PLLSAI2
#define STM32_SAI1CLK STM32_PLLSAI2_P_CLKOUT
#elif STM32_SAI1SEL == STM32_SAI1SEL_PLL
#define STM32_SAI1CLK STM32_PLL_P_CLKOUT
#elif STM32_SAI1SEL == STM32_SAI1SEL_EXTCLK
#define STM32_SAI1CLK 0 /* Unknown, would require a board value */
#elif STM32_SAI1SEL == STM32_SAI1SEL_OFF
#define STM32_SAI1CLK 0
#else
#error "invalid source selected for SAI1 clock"
#endif
/**
* @brief SAI2 clock frequency.
*/
#if (STM32_SAI2SEL == STM32_SAI2SEL_PLLSAI1) || defined(__DOXYGEN__)
#define STM32_SAI2CLK STM32_PLLSAI1_P_CLKOUT
#elif STM32_SAI2SEL == STM32_SAI2SEL_PLLSAI2
#define STM32_SAI2CLK STM32_PLLSAI2_P_CLKOUT
#elif STM32_SAI2SEL == STM32_SAI2SEL_PLL
#define STM32_SAI2CLK STM32_PLL_P_CLKOUT
#elif STM32_SAI2SEL == STM32_SAI2SEL_EXTCLK
#define STM32_SAI2CLK 0 /* Unknown, would require a board value */
#elif STM32_SAI2SEL == STM32_SAI2SEL_OFF
#define STM32_SAI2CLK 0
#else
#error "invalid source selected for SAI2 clock"
#endif
/**
* @brief USB clock point.
*/

6
os/hal/ports/STM32/STM32L4xx/stm32_registry.h
View File

@ -627,7 +627,7 @@
#define STM32_I2C3_TX_DMA_CHN 0x00000030
#define STM32_HAS_I2C4 TRUE
#define STM32_I2C4_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 1))
#define STM32_I2C4_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 2))
#define STM32_I2C4_RX_DMA_CHN 0x00000000
#define STM32_I2C4_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 1))
#define STM32_I2C4_TX_DMA_CHN 0x00000000
@ -1171,9 +1171,9 @@
#define STM32_I2C3_TX_DMA_CHN 0x00000030
#define STM32_HAS_I2C4 TRUE
#define STM32_I2C4_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 1))
#define STM32_I2C4_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 2))
#define STM32_I2C4_RX_DMA_CHN 0x00000000
#define STM32_I2C4_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 2))
#define STM32_I2C4_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 1))
#define STM32_I2C4_TX_DMA_CHN 0x00000000
/* QUADSPI attributes.*/

4
testhal/STM32/multi/ADC/cfg/stm32l4r5zi_nucleo144/mcuconf.h
View File

@ -81,6 +81,7 @@
#define STM32_PLLSAI2P_VALUE 7
#define STM32_PLLSAI2Q_VALUE 6
#define STM32_PLLSAI2R_VALUE 6
#define STM32_PLLSAI2DIVR STM32_PLLSAI2DIVR_DIV16
/*
* Peripherals clock sources.
@ -94,6 +95,7 @@
#define STM32_I2C1SEL STM32_I2C1SEL_SYSCLK
#define STM32_I2C2SEL STM32_I2C2SEL_SYSCLK
#define STM32_I2C3SEL STM32_I2C3SEL_SYSCLK
#define STM32_I2C4SEL STM32_I2C4SEL_SYSCLK
#define STM32_LPTIM1SEL STM32_LPTIM1SEL_PCLK1
#define STM32_LPTIM2SEL STM32_LPTIM2SEL_PCLK1
#define STM32_CLK48SEL STM32_CLK48SEL_PLLSAI1
@ -103,7 +105,7 @@
#define STM32_SAI1SEL STM32_SAI1SEL_OFF
#define STM32_SAI2SEL STM32_SAI2SEL_OFF
#define STM32_DSISEL STM32_DSISEL_DSIPHY
#define STM32_SDMMC STM32_SDMMCSEL_48CLK
#define STM32_SDMMCSEL STM32_SDMMCSEL_48CLK
#define STM32_OSPISEL STM32_OSPISEL_SYSCLK
#define STM32_RTCSEL STM32_RTCSEL_LSI

4
testhal/STM32/multi/DAC/cfg/stm32l4r5zi_nucleo144/mcuconf.h
View File

@ -81,6 +81,7 @@
#define STM32_PLLSAI2P_VALUE 7
#define STM32_PLLSAI2Q_VALUE 6
#define STM32_PLLSAI2R_VALUE 6
#define STM32_PLLSAI2DIVR STM32_PLLSAI2DIVR_DIV16
/*
* Peripherals clock sources.
@ -94,6 +95,7 @@
#define STM32_I2C1SEL STM32_I2C1SEL_SYSCLK
#define STM32_I2C2SEL STM32_I2C2SEL_SYSCLK
#define STM32_I2C3SEL STM32_I2C3SEL_SYSCLK
#define STM32_I2C4SEL STM32_I2C4SEL_SYSCLK
#define STM32_LPTIM1SEL STM32_LPTIM1SEL_PCLK1
#define STM32_LPTIM2SEL STM32_LPTIM2SEL_PCLK1
#define STM32_CLK48SEL STM32_CLK48SEL_PLLSAI1
@ -103,7 +105,7 @@
#define STM32_SAI1SEL STM32_SAI1SEL_OFF
#define STM32_SAI2SEL STM32_SAI2SEL_OFF
#define STM32_DSISEL STM32_DSISEL_DSIPHY
#define STM32_SDMMC STM32_SDMMCSEL_48CLK
#define STM32_SDMMCSEL STM32_SDMMCSEL_48CLK
#define STM32_OSPISEL STM32_OSPISEL_SYSCLK
#define STM32_RTCSEL STM32_RTCSEL_LSI

4
testhal/STM32/multi/RTC/cfg/stm32l4r5_nucleo144/mcuconf.h
View File

@ -81,6 +81,7 @@
#define STM32_PLLSAI2P_VALUE 7
#define STM32_PLLSAI2Q_VALUE 6
#define STM32_PLLSAI2R_VALUE 6
#define STM32_PLLSAI2DIVR STM32_PLLSAI2DIVR_DIV16
/*
* Peripherals clock sources.
@ -94,6 +95,7 @@
#define STM32_I2C1SEL STM32_I2C1SEL_SYSCLK
#define STM32_I2C2SEL STM32_I2C2SEL_SYSCLK
#define STM32_I2C3SEL STM32_I2C3SEL_SYSCLK
#define STM32_I2C4SEL STM32_I2C4SEL_SYSCLK
#define STM32_LPTIM1SEL STM32_LPTIM1SEL_PCLK1
#define STM32_LPTIM2SEL STM32_LPTIM2SEL_PCLK1
#define STM32_CLK48SEL STM32_CLK48SEL_PLLSAI1
@ -103,7 +105,7 @@
#define STM32_SAI1SEL STM32_SAI1SEL_OFF
#define STM32_SAI2SEL STM32_SAI2SEL_OFF
#define STM32_DSISEL STM32_DSISEL_DSIPHY
#define STM32_SDMMC STM32_SDMMCSEL_48CLK
#define STM32_SDMMCSEL STM32_SDMMCSEL_48CLK
#define STM32_OSPISEL STM32_OSPISEL_SYSCLK
#define STM32_RTCSEL STM32_RTCSEL_LSI

4
testhal/STM32/multi/SPI/cfg/stm32l4r5_nucleo144/mcuconf.h
View File

@ -81,6 +81,7 @@
#define STM32_PLLSAI2P_VALUE 7
#define STM32_PLLSAI2Q_VALUE 6
#define STM32_PLLSAI2R_VALUE 6
#define STM32_PLLSAI2DIVR STM32_PLLSAI2DIVR_DIV16
/*
* Peripherals clock sources.
@ -94,6 +95,7 @@
#define STM32_I2C1SEL STM32_I2C1SEL_SYSCLK
#define STM32_I2C2SEL STM32_I2C2SEL_SYSCLK
#define STM32_I2C3SEL STM32_I2C3SEL_SYSCLK
#define STM32_I2C4SEL STM32_I2C4SEL_SYSCLK
#define STM32_LPTIM1SEL STM32_LPTIM1SEL_PCLK1
#define STM32_LPTIM2SEL STM32_LPTIM2SEL_PCLK1
#define STM32_CLK48SEL STM32_CLK48SEL_PLLSAI1
@ -103,7 +105,7 @@
#define STM32_SAI1SEL STM32_SAI1SEL_OFF
#define STM32_SAI2SEL STM32_SAI2SEL_OFF
#define STM32_DSISEL STM32_DSISEL_DSIPHY
#define STM32_SDMMC STM32_SDMMCSEL_48CLK
#define STM32_SDMMCSEL STM32_SDMMCSEL_48CLK
#define STM32_OSPISEL STM32_OSPISEL_SYSCLK
#define STM32_RTCSEL STM32_RTCSEL_LSI

4
testhal/STM32/multi/SPI/cfg/stm32l4r9_discovery/mcuconf.h
View File

@ -81,6 +81,7 @@
#define STM32_PLLSAI2P_VALUE 7
#define STM32_PLLSAI2Q_VALUE 6
#define STM32_PLLSAI2R_VALUE 6
#define STM32_PLLSAI2DIVR STM32_PLLSAI2DIVR_DIV16
/*
* Peripherals clock sources.
@ -94,6 +95,7 @@
#define STM32_I2C1SEL STM32_I2C1SEL_SYSCLK
#define STM32_I2C2SEL STM32_I2C2SEL_SYSCLK
#define STM32_I2C3SEL STM32_I2C3SEL_SYSCLK
#define STM32_I2C4SEL STM32_I2C4SEL_SYSCLK
#define STM32_LPTIM1SEL STM32_LPTIM1SEL_PCLK1
#define STM32_LPTIM2SEL STM32_LPTIM2SEL_PCLK1
#define STM32_CLK48SEL STM32_CLK48SEL_PLLSAI1
@ -103,7 +105,7 @@
#define STM32_SAI1SEL STM32_SAI1SEL_OFF
#define STM32_SAI2SEL STM32_SAI2SEL_OFF
#define STM32_DSISEL STM32_DSISEL_DSIPHY
#define STM32_SDMMC STM32_SDMMCSEL_48CLK
#define STM32_SDMMCSEL STM32_SDMMCSEL_48CLK
#define STM32_OSPISEL STM32_OSPISEL_SYSCLK
#define STM32_RTCSEL STM32_RTCSEL_LSI

4
testhal/STM32/multi/TRNG/cfg/stm32l4r5zi_nucleo144/mcuconf.h
View File

@ -81,6 +81,7 @@
#define STM32_PLLSAI2P_VALUE 7
#define STM32_PLLSAI2Q_VALUE 6
#define STM32_PLLSAI2R_VALUE 6
#define STM32_PLLSAI2DIVR STM32_PLLSAI2DIVR_DIV16
/*
* Peripherals clock sources.
@ -94,6 +95,7 @@
#define STM32_I2C1SEL STM32_I2C1SEL_SYSCLK
#define STM32_I2C2SEL STM32_I2C2SEL_SYSCLK
#define STM32_I2C3SEL STM32_I2C3SEL_SYSCLK
#define STM32_I2C4SEL STM32_I2C4SEL_SYSCLK
#define STM32_LPTIM1SEL STM32_LPTIM1SEL_PCLK1
#define STM32_LPTIM2SEL STM32_LPTIM2SEL_PCLK1
#define STM32_CLK48SEL STM32_CLK48SEL_PLLSAI1
@ -103,7 +105,7 @@
#define STM32_SAI1SEL STM32_SAI1SEL_OFF
#define STM32_SAI2SEL STM32_SAI2SEL_OFF
#define STM32_DSISEL STM32_DSISEL_DSIPHY
#define STM32_SDMMC STM32_SDMMCSEL_48CLK
#define STM32_SDMMCSEL STM32_SDMMCSEL_48CLK
#define STM32_OSPISEL STM32_OSPISEL_SYSCLK
#define STM32_RTCSEL STM32_RTCSEL_LSI

4
testhal/STM32/multi/USB_CDC/cfg/stm32l4r5_nucleo144/mcuconf.h
View File

@ -81,6 +81,7 @@
#define STM32_PLLSAI2P_VALUE 7
#define STM32_PLLSAI2Q_VALUE 6
#define STM32_PLLSAI2R_VALUE 6
#define STM32_PLLSAI2DIVR STM32_PLLSAI2DIVR_DIV16
/*
* Peripherals clock sources.
@ -94,6 +95,7 @@
#define STM32_I2C1SEL STM32_I2C1SEL_SYSCLK
#define STM32_I2C2SEL STM32_I2C2SEL_SYSCLK
#define STM32_I2C3SEL STM32_I2C3SEL_SYSCLK
#define STM32_I2C4SEL STM32_I2C4SEL_SYSCLK
#define STM32_LPTIM1SEL STM32_LPTIM1SEL_PCLK1
#define STM32_LPTIM2SEL STM32_LPTIM2SEL_PCLK1
#define STM32_CLK48SEL STM32_CLK48SEL_PLLSAI1
@ -103,7 +105,7 @@
#define STM32_SAI1SEL STM32_SAI1SEL_OFF
#define STM32_SAI2SEL STM32_SAI2SEL_OFF
#define STM32_DSISEL STM32_DSISEL_DSIPHY
#define STM32_SDMMC STM32_SDMMCSEL_48CLK
#define STM32_SDMMCSEL STM32_SDMMCSEL_48CLK
#define STM32_OSPISEL STM32_OSPISEL_SYSCLK
#define STM32_RTCSEL STM32_RTCSEL_LSI

4
testhal/STM32/multi/WSPI-MFS/cfg/stm32l4r9_discovery/mcuconf.h
View File

@ -81,6 +81,7 @@
#define STM32_PLLSAI2P_VALUE 7
#define STM32_PLLSAI2Q_VALUE 6
#define STM32_PLLSAI2R_VALUE 6
#define STM32_PLLSAI2DIVR STM32_PLLSAI2DIVR_DIV16
/*
* Peripherals clock sources.
@ -94,6 +95,7 @@
#define STM32_I2C1SEL STM32_I2C1SEL_SYSCLK
#define STM32_I2C2SEL STM32_I2C2SEL_SYSCLK
#define STM32_I2C3SEL STM32_I2C3SEL_SYSCLK
#define STM32_I2C4SEL STM32_I2C4SEL_SYSCLK
#define STM32_LPTIM1SEL STM32_LPTIM1SEL_PCLK1
#define STM32_LPTIM2SEL STM32_LPTIM2SEL_PCLK1
#define STM32_CLK48SEL STM32_CLK48SEL_PLLSAI1
@ -103,7 +105,7 @@
#define STM32_SAI1SEL STM32_SAI1SEL_OFF
#define STM32_SAI2SEL STM32_SAI2SEL_OFF
#define STM32_DSISEL STM32_DSISEL_DSIPHY
#define STM32_SDMMC STM32_SDMMCSEL_48CLK
#define STM32_SDMMCSEL STM32_SDMMCSEL_48CLK
#define STM32_OSPISEL STM32_OSPISEL_SYSCLK
#define STM32_RTCSEL STM32_RTCSEL_LSI

4
tools/ftl/processors/conf/mcuconf_stm32l4rxxx/mcuconf.h.ftl
View File

@ -92,6 +92,7 @@
#define STM32_PLLSAI2P_VALUE ${doc.STM32_PLLSAI2P_VALUE!"7"}
#define STM32_PLLSAI2Q_VALUE ${doc.STM32_PLLSAI2Q_VALUE!"6"}
#define STM32_PLLSAI2R_VALUE ${doc.STM32_PLLSAI2R_VALUE!"6"}
#define STM32_PLLSAI2DIVR ${doc.STM32_PLLSAI2DIVR!"STM32_PLLSAI2DIVR_DIV16"}
/*
* Peripherals clock sources.
@ -105,6 +106,7 @@
#define STM32_I2C1SEL ${doc.STM32_I2C1SEL!"STM32_I2C1SEL_SYSCLK"}
#define STM32_I2C2SEL ${doc.STM32_I2C2SEL!"STM32_I2C2SEL_SYSCLK"}
#define STM32_I2C3SEL ${doc.STM32_I2C3SEL!"STM32_I2C3SEL_SYSCLK"}
#define STM32_I2C4SEL ${doc.STM32_I2C4SEL!"STM32_I2C4SEL_SYSCLK"}
#define STM32_LPTIM1SEL ${doc.STM32_LPTIM1SEL!"STM32_LPTIM1SEL_PCLK1"}
#define STM32_LPTIM2SEL ${doc.STM32_LPTIM2SEL!"STM32_LPTIM2SEL_PCLK1"}
#define STM32_CLK48SEL ${doc.STM32_CLK48SEL!"STM32_CLK48SEL_PLLSAI1"}
@ -114,7 +116,7 @@
#define STM32_SAI1SEL ${doc.STM32_SAI1SEL!"STM32_SAI1SEL_OFF"}
#define STM32_SAI2SEL ${doc.STM32_SAI2SEL!"STM32_SAI2SEL_OFF"}
#define STM32_DSISEL ${doc.STM32_DSISEL!"STM32_DSISEL_DSIPHY"}
#define STM32_SDMMC ${doc.STM32_SDMMC!"STM32_SDMMCSEL_48CLK"}
#define STM32_SDMMCSEL ${doc.STM32_SDMMC!"STM32_SDMMCSEL_48CLK"}
#define STM32_OSPISEL ${doc.STM32_OSPISEL!"STM32_OSPISEL_SYSCLK"}
#define STM32_RTCSEL ${doc.STM32_RTCSEL!"STM32_RTCSEL_LSI"}