git-svn-id: svn://svn.code.sf.net/p/chibios/svn/branches/kernel_3_dev@6153 35acf78f-673a-0410-8e92-d51de3d6d3f4
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@ -593,10 +593,12 @@ void gpt_lld_start(GPTDriver *gptp) {
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"invalid frequency");
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/* Timer configuration.*/
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gptp->tim->CR1 = 0; /* Initially stopped. */
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gptp->tim->CR2 = STM32_TIM_CR2_CCDS; /* DMA on UE (if any). */
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gptp->tim->PSC = psc; /* Prescaler value. */
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gptp->tim->DIER = 0;
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gptp->tim->CR1 = 0; /* Initially stopped. */
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gptp->tim->CR2 = STM32_TIM_CR2_CCDS; /* DMA on UE (if any). */
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gptp->tim->PSC = psc; /* Prescaler value. */
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gptp->tim->DIER = gptp->config->dier & /* DMA-related DIER bits. */
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STM32_TIM_DIER_IRQ_MASK;
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gptp->tim->SR = 0; /* Clear pending IRQs. */
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}
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/**
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@ -609,9 +611,9 @@ void gpt_lld_start(GPTDriver *gptp) {
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void gpt_lld_stop(GPTDriver *gptp) {
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if (gptp->state == GPT_READY) {
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gptp->tim->CR1 = 0; /* Timer disabled. */
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gptp->tim->DIER = 0; /* All IRQs disabled. */
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gptp->tim->SR = 0; /* Clear eventual pending IRQs. */
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gptp->tim->CR1 = 0; /* Timer disabled. */
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gptp->tim->DIER = 0; /* All IRQs disabled. */
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gptp->tim->SR = 0; /* Clear pending IRQs. */
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#if STM32_GPT_USE_TIM1
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if (&GPTD1 == gptp) {
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@ -698,16 +700,16 @@ void gpt_lld_stop(GPTDriver *gptp) {
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*/
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void gpt_lld_start_timer(GPTDriver *gptp, gptcnt_t interval) {
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gptp->tim->ARR = interval - 1; /* Time constant. */
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gptp->tim->EGR = STM32_TIM_EGR_UG; /* Update event. */
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gptp->tim->CNT = 0; /* Reset counter. */
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gptp->tim->ARR = (uint32_t)(interval - 1); /* Time constant. */
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gptp->tim->EGR = STM32_TIM_EGR_UG; /* Update event. */
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gptp->tim->CNT = 0; /* Reset counter. */
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/* NOTE: After generating the UG event it takes several clock cycles before
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SR bit 0 goes to 1. This is because the clearing of CNT has been inserted
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before the clearing of SR, to give it some time.*/
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gptp->tim->SR = 0; /* Clear pending IRQs (if any). */
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gptp->tim->DIER = STM32_TIM_DIER_UIE; /* Update Event IRQ enabled. */
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gptp->tim->CR1 = STM32_TIM_CR1_URS | STM32_TIM_CR1_CEN;
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gptp->tim->SR = 0; /* Clear pending IRQs. */
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gptp->tim->DIER |= STM32_TIM_DIER_UIE; /* Update Event IRQ enabled.*/
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gptp->tim->CR1 = STM32_TIM_CR1_URS | STM32_TIM_CR1_CEN;
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}
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/**
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@ -719,9 +721,11 @@ void gpt_lld_start_timer(GPTDriver *gptp, gptcnt_t interval) {
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*/
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void gpt_lld_stop_timer(GPTDriver *gptp) {
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gptp->tim->CR1 = 0; /* Initially stopped. */
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gptp->tim->SR = 0; /* Clear pending IRQs (if any). */
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gptp->tim->DIER = 0; /* Interrupts disabled. */
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gptp->tim->CR1 = 0; /* Initially stopped. */
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gptp->tim->SR = 0; /* Clear pending IRQs. */
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/* All interrupts disabled.*/
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gptp->tim->DIER &= ~STM32_TIM_DIER_IRQ_MASK;
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}
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/**
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@ -737,9 +741,9 @@ void gpt_lld_stop_timer(GPTDriver *gptp) {
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*/
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void gpt_lld_polled_delay(GPTDriver *gptp, gptcnt_t interval) {
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gptp->tim->ARR = interval - 1; /* Time constant. */
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gptp->tim->EGR = STM32_TIM_EGR_UG; /* Update event. */
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gptp->tim->SR = 0; /* Clear pending IRQs (if any). */
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gptp->tim->ARR = (uint32_t)(interval - 1); /* Time constant. */
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gptp->tim->EGR = STM32_TIM_EGR_UG; /* Update event. */
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gptp->tim->SR = 0; /* Clear pending IRQs. */
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gptp->tim->CR1 = STM32_TIM_CR1_OPM | STM32_TIM_CR1_URS | STM32_TIM_CR1_CEN;
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while (!(gptp->tim->SR & STM32_TIM_SR_UIF))
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;
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@ -367,7 +367,7 @@ typedef uint32_t gptfreq_t;
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/**
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* @brief GPT counter type.
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*/
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typedef uint16_t gptcnt_t;
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typedef uint32_t gptcnt_t;
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/**
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* @brief Driver configuration structure.
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@ -386,6 +386,12 @@ typedef struct {
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*/
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gptcallback_t callback;
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/* End of the mandatory fields.*/
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/**
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* @brief TIM DIER register initialization data.
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* @note The value of this field should normally be equal to zero.
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* @note Only the DMA-related bits can be specified in this field.
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*/
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uint32_t dier;
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} GPTConfig;
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/**
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@ -432,7 +438,7 @@ struct GPTDriver {
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* @notapi
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*/
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#define gpt_lld_change_interval(gptp, interval) \
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((gptp)->tim->ARR = (uint16_t)((interval) - 1))
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((gptp)->tim->ARR = (uint32_t)((interval) - 1))
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/*===========================================================================*/
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/* External declarations. */
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@ -111,7 +111,7 @@ static void icu_lld_serve_interrupt(ICUDriver *icup) {
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uint16_t sr;
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sr = icup->tim->SR;
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sr &= icup->tim->DIER;
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sr &= icup->tim->DIER & STM32_TIM_DIER_IRQ_MASK;
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icup->tim->SR = ~sr;
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if (icup->config->channel == ICU_CHANNEL_1) {
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if ((sr & STM32_TIM_SR_CC1IF) != 0)
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@ -458,7 +458,8 @@ void icu_lld_start(ICUDriver *icup) {
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else {
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/* Driver re-configuration scenario, it must be stopped first.*/
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icup->tim->CR1 = 0; /* Timer disabled. */
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icup->tim->DIER = 0; /* All IRQs disabled. */
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icup->tim->DIER = icup->config->dier &/* DMA-related DIER settings. */
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~STM32_TIM_DIER_IRQ_MASK;
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icup->tim->SR = 0; /* Clear eventual pending IRQs. */
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icup->tim->CCR[0] = 0; /* Comparator 1 disabled. */
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icup->tim->CCR[1] = 0; /* Comparator 2 disabled. */
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@ -621,9 +622,11 @@ void icu_lld_enable(ICUDriver *icup) {
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*/
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void icu_lld_disable(ICUDriver *icup) {
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icup->tim->CR1 = 0; /* Initially stopped. */
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icup->tim->SR = 0; /* Clear pending IRQs (if any). */
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icup->tim->DIER = 0; /* Interrupts disabled. */
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icup->tim->CR1 = 0; /* Initially stopped. */
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icup->tim->SR = 0; /* Clear pending IRQs (if any). */
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/* All interrupts disabled.*/
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icup->tim->DIER &= ~STM32_TIM_DIER_IRQ_MASK;
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}
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#endif /* HAL_USE_ICU */
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@ -291,6 +291,12 @@ typedef struct {
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* @note Only inputs TIMx 1 and 2 are supported.
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*/
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icuchannel_t channel;
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/**
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* @brief TIM DIER register initialization data.
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* @note The value of this field should normally be equal to zero.
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* @note Only the DMA-related bits can be specified in this field.
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*/
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uint32_t dier;
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} ICUConfig;
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/**
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@ -112,7 +112,7 @@ static void pwm_lld_serve_interrupt(PWMDriver *pwmp) {
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uint16_t sr;
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sr = pwmp->tim->SR;
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sr &= pwmp->tim->DIER;
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sr &= pwmp->tim->DIER & STM32_TIM_DIER_IRQ_MASK;
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pwmp->tim->SR = ~sr;
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if ((sr & STM32_TIM_SR_CC1IF) != 0)
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pwmp->config->channels[0].callback(pwmp);
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@ -169,9 +169,8 @@ OSAL_IRQ_HANDLER(STM32_TIM1_CC_HANDLER) {
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OSAL_IRQ_PROLOGUE();
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sr = STM32_TIM1->SR & STM32_TIM1->DIER;
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STM32_TIM1->SR = ~(STM32_TIM_SR_CC1IF | STM32_TIM_SR_CC2IF |
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STM32_TIM_SR_CC3IF | STM32_TIM_SR_CC4IF);
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sr = STM32_TIM1->SR & STM32_TIM1->DIER & STM32_TIM_DIER_IRQ_MASK;
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STM32_TIM1->SR = ~sr;
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if ((sr & STM32_TIM_SR_CC1IF) != 0)
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PWMD1.config->channels[0].callback(&PWMD1);
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if ((sr & STM32_TIM_SR_CC2IF) != 0)
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@ -299,9 +298,8 @@ OSAL_IRQ_HANDLER(STM32_TIM8_CC_HANDLER) {
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OSAL_IRQ_PROLOGUE();
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sr = STM32_TIM8->SR & STM32_TIM8->DIER;
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STM32_TIM8->SR = ~(STM32_TIM_SR_CC1IF | STM32_TIM_SR_CC2IF |
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STM32_TIM_SR_CC3IF | STM32_TIM_SR_CC4IF);
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sr = STM32_TIM8->SR & STM32_TIM8->DIER & STM32_TIM_DIER_IRQ_MASK;
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STM32_TIM8->SR = ~sr;
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if ((sr & STM32_TIM_SR_CC1IF) != 0)
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PWMD8.config->channels[0].callback(&PWMD8);
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if ((sr & STM32_TIM_SR_CC2IF) != 0)
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else {
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/* Driver re-configuration scenario, it must be stopped first.*/
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pwmp->tim->CR1 = 0; /* Timer disabled. */
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pwmp->tim->DIER = 0; /* All IRQs disabled. */
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pwmp->tim->DIER = pwmp->config->dier &/* DMA-related DIER settings. */
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~STM32_TIM_DIER_IRQ_MASK;
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pwmp->tim->SR = 0; /* Clear eventual pending IRQs. */
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pwmp->tim->CCR[0] = 0; /* Comparator 1 disabled. */
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pwmp->tim->CCR[1] = 0; /* Comparator 2 disabled. */
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@ -562,19 +561,20 @@ void pwm_lld_start(PWMDriver *pwmp) {
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}
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#endif /* STM32_PWM_USE_ADVANCED*/
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pwmp->tim->CCER = ccer;
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pwmp->tim->EGR = STM32_TIM_EGR_UG; /* Update event. */
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pwmp->tim->DIER = pwmp->config->callback == NULL ? 0 : STM32_TIM_DIER_UIE;
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pwmp->tim->SR = 0; /* Clear pending IRQs. */
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pwmp->tim->CCER = ccer;
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pwmp->tim->EGR = STM32_TIM_EGR_UG; /* Update event. */
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pwmp->tim->DIER |= pwmp->config->callback == NULL ? 0 : STM32_TIM_DIER_UIE;
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pwmp->tim->SR = 0; /* Clear pending IRQs. */
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#if STM32_PWM_USE_TIM1 || STM32_PWM_USE_TIM8
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#if STM32_PWM_USE_ADVANCED
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pwmp->tim->BDTR = pwmp->config->bdtr | STM32_TIM_BDTR_MOE;
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pwmp->tim->BDTR = pwmp->config->bdtr | STM32_TIM_BDTR_MOE;
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#else
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pwmp->tim->BDTR = STM32_TIM_BDTR_MOE;
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pwmp->tim->BDTR = STM32_TIM_BDTR_MOE;
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#endif
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#endif
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/* Timer configured and started.*/
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pwmp->tim->CR1 = STM32_TIM_CR1_ARPE | STM32_TIM_CR1_URS | STM32_TIM_CR1_CEN;
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pwmp->tim->CR1 = STM32_TIM_CR1_ARPE | STM32_TIM_CR1_URS |
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STM32_TIM_CR1_CEN;
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}
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/**
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@ -345,14 +345,20 @@ typedef struct {
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* @brief TIM CR2 register initialization data.
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* @note The value of this field should normally be equal to zero.
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*/
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uint16_t cr2;
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uint32_t cr2;
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#if STM32_PWM_USE_ADVANCED || defined(__DOXYGEN__)
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/**
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* @brief TIM BDTR (break & dead-time) register initialization data.
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* @note The value of this field should normally be equal to zero.
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*/ \
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uint16_t bdtr;
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uint32_t bdtr;
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#endif
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/**
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* @brief TIM DIER register initialization data.
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* @note The value of this field should normally be equal to zero.
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* @note Only the DMA-related bits can be specified in this field.
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*/
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uint32_t dier;
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} PWMConfig;
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/**
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@ -121,6 +121,17 @@
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#define STM32_TIM_DIER_CC4DE (1U << 12)
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#define STM32_TIM_DIER_COMDE (1U << 13)
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#define STM32_TIM_DIER_TDE (1U << 14)
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#define STM32_TIM_DIER_IRQ_MASK (STM32_TIM_DIER_UIE | \
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STM32_TIM_DIER_CC1IE | \
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STM32_TIM_DIER_CC2IE | \
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STM32_TIM_DIER_CC3IE | \
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STM32_TIM_DIER_CC4IE | \
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STM32_TIM_DIER_COMIE | \
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STM32_TIM_DIER_TIE | \
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STM32_TIM_DIER_BIE | \
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STM32_TIM_DIER_UDE)
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/** @} */
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/**
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