From da3d1eae7b4035fb916e14ba853a5cf2aa0f70cd Mon Sep 17 00:00:00 2001 From: barthess Date: Tue, 20 Sep 2011 07:02:14 +0000 Subject: [PATCH] RTC. Code reorganization to correspond ChibiOS rules. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3356 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- os/hal/platforms/STM32/rtc_lld.c | 45 +++++++++---------- os/hal/platforms/STM32/rtc_lld.h | 8 ---- os/hal/platforms/STM32F1xx/hal_lld_f100.h | 7 +++ os/hal/platforms/STM32F1xx/hal_lld_f103.h | 11 +++++ .../platforms/STM32F1xx/hal_lld_f105_f107.h | 7 +++ testhal/STM32F1xx/RTC/halconf.h | 7 --- testhal/STM32F1xx/RTC/mcuconf.h | 1 + 7 files changed, 47 insertions(+), 39 deletions(-) diff --git a/os/hal/platforms/STM32/rtc_lld.c b/os/hal/platforms/STM32/rtc_lld.c index 941f2429f..465f2f02e 100644 --- a/os/hal/platforms/STM32/rtc_lld.c +++ b/os/hal/platforms/STM32/rtc_lld.c @@ -115,23 +115,14 @@ void rtc_lld_init(void){ uint32_t preload = 0; rccEnableBKPInterface(FALSE); - - /* Ensure that RTC_CNT and RTC_DIV contain actual values after enabling - * clocking on APB1, because these values only update when APB1 functioning.*/ - RTC->CRL &= ~(RTC_CRL_RSF); - while (!(RTC->CRL & RTC_CRL_RSF)) - ; + //RCC->APB1ENR |= (RCC_APB1ENR_BKPEN | RCC_APB1ENR_PWREN); /* enable access to BKP registers */ PWR->CR |= PWR_CR_DBP; /* select clock source */ - RCC->BDCR |= RTC_CLOCK_SOURCE; + RCC->BDCR |= STM32_RTC; - chDbgCheck(((RTC_CLOCK_SOURCE == RCC_BDCR_RTCSEL_LSE) &&\ - (RTC_CLOCK_SOURCE == RCC_BDCR_RTCSEL_LSI) &&\ - (RTC_CLOCK_SOURCE == RCC_BDCR_RTCSEL_HSE)), "No clock source selected"); - - if (RTC_CLOCK_SOURCE == RCC_BDCR_RTCSEL_LSE){ +#if STM32_RTC == STM32_RTC_LSE if (! ((RCC->BDCR & RCC_BDCR_RTCEN) || (RCC->BDCR & RCC_BDCR_LSEON))){ RCC->BDCR |= RCC_BDCR_LSEON; while(!(RCC->BDCR & RCC_BDCR_LSERDY)) @@ -139,26 +130,32 @@ void rtc_lld_init(void){ RCC->BDCR |= RCC_BDCR_RTCEN; } preload = STM32_LSECLK - 1; - } - else if (RTC_CLOCK_SOURCE == RCC_BDCR_RTCSEL_LSI){ + +#elif STM32_RTC == STM32_RTC_LSI RCC->CSR |= RCC_CSR_LSION; while(!(RCC->CSR & RCC_CSR_LSIRDY)) ; - /* According to errata notes we must wait additional 100 uS for stabilization */ + /* According to errata sheet we must wait additional 100 uS for stabilization */ uint32_t tmo = (STM32_SYSCLK / 1000000 ) * 100; while(tmo--) ; RCC->BDCR |= RCC_BDCR_RTCEN; preload = STM32_LSICLK - 1; - } - else if (RTC_CLOCK_SOURCE == RCC_BDCR_RTCSEL_HSE){ - preload = (STM32_HSICLK / 128) - 1; - } - else{ - chDbgPanic("Wrong"); - } - /* Write preload register only if value changed */ +#elif STM32_RTC == STM32_RTC_HSE + preload = (STM32_HSICLK / 128) - 1; + +#else +#error "RTC clock source not selected" +#endif + + /* Ensure that RTC_CNT and RTC_DIV contain actual values after enabling + * clocking on APB1, because these values only update when APB1 functioning.*/ + RTC->CRL &= ~(RTC_CRL_RSF); + while (!(RTC->CRL & RTC_CRL_RSF)) + ; + + /* Write preload register only if its value changed */ if (preload != ((((uint32_t)(RTC->PRLH)) << 16) + RTC->PRLL)){ while(!(RTC->CRL & RTC_CRL_RTOFF)) ; @@ -174,7 +171,7 @@ void rtc_lld_init(void){ /* disable all interrupts and clear all even flags just to be safe */ RTC->CRH &= ~(RTC_CRH_OWIE | RTC_CRH_ALRIE | RTC_CRH_SECIE); - RTC->CRL &= ~(RTC_CRL_SECF | RTC_CRL_ALRF | RTC_CRL_OWF); + RTC->CRL &= ~(RTC_CRL_SECF | RTC_CRL_ALRF | RTC_CRL_OWF); #if RTC_SUPPORTS_CALLBACKS RTCD.alarm_cb = NULL; diff --git a/os/hal/platforms/STM32/rtc_lld.h b/os/hal/platforms/STM32/rtc_lld.h index c2c6f676b..7d7d703f0 100644 --- a/os/hal/platforms/STM32/rtc_lld.h +++ b/os/hal/platforms/STM32/rtc_lld.h @@ -47,14 +47,6 @@ #define RTC_SUPPORTS_CALLBACKS TRUE #endif -/** - * @brief Clock source selecting. LSE by default. - */ -#if !defined(RTC_CLOCK_SOURCE) || defined(__DOXYGEN__) -#define RTC_CLOCK_SOURCE RCC_BDCR_RTCSEL_LSE -#endif - - /*===========================================================================*/ /* Derived constants and error checks. */ /*===========================================================================*/ diff --git a/os/hal/platforms/STM32F1xx/hal_lld_f100.h b/os/hal/platforms/STM32F1xx/hal_lld_f100.h index aad199528..60e42ece4 100644 --- a/os/hal/platforms/STM32F1xx/hal_lld_f100.h +++ b/os/hal/platforms/STM32F1xx/hal_lld_f100.h @@ -228,6 +228,13 @@ #define STM32_MCO STM32_MCO_NOCLOCK #endif +/** + * @brief Clock source selecting. LSI by default. + */ +#if !defined(STM32_RTC) || defined(__DOXYGEN__) +#define STM32_RTC STM32_RTC_LSI +#endif + /*===========================================================================*/ /* Derived constants and error checks. */ /*===========================================================================*/ diff --git a/os/hal/platforms/STM32F1xx/hal_lld_f103.h b/os/hal/platforms/STM32F1xx/hal_lld_f103.h index 4421663a0..f14ab5dc4 100644 --- a/os/hal/platforms/STM32F1xx/hal_lld_f103.h +++ b/os/hal/platforms/STM32F1xx/hal_lld_f103.h @@ -90,6 +90,11 @@ #define STM32_MCO_HSE (6 << 24) /**< HSE clock on MCO pin. */ #define STM32_MCO_PLLDIV2 (7 << 24) /**< PLL/2 clock on MCO pin. */ +#define STM32_RTC_NOCLOCK (0 << 8) /**< No clock */ +#define STM32_RTC_LSE (1 << 8) /**< LSE used as RTC clock */ +#define STM32_RTC_LSI (2 << 8) /**< LSI used as RTC clock */ +#define STM32_RTC_HSE (3 << 8) /**< HSE divided by 128 used as RTC clock */ + /*===========================================================================*/ /* Platform specific friendly IRQ names. */ /*===========================================================================*/ @@ -251,6 +256,12 @@ #define STM32_MCO STM32_MCO_NOCLOCK #endif +/** + * @brief Clock source selecting. LSI by default. + */ +#if !defined(STM32_RTC) || defined(__DOXYGEN__) +#define STM32_RTC STM32_RTC_LSI +#endif /*===========================================================================*/ /* Derived constants and error checks. */ /*===========================================================================*/ diff --git a/os/hal/platforms/STM32F1xx/hal_lld_f105_f107.h b/os/hal/platforms/STM32F1xx/hal_lld_f105_f107.h index 27a840ba8..52c124d2d 100644 --- a/os/hal/platforms/STM32F1xx/hal_lld_f105_f107.h +++ b/os/hal/platforms/STM32F1xx/hal_lld_f105_f107.h @@ -317,6 +317,13 @@ #define STM32_MCO STM32_MCO_NOCLOCK #endif +/** + * @brief Clock source selecting. LSI by default. + */ +#if !defined(STM32_RTC) || defined(__DOXYGEN__) +#define STM32_RTC STM32_RTC_LSI +#endif + /*===========================================================================*/ /* Derived constants and error checks. */ /*===========================================================================*/ diff --git a/testhal/STM32F1xx/RTC/halconf.h b/testhal/STM32F1xx/RTC/halconf.h index 93367c2d2..4dcef13da 100644 --- a/testhal/STM32F1xx/RTC/halconf.h +++ b/testhal/STM32F1xx/RTC/halconf.h @@ -219,13 +219,6 @@ #define RTC_SUPPORTS_CALLBACKS TRUE #endif -/** - * @brief Clock source selecting. LSE by default. - */ -#if !defined(RTC_CLOCK_SOURCE) || defined(__DOXYGEN__) -#define RTC_CLOCK_SOURCE RCC_BDCR_RTCSEL_LSE -#endif - /*===========================================================================*/ /* MAC driver related settings. */ /*===========================================================================*/ diff --git a/testhal/STM32F1xx/RTC/mcuconf.h b/testhal/STM32F1xx/RTC/mcuconf.h index beefe5cba..2c5d4d8be 100644 --- a/testhal/STM32F1xx/RTC/mcuconf.h +++ b/testhal/STM32F1xx/RTC/mcuconf.h @@ -43,6 +43,7 @@ #define STM32_PPRE2 STM32_PPRE2_DIV2 #define STM32_ADCPRE STM32_ADCPRE_DIV4 #define STM32_MCO STM32_MCO_NOCLOCK +#define STM32_RTC STM32_RTC_LSE /* * ADC driver system settings.