Cosmetic changes in SAMA clock init
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@10579 35acf78f-673a-0410-8e92-d51de3d6d3f4
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@ -79,8 +79,9 @@ void sama_clock_init(void) {
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/* Disabling PMC write protection. */
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pmcDisableWP();
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/* Enforces the reset default configuration of clock tree. */
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{
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/*
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* Enforcing the reset default configuration of clock tree.
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*/
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/* Setting Slow Clock source to OSCRC. */
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SCKC->SCKC_CR = 0U;
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@ -110,12 +111,10 @@ void sama_clock_init(void) {
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/* Counter Clock Source to MOSCRC. */
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PMC->CKGR_MCFR &= ~CKGR_MCFR_CCSS;
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}
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/*
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* Main oscillator configuration block.
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*/
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{
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/* Setting Slow clock source. */
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SCKC->SCKC_CR = SAMA_OSC_SEL;
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while ((SAMA_OSC_SEL && !(PMC->PMC_SR & PMC_SR_OSCSELS)) ||
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@ -139,11 +138,8 @@ void sama_clock_init(void) {
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;
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mainf = CKGR_MCFR_MAINF(PMC->CKGR_MCFR);
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/*
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* TODO: check mainf
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* select alternate clock source if mainf is out of range:
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* if the system is configured to use crystal osc,
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* this function should start trying to use crystal osc sources and
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* should switch to alternate sources if mainf is invalid.
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* @TODO: add mainf check and eventual clock source fallback. This mechanism
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* should be activable through a switch.
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*/
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(void)mainf;
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@ -156,12 +152,10 @@ void sama_clock_init(void) {
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#if !SAMA_MOSCRC_ENABLED
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PMC->CKGR_MOR &= ~ CKGR_MOR_MOSCRCEN;
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#endif
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}
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/*
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* PLLA configuration block.
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*/
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{
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pllar = SAMA_PLLA_ONE | CKGR_PLLAR_PLLACOUNT(0x3F);
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#if SAMA_ACTIVATE_PLLA
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pllar |= CKGR_PLLAR_DIVA_BYPASS | SAMA_PLLA_MUL;
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@ -172,12 +166,10 @@ void sama_clock_init(void) {
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while (!(PMC->PMC_SR & PMC_SR_LOCKA))
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; /* Waits until PLLA is locked. */
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#endif
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}
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/*
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* Master clock configuration block.
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*/
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{
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mckr = PMC->PMC_MCKR;
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mckr &= ~PMC_MCKR_CSS_Msk;
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mckr |= SAMA_MCK_SEL;
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@ -196,8 +188,6 @@ void sama_clock_init(void) {
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while (!(PMC->PMC_SR & PMC_SR_MCKRDY))
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; /* Waits until MCK is stable. */
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}
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/* Enabling write protection. */
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pmcEnableWP();
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