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Cosmetic changes in SAMA clock init 

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@10579 35acf78f-673a-0410-8e92-d51de3d6d3f4
This commit is contained in:
Rocco Marco Guglielmi 2017-09-13 19:52:54 +00:00
parent 412b535d51
commit dab0220e94
1 changed files with 5 additions and 15 deletions
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20
os/hal/ports/SAMA/SAMA5D2x/hal_lld.c
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@ -79,8 +79,9 @@ void sama_clock_init(void) {
/* Disabling PMC write protection. */ /* Disabling PMC write protection. */
pmcDisableWP(); pmcDisableWP();
/* Enforces the reset default configuration of clock tree. */ /*
{ * Enforcing the reset default configuration of clock tree.
*/
/* Setting Slow Clock source to OSCRC. */ /* Setting Slow Clock source to OSCRC. */
SCKC->SCKC_CR = 0U; SCKC->SCKC_CR = 0U;
@ -110,12 +111,10 @@ void sama_clock_init(void) {
/* Counter Clock Source to MOSCRC. */ /* Counter Clock Source to MOSCRC. */
PMC->CKGR_MCFR &= ~CKGR_MCFR_CCSS; PMC->CKGR_MCFR &= ~CKGR_MCFR_CCSS;
}
/* /*
* Main oscillator configuration block. * Main oscillator configuration block.
*/ */
{
/* Setting Slow clock source. */ /* Setting Slow clock source. */
SCKC->SCKC_CR = SAMA_OSC_SEL; SCKC->SCKC_CR = SAMA_OSC_SEL;
while ((SAMA_OSC_SEL && !(PMC->PMC_SR & PMC_SR_OSCSELS)) || while ((SAMA_OSC_SEL && !(PMC->PMC_SR & PMC_SR_OSCSELS)) ||
@ -139,11 +138,8 @@ void sama_clock_init(void) {
; ;
mainf = CKGR_MCFR_MAINF(PMC->CKGR_MCFR); mainf = CKGR_MCFR_MAINF(PMC->CKGR_MCFR);
/* /*
* TODO: check mainf * @TODO: add mainf check and eventual clock source fallback. This mechanism
* select alternate clock source if mainf is out of range: * should be activable through a switch.
* if the system is configured to use crystal osc,
* this function should start trying to use crystal osc sources and
* should switch to alternate sources if mainf is invalid.
*/ */
(void)mainf; (void)mainf;
@ -156,12 +152,10 @@ void sama_clock_init(void) {
#if !SAMA_MOSCRC_ENABLED #if !SAMA_MOSCRC_ENABLED
PMC->CKGR_MOR &= ~ CKGR_MOR_MOSCRCEN; PMC->CKGR_MOR &= ~ CKGR_MOR_MOSCRCEN;
#endif #endif
}
/* /*
* PLLA configuration block. * PLLA configuration block.
*/ */
{
pllar = SAMA_PLLA_ONE | CKGR_PLLAR_PLLACOUNT(0x3F); pllar = SAMA_PLLA_ONE | CKGR_PLLAR_PLLACOUNT(0x3F);
#if SAMA_ACTIVATE_PLLA #if SAMA_ACTIVATE_PLLA
pllar |= CKGR_PLLAR_DIVA_BYPASS | SAMA_PLLA_MUL; pllar |= CKGR_PLLAR_DIVA_BYPASS | SAMA_PLLA_MUL;
@ -172,12 +166,10 @@ void sama_clock_init(void) {
while (!(PMC->PMC_SR & PMC_SR_LOCKA)) while (!(PMC->PMC_SR & PMC_SR_LOCKA))
; /* Waits until PLLA is locked. */ ; /* Waits until PLLA is locked. */
#endif #endif
}
/* /*
* Master clock configuration block. * Master clock configuration block.
*/ */
{
mckr = PMC->PMC_MCKR; mckr = PMC->PMC_MCKR;
mckr &= ~PMC_MCKR_CSS_Msk; mckr &= ~PMC_MCKR_CSS_Msk;
mckr |= SAMA_MCK_SEL; mckr |= SAMA_MCK_SEL;
@ -196,8 +188,6 @@ void sama_clock_init(void) {
while (!(PMC->PMC_SR & PMC_SR_MCKRDY)) while (!(PMC->PMC_SR & PMC_SR_MCKRDY))
; /* Waits until MCK is stable. */ ; /* Waits until MCK is stable. */
}
/* Enabling write protection. */ /* Enabling write protection. */
pmcEnableWP(); pmcEnableWP();