Fixed bugs #445 and #446.

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@6560 35acf78f-673a-0410-8e92-d51de3d6d3f4

os/hal/include/adc.h

@@ -224,16 +224,8 @@ typedef enum {
     adc_lld_stop_conversion(adcp);                                          \
     if ((adcp)->grpp->end_cb != NULL) {                                     \
       (adcp)->state = ADC_COMPLETE;                                         \
-      if ((adcp)->depth > 1) {                                              \
+      /* Invoke the callback passing the whole buffer.*/                    \
-        /* Invokes the callback passing the 2nd half of the buffer.*/       \
+      (adcp)->grpp->end_cb(adcp, (adcp)->samples, (adcp)->depth);           \
-        size_t half = (adcp)->depth / 2;                                    \
-        size_t half_index = half * (adcp)->grpp->num_channels;              \
-        (adcp)->grpp->end_cb(adcp, (adcp)->samples + half_index, half);     \
-      }                                                                     \
-      else {                                                                \
-        /* Invokes the callback passing the whole buffer.*/                 \
-        (adcp)->grpp->end_cb(adcp, (adcp)->samples, (adcp)->depth);         \
-      }                                                                     \
       if ((adcp)->state == ADC_COMPLETE) {                                  \
         (adcp)->state = ADC_READY;                                          \
         (adcp)->grpp = NULL;                                                \

os/hal/platforms/STM32F0xx/adc_lld.c

@@ -80,14 +80,14 @@ static void adc_lld_serve_rx_interrupt(ADCDriver *adcp, uint32_t flags) {
     /* It is possible that the conversion group has already be reset by the
        ADC error handler, in this case this interrupt is spurious.*/
     if (adcp->grpp != NULL) {
-      if ((flags & STM32_DMA_ISR_HTIF) != 0) {
-        /* Half transfer processing.*/
-        _adc_isr_half_code(adcp);
-      }
       if ((flags & STM32_DMA_ISR_TCIF) != 0) {
         /* Transfer complete processing.*/
         _adc_isr_full_code(adcp);
       }
+      else if ((flags & STM32_DMA_ISR_HTIF) != 0) {
+        /* Half transfer processing.*/
+        _adc_isr_half_code(adcp);
+      }
     }
   }
 }
@@ -254,11 +254,11 @@ void adc_lld_start_conversion(ADCDriver *adcp) {
   mode = adcp->dmamode;
   if (grpp->circular) {
     mode |= STM32_DMA_CR_CIRC;
-  }
+    if (adcp->depth > 1) {
-  if (adcp->depth > 1) {
+      /* If circular buffer depth > 1, then the half transfer interrupt
-    /* If the buffer depth is greater than one then the half transfer interrupt
+         is enabled in order to allow streaming processing.*/
-       interrupt is enabled in order to allows streaming processing.*/
+      mode |= STM32_DMA_CR_HTIE;
-    mode |= STM32_DMA_CR_HTIE;
+    }
   }
   dmaStreamSetMemory0(adcp->dmastp, adcp->samples);
   dmaStreamSetTransactionSize(adcp->dmastp, (uint32_t)grpp->num_channels *

os/hal/platforms/STM32F1xx/adc_lld.c

@@ -63,14 +63,14 @@ static void adc_lld_serve_rx_interrupt(ADCDriver *adcp, uint32_t flags) {
     _adc_isr_error_code(adcp, ADC_ERR_DMAFAILURE);
   }
   else {
-    if ((flags & STM32_DMA_ISR_HTIF) != 0) {
-      /* Half transfer processing.*/
-      _adc_isr_half_code(adcp);
-    }
     if ((flags & STM32_DMA_ISR_TCIF) != 0) {
       /* Transfer complete processing.*/
       _adc_isr_full_code(adcp);
     }
+    else if ((flags & STM32_DMA_ISR_HTIF) != 0) {
+      /* Half transfer processing.*/
+      _adc_isr_half_code(adcp);
+    }
   }
 }
 
@@ -181,23 +181,22 @@ void adc_lld_stop(ADCDriver *adcp) {
  * @notapi
  */
 void adc_lld_start_conversion(ADCDriver *adcp) {
-  uint32_t mode, n, cr2;
+  uint32_t mode, cr2;
   const ADCConversionGroup *grpp = adcp->grpp;
 
   /* DMA setup.*/
   mode = adcp->dmamode;
-  if (grpp->circular)
+  if (grpp->circular) {
     mode |= STM32_DMA_CR_CIRC;
-  if (adcp->depth > 1) {
+    if (adcp->depth > 1) {
-    /* If the buffer depth is greater than one then the half transfer interrupt
+      /* If circular buffer depth > 1, then the half transfer interrupt
-       interrupt is enabled in order to allows streaming processing.*/
+         is enabled in order to allow streaming processing.*/
-    mode |= STM32_DMA_CR_HTIE;
+      mode |= STM32_DMA_CR_HTIE;
-    n = (uint32_t)grpp->num_channels * (uint32_t)adcp->depth;
+    }
   }
-  else
-    n = (uint32_t)grpp->num_channels;
   dmaStreamSetMemory0(adcp->dmastp, adcp->samples);
-  dmaStreamSetTransactionSize(adcp->dmastp, n);
+  dmaStreamSetTransactionSize(adcp->dmastp, (uint32_t)grpp->num_channels *
+                                            (uint32_t)adcp->depth);
   dmaStreamSetMode(adcp->dmastp, mode);
   dmaStreamEnable(adcp->dmastp);
 

os/hal/platforms/STM32F30x/adc_lld.c

@@ -194,14 +194,14 @@ static void adc_lld_serve_dma_interrupt(ADCDriver *adcp, uint32_t flags) {
     /* It is possible that the conversion group has already be reset by the
        ADC error handler, in this case this interrupt is spurious.*/
     if (adcp->grpp != NULL) {
-      if ((flags & STM32_DMA_ISR_HTIF) != 0) {
-        /* Half transfer processing.*/
-        _adc_isr_half_code(adcp);
-      }
       if ((flags & STM32_DMA_ISR_TCIF) != 0) {
         /* Transfer complete processing.*/
         _adc_isr_full_code(adcp);
       }
+      else if ((flags & STM32_DMA_ISR_HTIF) != 0) {
+        /* Half transfer processing.*/
+        _adc_isr_half_code(adcp);
+      }
     }
   }
 }
@@ -478,14 +478,14 @@ void adc_lld_start_conversion(ADCDriver *adcp) {
 #else
     cfgr |= ADC_CFGR_DMACFG_CIRCULAR;
 #endif
+    if (adcp->depth > 1) {
+      /* If circular buffer depth > 1, then the half transfer interrupt
+         is enabled in order to allow streaming processing.*/
+      dmamode |= STM32_DMA_CR_HTIE;
+    }
   }
 
   /* DMA setup.*/
-  if (adcp->depth > 1) {
-    /* If the buffer depth is greater than one then the half transfer interrupt
-       interrupt is enabled in order to allows streaming processing.*/
-    dmamode |= STM32_DMA_CR_HTIE;
-  }
   dmaStreamSetMemory0(adcp->dmastp, adcp->samples);
 #if STM32_ADC_DUAL_MODE
   dmaStreamSetTransactionSize(adcp->dmastp, ((uint32_t)grpp->num_channels/2) *

os/hal/platforms/STM32F37x/adc_lld.c

@@ -157,14 +157,14 @@ static void adc_lld_serve_dma_interrupt(ADCDriver *adcp, uint32_t flags) {
     /* It is possible that the conversion group has already be reset by the
        ADC error handler, in this case this interrupt is spurious.*/
     if (adcp->grpp != NULL) {
-      if ((flags & STM32_DMA_ISR_HTIF) != 0) {
-        /* Half transfer processing.*/
-        _adc_isr_half_code(adcp);
-      }
       if ((flags & STM32_DMA_ISR_TCIF) != 0) {
         /* Transfer complete processing.*/
         _adc_isr_full_code(adcp);
       }
+      else if ((flags & STM32_DMA_ISR_HTIF) != 0) {
+        /* Half transfer processing.*/
+        _adc_isr_half_code(adcp);
+      }
     }
   }
 }
@@ -528,11 +528,11 @@ void adc_lld_start_conversion(ADCDriver *adcp) {
   mode = adcp->dmamode;
   if (grpp->circular) {
     mode |= STM32_DMA_CR_CIRC;
-  }
+    if (adcp->depth > 1) {
-  if (adcp->depth > 1) {
+      /* If circular buffer depth > 1, then the half transfer interrupt
-    /* If the buffer depth is greater than one then the half transfer interrupt
+         is enabled in order to allow streaming processing.*/
-       interrupt is enabled in order to allows streaming processing.*/
+      mode |= STM32_DMA_CR_HTIE;
-    mode |= STM32_DMA_CR_HTIE;
+    }
   }
   dmaStreamSetMemory0(adcp->dmastp, adcp->samples);
   dmaStreamSetTransactionSize(adcp->dmastp,

os/hal/platforms/STM32F4xx/adc_lld.c

@@ -85,14 +85,14 @@ static void adc_lld_serve_rx_interrupt(ADCDriver *adcp, uint32_t flags) {
     /* It is possible that the conversion group has already be reset by the
        ADC error handler, in this case this interrupt is spurious.*/
     if (adcp->grpp != NULL) {
-      if ((flags & STM32_DMA_ISR_HTIF) != 0) {
-        /* Half transfer processing.*/
-        _adc_isr_half_code(adcp);
-      }
       if ((flags & STM32_DMA_ISR_TCIF) != 0) {
         /* Transfer complete processing.*/
         _adc_isr_full_code(adcp);
       }
+      else if ((flags & STM32_DMA_ISR_HTIF) != 0) {
+        /* Half transfer processing.*/
+        _adc_isr_half_code(adcp);
+      }
     }
   }
 }
@@ -324,11 +324,11 @@ void adc_lld_start_conversion(ADCDriver *adcp) {
   mode = adcp->dmamode;
   if (grpp->circular) {
     mode |= STM32_DMA_CR_CIRC;
-  }
+    if (adcp->depth > 1) {
-  if (adcp->depth > 1) {
+      /* If circular buffer depth > 1, then the half transfer interrupt
-    /* If the buffer depth is greater than one then the half transfer interrupt
+         is enabled in order to allow streaming processing.*/
-       interrupt is enabled in order to allows streaming processing.*/
+      mode |= STM32_DMA_CR_HTIE;
-    mode |= STM32_DMA_CR_HTIE;
+    }
   }
   dmaStreamSetMemory0(adcp->dmastp, adcp->samples);
   dmaStreamSetTransactionSize(adcp->dmastp, (uint32_t)grpp->num_channels *

os/hal/platforms/STM32L1xx/adc_lld.c

@@ -66,14 +66,14 @@ static void adc_lld_serve_rx_interrupt(ADCDriver *adcp, uint32_t flags) {
     /* It is possible that the conversion group has already be reset by the
        ADC error handler, in this case this interrupt is spurious.*/
     if (adcp->grpp != NULL) {
-      if ((flags & STM32_DMA_ISR_HTIF) != 0) {
-        /* Half transfer processing.*/
-        _adc_isr_half_code(adcp);
-      }
       if ((flags & STM32_DMA_ISR_TCIF) != 0) {
         /* Transfer complete processing.*/
         _adc_isr_full_code(adcp);
       }
+      else if ((flags & STM32_DMA_ISR_HTIF) != 0) {
+        /* Half transfer processing.*/
+        _adc_isr_half_code(adcp);
+      }
     }
   }
 }
@@ -206,11 +206,11 @@ void adc_lld_start_conversion(ADCDriver *adcp) {
   mode = adcp->dmamode;
   if (grpp->circular) {
     mode |= STM32_DMA_CR_CIRC;
-  }
+    if (adcp->depth > 1) {
-  if (adcp->depth > 1) {
+      /* If circular buffer depth > 1, then the half transfer interrupt
-    /* If the buffer depth is greater than one then the half transfer interrupt
+         is enabled in order to allow streaming processing.*/
-       interrupt is enabled in order to allows streaming processing.*/
+      mode |= STM32_DMA_CR_HTIE;
-    mode |= STM32_DMA_CR_HTIE;
+    }
   }
   dmaStreamSetMemory0(adcp->dmastp, adcp->samples);
   dmaStreamSetTransactionSize(adcp->dmastp, (uint32_t)grpp->num_channels *

readme.txt

@@ -89,6 +89,10 @@
 *****************************************************************************
 
 *** 2.7.0 ***
+- FIX: Fixed spurious half buffer callback in STM32 ADC drivers (bug #446)
+  (backported to 2.4.6 and 2.6.2).
+- FIX: Fixed callbacks changes to the ADC high level driver (bug #445)
+  (backported to 2.4.6 and 2.6.2).
 - FIX: Fixed wrong definition in STM32F37x ADC driver (bug #444)(backported
   to 2.6.2).
 - FIX: Fixed wrong CORTEX_PRIORITY_PENDSV value (bug #443)(backported to