From dba2dd7996ca21159f5e7bc9771fd738c04febba Mon Sep 17 00:00:00 2001
From: Giovanni Di Sirio <gdisirio@gmail.com>
Date: Sat, 24 Apr 2021 13:25:41 +0000
Subject: [PATCH] Missing NO_INIT check.

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@14297 27425a3e-05d8-49a3-a47f-9c15f0e5edd8
---
 os/hal/ports/STM32/STM32L4xx+/hal_lld.c | 4 +++-
 os/hal/ports/STM32/STM32L4xx/hal_lld.c  | 4 +++-
 2 files changed, 6 insertions(+), 2 deletions(-)

diff --git a/os/hal/ports/STM32/STM32L4xx+/hal_lld.c b/os/hal/ports/STM32/STM32L4xx+/hal_lld.c
index ac32d95c5..190597627 100644
--- a/os/hal/ports/STM32/STM32L4xx+/hal_lld.c
+++ b/os/hal/ports/STM32/STM32L4xx+/hal_lld.c
@@ -121,6 +121,7 @@ void hal_lld_init(void) {
  */
 void stm32_clock_init(void) {
 
+#if !STM32_NO_INIT
   /* Reset of all peripherals.
      Note, GPIOs are not reset because initialized before this point in
      board files.*/
@@ -140,7 +141,7 @@ void stm32_clock_init(void) {
 
   /* SYSCFG clock enabled here because it is a multi-functional unit shared
      among multiple drivers.*/
-  rccEnableAPB2(RCC_APB2ENR_SYSCFGEN, true);
+  rccEnableAPB2(RCC_APB2ENR_SYSCFGEN, false);
 
   /* Core voltage setup, backup domain access enabled and left open.*/
   PWR->CR1 = STM32_VOS | PWR_CR1_DBP;
@@ -239,6 +240,7 @@ void stm32_clock_init(void) {
            (STM32_FLASHBITS & FLASH_ACR_LATENCY_Msk)) {
     }
   }
+#endif /* STM32_NO_INIT */
 }
 
 /** @} */
diff --git a/os/hal/ports/STM32/STM32L4xx/hal_lld.c b/os/hal/ports/STM32/STM32L4xx/hal_lld.c
index 8f5705c64..c6f16a5f1 100644
--- a/os/hal/ports/STM32/STM32L4xx/hal_lld.c
+++ b/os/hal/ports/STM32/STM32L4xx/hal_lld.c
@@ -121,6 +121,7 @@ void hal_lld_init(void) {
  */
 void stm32_clock_init(void) {
 
+#if !STM32_NO_INIT
   /* Reset of all peripherals.
      Note, GPIOs are not reset because initialized before this point in
      board files.*/
@@ -140,7 +141,7 @@ void stm32_clock_init(void) {
 
   /* SYSCFG clock enabled here because it is a multi-functional unit shared
      among multiple drivers.*/
-  rccEnableAPB2(RCC_APB2ENR_SYSCFGEN, true);
+  rccEnableAPB2(RCC_APB2ENR_SYSCFGEN, false);
 
   /* Core voltage setup, backup domain access enabled and left open.*/
   PWR->CR1 = STM32_VOS | PWR_CR1_DBP;
@@ -238,6 +239,7 @@ void stm32_clock_init(void) {
            (STM32_FLASHBITS & FLASH_ACR_LATENCY_Msk)) {
     }
   }
+#endif /* STM32_NO_INIT */
 }
 
 /** @} */